TWI804217B - Memory device - Google Patents

Abstract

A memory device includes a stacked structure, a circuit structure, and a vertical contact. The stacked structure includes conductive layers and first insulating layers alternately stacked along a first direction, a first array region, a second array region, and a connection region. The first array region includes first channel layers extending along the first direction. The second array region includes second channel layers extending along the first direction. The connection region is disposed between the first array region and the second array region, and includes a staircase region, an opening region, a bottom isolating member and a common wall. The opening region extends along the first direction and has an isolating sidewall. The isolating sidewall electrically isolates the conductive layers from the opening region. The staircase region is adjacent to a first side of the opening region, and the common wall is adjacent to a second side of the opening region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region.

Description

memory device

The present invention relates to a memory device, and in particular to a three-dimensional memory device.

Recently, people's demand for memory devices continues to increase. With more and more applications now, how to provide memory devices with higher storage capacity has become one of the important research directions, so the development of three-dimensional memory devices is becoming more and more urgent.

The present invention relates to a memory device, and in particular to a three-dimensional memory device. The three-dimensional memory device of the present invention can provide a memory device with a high storage capacity, and compared with the comparative example in which a stepped area is provided on one side of the memory array area, the memory device of the present invention can have improved operating speed.

According to an embodiment of the present invention, a memory device is provided. The memory device includes a stack structure, a circuit structure and a vertical contact. The laminated structure includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked along a first direction, a first array area, a second array area and a connection area. The first array area includes a plurality of first channel pillars extending along a first direction. The second array area includes a plurality of second channel pillars extending along the first direction. The connection area is set in the first array area Between the second array area, the connection area includes a stepped area, an untreated area, a bottom spacer and a shared wall. The untreated area extends along the first direction and has an isolation side wall, the isolation side wall electrically isolates the conductive layer from the untreated area, the stepped area is adjacent to a first side of the untreated area, and the shared wall is adjacent to a first side of the untreated area On the second side, the first side is opposite to the second side, and part of the conductive layer extends continuously in the step area, the first array area, the common wall and the second array area respectively. The bottom isolator extends along the first direction to separate the conductive layer at a bottom portion of the stacked structure and defines a ground selection line, and the bottom isolator is in contact with the isolation sidewall. The circuit structure is disposed under the connection area. The vertical contact passes through the untreated area and electrically connects the circuit structure to the corresponding conductive layer.

According to yet another embodiment of the present invention, a memory device is provided. The memory device includes a stack structure, a circuit structure and a vertical contact. The stacked structure includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked along a first direction, a first array region, a second array region, a connection region, a plurality of trenches and a plurality of top spacers . The first array area includes a plurality of first channel pillars extending along a first direction. The second array area includes a plurality of second channel pillars extending along the first direction. The connection area is disposed between the first array area and the second array area, wherein the connection area includes a stepped area, an unprocessed area, a bottom spacer and a shared wall. The trench extends along a first direction and passes through the stacked structure, and extends along a second direction perpendicular to the first direction, wherein the trench includes a first trench, a second trench, a third trench, and a fourth trench groove and the fifth groove. The second groove is disposed between the first groove and the third groove. The fourth groove is disposed between the third groove and the fifth groove. top spacer along The first direction extends through the corresponding conductive layer disposed in the top portion of the stacked structure. The first trench, the third trench and the fifth trench respectively extend continuously along the second direction to divide the stacked structure into a first block and a second block. The second trench and the top spacer on the opposite side of the second trench divide the first block into 4 sub-blocks. The fourth trench and top spacers on opposite sides of the fourth trench divide the second block into 4 sub-blocks. In each of the first block and the second block, the stepped area is adjacent to a first side of the untreated area, the shared wall is adjacent to a second side of the untreated area, the first side is opposite to the second side, And part of the conductive layer extends continuously in the step area, the first array area, the common wall and the second array area. The untreated area extends along the first direction and has an isolation sidewall, and the isolation sidewall electrically isolates the conductive layer from the untreated area. The bottom isolator extends along the first direction to separate the conductive layer at a bottom portion of the stacked structure and defines a ground selection line, and the bottom isolator is in contact with the isolation sidewall. The circuit structure is disposed under the connection area. The vertical contact passes through the untreated area and electrically connects the circuit structure to the corresponding conductive layer.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

10: Memory device

112: insulating material

120: Bottom plate

122: The first insulating layer

124: conductive layer

125: Second insulating layer

126,1261~1264,128,1281~1283: side connectors

132: the first conductive connector

134: the second conductive connector

136: circuit contact

BK1, BK2: block

BK11~BK14, BK21~BK24: sub-blocks

CR: connection region

CT: circuit structure

CW: Common Wall

DI: first direction

DII: second direction

DIII: Third Direction

GSLC: bottom spacer

GSLN, GSLN1~GSLN4: grounding selection line contacts

GSLR: Bottom Landing Zone

HP1: the first array area

HP2: second array area

L1, L2: Length

LR: Landing Pad

LT: Groove

LT1: first groove

LT2: second groove

LT3: the third groove

LT4: fourth groove

LT5: fifth groove

LTI: Conductive Strip

LTO: Insulated side walls

MI: ladder structure

OP: untreated area

OP1: The first untreated area

OP2: The second untreated area

OW: isolated side wall

S1, S2: side

SSLC: top spacer

SSLN,SSLN1~SSLN8: Tandem selection line contacts

SSLR: top landing zone

ST: step area

T1: laminated structure

TAC: vertical contact

VC1: the first channel column

VC2: second channel column

WLN: word line contact

X1, X1', X2, X2', X3, X3', Y1, Y1', Y2, Y2', Y3, Y3', Y4, Y4': end points of hatching

Figure 1 shows a top view of a memory device according to an embodiment of the present invention; Figure 2 shows a partially enlarged view of Figure 1; Figure 3 shows a partial perspective view of a memory device according to an embodiment of the present invention picture; Figure 4 shows a cross-sectional view along the line X1-X1' in Figure 2; Figure 5 shows a cross-sectional view along the line X2-X2' in Figure 2; Figure 6 shows a cross-sectional view along the line X2-X2' in Figure 2; Sectional view of the connection line X3-X3' in Figure 2; Figure 7 shows a cross-sectional view along the line Y1-Y1' in Figure 2; Figure 8 shows a cross-sectional view along the line Y2-Y2' in Figure 2 Figure 9 shows a cross-sectional view along the line Y3-Y3' in Figure 2; and Figure 10 shows a cross-sectional view along the line Y4-Y4' in Figure 2.

In the following detailed description, for purposes of explanation, various specific details are provided to provide a general understanding of the embodiments of the present disclosure. However, it is understood that one or more embodiments can be practiced without these specific details. In other instances, well-known structures and elements are shown schematically in order to simplify the drawings.

The singular forms "a" and "the" used in the specification of this case and the appended claims include plural expressions, unless there is a clear instruction in the text. For example, the expression "a vertical contact" includes a plurality of such vertical contacts.

The memory device in this case can be applied to 3D NAND memory, 3D NOR memory, 3D AND memory or other suitable memories.

FIG. 1 shows a top view of a memory device 10 according to an embodiment of the present invention. FIG. 2 shows a partially enlarged view of FIG. 1, especially for a more detailed description of the connection region CR. Figures 1-2 are, for example, corresponding to the second direction DII and the third direction The plane formed by DIII. FIG. 3 shows a partial perspective view of a memory device 10 according to an embodiment of the present invention. Figure 4 shows a cross-sectional view along the line X1-X1' in Figure 2. Figure 5 shows a cross-sectional view along the line X2-X2' in Figure 2. Figure 6 shows a cross-sectional view along the line X3-X3' in Figure 2. Figures 4 to 6 respectively correspond to planes formed by the first direction DI and the second direction DII, for example. Figure 7 shows a cross-sectional view along the line Y1-Y1' in Figure 2. Figure 8 shows a cross-sectional view along the line Y2-Y2' in Figure 2. Figure 9 shows a cross-sectional view along the line Y3-Y3' in Figure 2. Figure 10 shows a cross-sectional view along the line Y4-Y4' in Figure 2. FIGS. 7-10 respectively correspond to planes formed by the first direction DI and the third direction DIII, for example. In this embodiment, the first direction DI, the second direction DII and the third direction DIII are perpendicular to each other, but the present invention is not limited thereto, as long as the first direction DI, the second direction DII and the third direction DIII are mutually perpendicular Just stagger.

Please refer to FIGS. 1-3 at the same time, the memory device 10 includes a stacked structure T1, a plurality of circuit structures CT and a plurality of vertical contacts TAC. The stacked structure T1 includes a base plate 120 (shown in FIG. 4 ) and a plurality of conductive layers 124 and a plurality of conductive layers 124 alternately stacked on the upper surface of the base plate 120 (shown in FIG. 4 ) along a first direction DI. The first insulating layer 122 . Moreover, from the top view of FIGS. 1-2 , the stacked structure T1 includes a first array region HP1 , a second array region HP2 and a connection region CR. The first array area HP1 includes a plurality of first channel pillars VC1 extending along the first direction DI. The second array area HP2 includes a plurality of second channel pillars VC2 extending along the first direction DI. In at least one embodiment, the first array area HP1 and the second array area HP2 are respectively a first memory array including a plurality of memory strings and a second memory array. The connecting region CR is disposed between the first array region HP1 and the second array region HP2. The conductive layer 124 at the bottom part of the stacked structure T1 (i.e. as a ground selection line), the conductive layer 124 at the middle part (i.e. as a word line) and the conductive layer 124 at the top part (i.e. as a serial selection line) are stacked in sequence on the base plate 120 (shown in FIG. 4 ). Compared with the comparative example in which the connecting region in one block is only arranged on a single side of the array region, since the connecting region CR in this embodiment is arranged between the first array region HP1 and the second array region HP2, so that The distance of the current/voltage transmission path between the circuit structure CT and the first array region HP1 or between the circuit structure CT and the second array region HP2 can be shortened, so the resistance and capacitance can be reduced, thereby increasing the operating speed of the memory device 10 .

In one example, the (first or second) channel column VC1 or VC2 may include multiple layers, and the multiple layers may include a tunneling layer, a charge trapping layer, and a blocking layer. layer). The tunneling layer may include silicon oxide, or a silicon oxide/silicon nitride combination (such as oxide/nitride/oxide (Oxide/Nitride/Oxide or ONO)). The charge trapping layer may include silicon nitride (SiN) or other materials capable of trapping charges. The barrier layer may include silicon oxide, aluminum oxide, and/or combinations of these materials. Multiple layers may be formed on the inner surfaces of the holes penetrating down through alternate pairs of conductive layers 124 (gate layers or word line layers) and the first insulating layer 122, and polysilicon may be filled in the middle of the holes. The filling material (eg, multilayer and polysilicon) in each (first or second) channel pillar intersecting the conductive layer 124 can form a series of memory cells along the first direction DI. Each channel column (VC1 or VC2) includes a string of memory cells connected in series in NAND type.

As shown in FIG. 1 , the memory device 10 further includes a plurality of trenches LT and a plurality of top spacers SSLC. In this embodiment, the trench LT extends through the stacked structure T1 along the first direction DI, extends along the second direction DII, and includes a second One trench ~ fifth trench LT1 ~ LT5, each trench (LT1 ~ LT5) has a side surface (or wall) and an interior, a dielectric film (such as oxide) covers the side surface (or wall), and Adjacent layers (such as the conductive layer 124 ) are isolated, and a conductive material (such as tungsten) is filled inside. The first to fifth trenches LT1 to LT5 are sequentially arranged along the third direction DIII and separated from each other, that is, the second trench LT2 is located between the first trench LT1 and the third trench LT3, and the fourth trench LT2 is located between the first trench LT1 and the third trench LT3. The trench LT4 is located between the third trench LT3 and the fifth trench LT5 , but the number of the trenches of the present invention is not limited thereto.

As shown in Figures 2 and 10, the top spacer SSLC extends through the corresponding conductive layer 124 at the top portion of the stacked structure T1 along the first direction DI, and is respectively continuous from the first array region HP1 along the second direction DII. extending to the edge portion of the connection region CR adjacent to the first array region HP1. The top spacer SSLC continuously extends from an edge portion of the connection region CR adjacent to the second array region HP2 to the second array region HP2 along the second direction DII to define a serial selection line. Each top spacer SSLC includes an insulating material such as an oxide to isolate the conductive layer 124 at opposite sides of each top spacer SSLC disposed in the top portion of the stacked structure T1. The above-mentioned edge part is also called the top landing area SSLR (as shown in Figure 2). The first trench LT1 , the third trench LT3 and the fifth trench LT5 respectively extend continuously along the second direction DII, and separate the stacked structure T1 into two blocks BK1 and BK2 . The second trench LT2 and the fourth trench LT4 extend discontinuously along the second direction DII respectively. The second trench LT2 and the top spacer SSLC located on the opposite side of the second trench LT2 separate the block BK1 into four sub-blocks BK11 - BK14 . Similarly, the fourth trench LT4 and the top spacer SSLC located on the opposite side of the fourth trench LT4 divide the block BK2 into four sub-blocks BK21 - BK24 . The blocks BK1 and BK2 can be independently controlled and operated respectively.

As shown in FIG. 2, the connection area CR includes a plurality of stepped areas ST, a plurality of stepped structures MI, a plurality of untreated areas OP (OP1 and OP2), a plurality of bottom spacers GSLC and a plurality of common walls CW. Each ladder structure MI extends from the block BK1 to the block BK2 along the third direction DIII. In the top view, the stair regions ST in the blocks BK1 and BK2 overlap the corresponding stair structures MI.

In each block (BK1 or BK2), the untreated area OP (OP1 or OP2) extends along the first direction DI and has an isolation sidewall OW which surrounds the untreated area OP (OP1 and OP2), and The conductive layer 124 is electrically isolated from the untreated area OP ( OP1 and OP2 ). In each block ( BK1 or BK2 ), the first untreated area OP1 and the second untreated area OP2 are connected by one side of the isolation sidewall OW. The side of the isolation sidewall OW is adjacent to the step region ST and extends along the second direction DII. The isolation sidewall OW extends and passes through the stacked structure T1 along the first direction DI. The isolation sidewall OW is configured to prevent the second insulating layer 125 in the unprocessed region OP ( OP1 and OP2 ) from being removed during a gate replacement process for fabricating the memory device 10 . That is, the gate replacement process is not performed in the untreated areas OP ( OP1 and OP2 ). The untreated region OP ( OP1 and OP2 ) includes a stack of alternating pairs of first insulating layers 122 (eg, oxide) and second insulating layers 125 (eg, nitride), as shown in FIG. 5 . As shown in FIG. 5 , the stacks of alternating pairs of first insulating layers 122 and second insulating layers 125 in the untreated region OP ( OP1 and OP2 ) are electrically isolated from the conductive layer 124 .

Please refer back to FIG. 2 , in the block BK2 , the step region ST is located between the first unprocessed region OP1 and the third trench LT3 . The common wall CW is located between the first unprocessed area OP1 and the fifth trench LT5, and is also located between the second unprocessed area OP2 and the fifth trench LT5. Similarly, in the block BK1, the stepped area ST is located in the first Between the processing area OP1 and the third trench LT3. The common wall CW is located between the first unprocessed area OP1 and the first trench LT1, and is also located between the second unprocessed area OP2 and the first trench LT1. As shown in Figures 1 and 2, in each block BK1 and BK2, the stepped area ST is adjacent to the first side S1 or S2 of the untreated area OP, and the common wall CW is adjacent to the second side S2 of the untreated area OP Or S1, the first side S1 or S2 is opposite to the second side S2 or S1. For example, in the block BK2, the step area ST is adjacent to the first side (such as S1) of the untreated area OP (such as the first untreated area OP1), and the common wall CW is adjacent to the untreated area OP (such as the first untreated area OP1). The second side (eg S2) of the area OP1), the first side (eg S1) is opposite to the second side (eg S2). In the block BK1, the step area ST is adjacent to the first side (such as S2) of the untreated area OP (such as the second untreated area OP2), and the common wall CW is adjacent to the untreated area OP (such as the second untreated area OP2). ), the second side (eg S1 ), the first side (eg S2 ) relative to the second side (eg S1 ).

FIG. 3 shows a partial perspective view of a block BK2 of the memory device 10 according to an embodiment of the present invention. As shown in Figures 1 and 3, the conductive layer 124 in the middle of the stacked structure T1 (that is, as a word line) extends continuously in the step area ST, the top landing area SSLR (details are described later), and the first array area. HP1, the common wall CW and the second array area HP2. Since the second trench LT2 and the fourth trench LT4 are not connected to the isolation sidewall OW of the first unprocessed area OP1 and the second unprocessed area OP2, in the same block (block BK1 or block BK2) of the same level Each conductive layer 124 serving as a word line is an integral structure in the step region ST, the first array region HP, the top landing region SSLR (details will be described later), the common wall CW and the second array region HP2. Therefore, the conductive layer 124 serving as the word line at the same level in the first array area HP1 and the second array area HP2 can be electrically connected to each other. For example, as shown in FIG. 1, in the block BK2, the sub-blocks BK21~BK24 on the opposite sides of the fourth trench LT4 are located on the same layer as the word line The conductive layer 124 is an integral structure in the step region ST, the top landing region SSLR (details will be described later), the first array region HP1, the common wall CW and the second array region HP2. Compared with the comparative example without a common wall, the setting of the same-layer word lines electrically connecting the first array area HP1 and the second array area HP2 by the common wall CW in this case can reduce the volume occupied by the step area ST .

Please refer to Figures 2 and 7 at the same time, in each block (BK1 or BK2), the bottom spacer GSLC extends along the first direction DI to separate the corresponding conductive layer 124 located at the bottom part of the stacked structure T1 Open, and define the ground selection line. The bottom spacer GSLC is in contact with the isolation sidewalls OW of the first and second unprocessed regions OP1 and OP2. Each bottom spacer GSLC includes an insulating material such as oxide to isolate the conductive layer 124 disposed on opposite sides of each bottom spacer GSLC in the bottom portion of the stacked structure T1.

As shown in Figure 2, in this embodiment, the unprocessed area OP may include a first unprocessed area OP1 and a second unprocessed area OP2 in each block BK1 and BK2, as in the first to second In the top view shown in the figure, the area of the first untreated area OP1 may be larger than the area of the second untreated area OP2. The first untreated area OP1 and the second untreated area OP2 can be separated by a part of the second trench LT2 and the fourth trench LT4 in the blocks BK1 and BK2 respectively. In block BK1, part of the second trench LT2 and bottom landing area GSLR may be set between the first untreated area OP1 and the second untreated area OP2. In block BK2, the first untreated area OP1 and the second untreated area OP2 Part of the fourth trench LT4 and the bottom landing area GSLR may be disposed between the second untreated area OP2. The conductive layer 124 at the bottom portion of the stacked structure T1 is exposed in the bottom landing region GSLR. Specifically, the isolation sidewall OW not only extends along the first direction DI, but also extends along the second direction DII and the third direction DIII, and the isolation sidewall OW surrounds the first untreated region OP1 After that, it continuously extends from the first untreated area OP1 to the second untreated area OP2 along the second direction DII, and surrounds the second untreated area OP2, forming two enclosed spaces. In the blocks BK1 and BK2, the bottom spacers GSLC adjacent to the first array region HP1 and the second array region HP2 contact the isolation sidewalls OW of the first unprocessed region OP1 and the second unprocessed region OP2 respectively, such as 2, but the present invention is not limited thereto. In other embodiments, the isolation sidewall OW can only form a closed space at the position of the first untreated area OP1, and form an open space at the position of the second untreated area OP2. For example, in the block BK2, the isolation side wall OW The bottom spacer GSLC may extend along the lower side and the right side of the second unprocessed region OP2 and be connected to the bottom spacer adjacent to the second array region HP2. However, the isolation sidewall OW does not extend to the upper side and the left side of the second untreated region OP2. In this embodiment, the two closed spaces formed by the first untreated area OP1 and the second untreated area OP2 are rectangular, but the present invention is not limited thereto.

As shown in FIGS. 2 and 3 , in order to allow each conductive layer 124 disposed in the middle portion of the stacked structure T1 to be connected to the word line contact WLN, a plurality of ladder structures MI are formed. The stepped structure MI allows each word line to be exposed through the landing pad LR, so as to be connected to the corresponding word line contact WLN. The ladder structure MI of this embodiment can be formed by a minimal incremental layer cost process (MILC process). The minimum incremental layer cost process can be calculated through an algorithm, using the least mask and etching The steps are performed to form a stepped structure MI, and the formed stepped structure MI may not be a regularly descending or gradually rising stepped profile. Compared with the regular step-down or step-up step structure, the step structure MI formed by the minimum incremental layer cost process can produce a denser step structure. Since the common wall CW has not undergone the minimum incremental layer cost process, the ladder structure MI and the common wall CW are opposite to each other in the upper view as shown in Figure 2 This separates. That is, the ladder structure MI and the common wall CW do not overlap in the plane defined by the second direction DII and the third direction DIII.

Please refer to FIGS. 2 and 3 at the same time, the circuit structure CT is disposed under the connection region CR, the first array region HP1 and the second array region HP2. The vertical contact TAC passes through the unprocessed region OP ( OP1 and OP2 ), the base plate 120 (shown in FIG. 5 ), and the insulating material 112 (shown in FIG. 5 ) under the base plate 120 along the first direction DI. As shown in FIG. 5, each vertical contact TAC passes through the stack of alternating pairs of first insulating layers 122 and second insulating layers 125 in the unprocessed region OP (OP1 and OP2), the bottom plate 120 and the underlying The insulating material 112 is electrically connected to the corresponding circuit structure CT. As shown in FIG. 3 , the corresponding circuit structure CT is electrically connected to the corresponding conductive layer 124 through at least one vertical contact TAC. As shown in FIGS. 2 and 3 , in the middle portion of the stacked structure T1 , the conductive layer 124 extends from the first array region HP1 and the top landing region SSLR to the stair region ST. In the stepped area ST, a plurality of landing pads LR corresponding to the conductive layer 124 are exposed. In this embodiment, each conductive layer 124 as a word line can be electrically contacted to the word line contact WLN through the exposed landing pad LR, and the word line contact WLN is connected to the word line contact WLN through the first conductive connection 132 Electrically connected to the vertical contact TAC, the vertical contact TAC is electrically connected to the circuit contact 136 through the second conductive connection 134 , and the circuit contact 136 is electrically connected to the corresponding circuit structure CT. In this way, the voltage from the circuit structure CT can be transmitted to the corresponding conductive layer 124 serving as the word line through the circuit contact 136 . The voltage, current or signal is further transmitted from the conductive layer 124 in the first array area HP1 to the conductive layer 124 in the same layer in the second array area HP2 through the common wall CW.

Similarly, as shown in FIG. 3 , each conductive layer 124 serving as a ground selection line can be electrically contacted with a ground selection line contact GSLN. That is, the ground selection line The contact GSLN is electrically connected to the corresponding conductive layer 124 of the bottom portion of the stacked structure T1 in the bottom landing region GSLR. The ground selection line contact GSLN is electrically connected to the vertical contact TAC through the first conductive connection 132, and the vertical contact TAC is electrically connected to the circuit contact 136 through the second conductive connection 134, and the circuit contact 136 is electrically connected Contact the corresponding circuit structure CT. Each conductive layer 124 as a series selection line can be electrically connected to the series selection line contact SSLN, and the series selection line contact SSLN is electrically connected to the vertical contact TAC through the first conductive connection 132, and the vertical contact The element TAC is electrically connected to the circuit contact 136 through the second conductive connection 134 , and the circuit contact 136 is electrically connected to the corresponding circuit structure CT. The extending direction of the serial select line contact SSLN, the ground select line contact GSLN and the circuit contact 136 may be parallel to the extending direction of the vertical contact TAC, for example, all extend along the first direction DI. The first conductive connection part 132 and the second conductive connection part 134 may respectively extend on a plane formed by the second direction DII and the third direction DIII.

Please refer to Figures 2 and 4 at the same time. The connection area CR in each block may further include two top landing areas SSLR. The top landing area SSLR is located at the two edge areas on opposite sides of the connection area CR. The two edge regions are adjacent to the first array area HP1 and the second array area HP2 respectively. The top landing area SSLR may be located between the first untreated area OP1 and the first array area HP1 and between the second untreated area OP2 and the second array area HP2, respectively. A tandem select line contact SSLN is disposed in the top landing region SSLR. Fig. 4 shows a cross-sectional view along the line X1-X1' in the sub-block BK24 in Fig. 2 . As shown in FIG. 4, after the initial step profile is formed through the preliminary etching process, the conductive layer 124 used as the serial selection line in the first array area HP1 and the second array area HP2 is separated from each other, so it is necessary to set the serial selection line. The line contacts SSLN and the side connectors 126 enable the same level of operation in the first array area HP1 and the second array area HP2. The conductive layers 124 that are string selection lines can be electrically connected to each other. The string select line contact SSLN shown in FIG. 4 is electrically connected to the conductive layer 124 serving as the string select line in the sub-block BK24 (shown in FIG. 1 ). In this embodiment, four serial selection line contacts SSLN are exemplarily shown, and the side connector 126 includes four side connectors 1261 - 1264 , but the present invention is not limited thereto. In some embodiments, the side connectors 1261~1264 can be located on the same plane and staggered from each other in the second direction DII and the third direction DIII, as long as the side connectors 1261~1264 can be electrically connected to the serial selection line respectively The contact SSLN and the conductive layer 124 at the same level are sufficient. The upper surface of the serial selection line contact SSLN and the ground selection line contact GSLN may have the same height, as shown in FIG. 6 . The sectional view in FIG. 4 corresponds to a section of a part of the common wall CW, so it can be known that the common wall CW includes a plurality of conductive layers 124 and a plurality of insulating layers 122 alternately stacked on the upper surface of the bottom plate 120 along the first direction DI. The conductive layer 124 disposed in the middle portion of the stacked structure T1 in the common wall CW (ie as a word line) extends continuously from the first array region HP1 to the second array region HP2 .

Fig. 5 shows a cross-sectional view along the line X2-X2' in the sub-block BK22 in Fig. 2 . Please refer to Figures 2 and 5 at the same time, in the untreated region OP (OP1 and OP2) (that is, in the closed space formed by the isolation sidewall OW), a plurality of first insulating layers 122 and a plurality of second insulating layers 125 Alternately stacked on the upper surface of the base plate 120 along the first direction DI. During the gate replacement process, since the untreated regions OP ( OP1 and OP2 ) are protected by the isolation sidewalls OW, the area within the enclosed untreated regions OP ( OP1 and OP2 ) will not be affected by the etchant. Therefore, the second insulating layer 125 in the untreated region OP ( OP1 and OP2 ) will not be replaced by the conductive layer 124 . On the contrary, the second insulating layer 125 outside the untreated region OP ( OP1 and OP2 ) not surrounded by the isolation sidewall OW will be replaced by the conductive layer 124 . Vertical contact TAC in the untreated area OPs (OP1 and OP2) pass through the first insulating layer 122, the second insulating layer 125, the bottom plate 120 and the insulating material 112 covering the circuit structure CT along the first direction DI, so as to be electrically connected to the corresponding circuit structure CT . The vertical contact TAC does not directly contact the bottom plate 120 , and the vertical contact TAC and the bottom plate 120 can be separated by the insulating material 112 . In this embodiment, the vertical contacts TAC can be respectively provided in the first untreated area OP1 and the second untreated area OP2, but the present invention is not limited thereto, the vertical contacts TAC can be provided only in the first untreated area OP2 in the area OP1 but not in the second unprocessed area OP2. As shown in Figure 1, a bottom landing area GSLR can be set between the first untreated area OP1 and the second untreated area OP2, and the ground selection line contact GSLN can be arranged in the bottom landing area GSLR, and the ground selection line contact GSLN And the bottom landing region GSLR can be electrically connected to the corresponding conductive layer 124 (ie, the ground selection line) at the bottom portion of the stacked structure T1. Please refer to Figures 1, 2 and 5 at the same time. The bottom landing area GSLR can overlap the ladder structure MI, and the conductive layer 124 (that is, as a ground selection line) at the bottom part of the stacked structure T1 is in the bottom landing area GSLR through the ladder structure MI. formed exposed. Each conductive layer 124 serving as a ground selection line can be electrically contacted with the ground selection line contact GSLN. The ground selection line contact GSLN shown in FIG. 5 is electrically connected to the conductive layer 124 serving as the ground selection line in the sub-blocks BK21 - BK22 (as shown in FIG. 1 ). As shown in FIG. 5 , the ground selection line contacts GSLN of the same level can be electrically connected to each other through the lateral connection piece 128 . In this embodiment, three pairs of ground selection line contacts GSLN are exemplarily shown, and the side connection part 128 includes three side connection parts 1281 - 1283 , but the present invention is not limited thereto. In some embodiments, the side connectors 1281~1283 can be located on the same plane and staggered from each other in the second direction DII and the third direction DIII, as long as the side connectors 1281~1283 can be electrically connected to the ground selection line respectively. The GSLN and the conductive layer 124 of the same level are sufficient. shown in Figure 5 The string select line contact SSLN is electrically connected to the conductive layer 124 serving as the string select line in the sub-block BK22 (shown in FIG. 1 ). In order to simplify the drawing, the lateral connecting member 126 is omitted.

Fig. 6 shows a cross-sectional view along the line X3-X3' of the sub-block BK21 in Fig. 2 . Please refer to Figures 2 and 6 at the same time. The word line contact WLN is disposed in the stepped area ST. Since the stepped area ST can overlap the stepped structure MI, the conductive layer 124 in the middle part of the stacked structure T1 (that is, serves as a word line) The step region ST is exposed by the formation of the step structure MI, that is, the landing pad LR is exposed, so that each conductive layer 124 serving as a word line can be electrically contacted with the word line contact WLN. The string select line contact SSLN shown in FIG. 6 is electrically connected to the conductive layer 124 serving as the string select line in the sub-block BK21 (shown in FIG. 1 ). The ground selection line contact GSLN shown in FIG. 6 is electrically connected to the conductive layer 124 serving as the ground selection line in the sub-blocks BK21 - BK22 (as shown in FIG. 1 ). In order to simplify the drawing, the side connectors 126 and 128 are omitted.

Figure 7 shows a cross-sectional view along the line Y1-Y1' in Figure 2. Please refer to FIGS. 2 and 7 at the same time. The first trench LT1 , the third trench LT3 and the fifth trench LT5 respectively pass through the stacked structure T1 along the first direction to the bottom plate 120 . The first trench LT1 , the third trench LT3 and the fifth trench LT5 respectively include conductive strips LTI (such as tungsten) and insulating sidewalls LTO (such as oxide), as shown in FIG. 7 . The insulating sidewalls LTO are disposed on the sidewalls of the first trench LT1 , the third trench LT3 and the fifth trench LT5 , and the conductive strip LTI is located between the insulating sidewalls LTO and electrically contacts the bottom plate 120 . In this embodiment, the conductive strip LTI can be used as a source line, and the bottom plate 120 can be used as a common source line. In detail, before the gate replacement process, the trench LT is formed first, and then the second insulating layer is removed through the gate replacement process through the trench LT, and the conductive material is filled into the first gate replacement process. The position where the second insulating layer (125) is removed. Therefore, a stacked structure T1 in which the conductive layers 124 and the first insulating layers 122 are alternately stacked is formed. Thereafter, the trench LT is slightly enlarged, and the insulating material and the conductive material are sequentially filled in the trench LT, thereby forming the trench LT including the conductive strip LTI and the insulating sidewall LTO, the first trench to the fifth trench LT1-LT5 all have the same or similar structures in the cross-sectional views. Since the third trench LT3 has insulating sidewalls LTO, the third trench LT3 can electrically isolate the blocks BK1 and BK2 from each other.

As shown in FIG. 7 , the bottom spacer GSLC separates the bottom three conductive layers 124 in the blocks BK1 and BK2 respectively, but the present invention is not limited thereto. In one example, the conductive layer 124 (as a ground selection line) disposed at the bottom portion of the stacked structure T1 of each block ( BK1 or BK2 ) is electrically isolated into two groups.

Please refer to FIGS. 1, 2 and 8 at the same time. The length L1 formed by the stepped structure MI in the third direction DIII is greater than the length L2 formed by the stepped region ST in the third direction DIII. In FIG. 8 , the word line contacts WLN located on opposite sides of the third trench LT3 are electrically connected to the conductive layer 124 serving as the word line in the blocks BK1 and BK2 , respectively.

Please refer to Figures 1, 2 and 9 at the same time, the ground selection line contacts GSLN may include ground selection line contacts GSLN1~GSLN4, the ground selection line contacts GSLN1~GSLN2 correspond to block BK1, and the ground selection line contacts GSLN3~GSLN4 Corresponds to block BK2. Since the isolation side wall OW and the bottom isolation member GSLC separate the corresponding conductive layer 124 as the ground selection line, the ground selection line contacts GSLN1-GSLN2 are respectively located on the first side S1 and the second side S2 of the isolation side wall OW, and are grounded. The selection line contacts GSLN3-GSLN4 are respectively located on the first side S1 and the second side S2 of the isolation side wall OW, and the ground selection line contact GSLN1 is electrically connected to the conductive layer 124 serving as the ground selection line in the sub-block BK11 or BK12. select The line selection contact GSLN2 is electrically connected to the conductive layer 124 as the ground selection line in the sub-block BK13 or BK14, and the ground selection line contact GSLN3 is electrically connected to the conductive layer 124 as the ground selection line in the sub-block BK21 or BK22 , the ground selection line contact GSLN4 is electrically connected to the conductive layer 124 serving as the ground selection line in the sub-block BK23 or BK24 .

Please refer to Figures 1, 2 and 10 at the same time, the serial selection line contact SSLN may include the serial selection line contacts SSLN1~SSLN8, because the top spacer SSLC separates the corresponding conductive layer 124 as the serial selection line , the serial selection line contacts SSLN1~SSLN8 are respectively located on the first side S1 and the second side S2 of the adjacent top spacer SSLC, and the serial selection line contact SSLN1 is electrically connected to the sub-block BK11 as a serial selection line The conductive layer 124 of the serial selection line contact SSLN2 is electrically connected to the conductive layer 124 as the serial selection line in the sub-block BK12, and the serial selection line contact SSLN3 is electrically connected to the sub-block BK13 as the serial selection line The conductive layer 124 of the selection line, the serial selection line contact SSLN4 is electrically connected to the conductive layer 124 of the serial selection line in the sub-block BK14, and the serial selection line contact SSLN5 is electrically connected to the sub-block BK21 as the conductive layer 124. The conductive layer 124 of the serial selection line, the serial selection line contact SSLN6 is electrically connected to the conductive layer 124 of the serial selection line in the sub-block BK22, and the serial selection line contact SSLN7 is electrically connected to the sub-block BK23 The conductive layer 124 serving as a string selection line, the string selection line contact SSLN8 is electrically connected to the conductive layer 124 serving as a string selection line in the sub-block BK24 .

In an embodiment, the materials of the top spacer SSLC, the bottom spacer GSLC, and the isolation sidewall OW may respectively include dielectric materials; the material of the first insulating layer 122 may include oxide; the material of the second insulating layer 125 may include nitrogen. compounds, For example, it is silicon nitride; the material of the conductive layer 124 may include tungsten; the material of the insulating sidewall LTO may include a dielectric material, and the dielectric material may be an oxide, but the invention is not limited thereto.

Based on the above, a memory device is provided according to an embodiment of the present application. The memory device includes a stack structure, a circuit structure and a vertical contact. The laminated structure includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked along a first direction, a first array area, a second array area and a connection area. The first array area includes a plurality of first channel pillars extending along a first direction. The second array area includes a plurality of second channel pillars extending along the first direction. The connection area is disposed between the first array area and the second array area, wherein the connection area includes a stepped area, an unprocessed area, a bottom spacer and a shared wall. The untreated area extends along the first direction and has an isolation side wall, the isolation side wall electrically isolates the conductive layer from the untreated area, the stepped area is in contact with a first side of the untreated area, and the shared wall is in contact with a first side of the untreated area On the second side, the first side is opposite to the second side, and part of the conductive layer extends continuously in the step area, the first array area, the common wall and the second array area respectively. The bottom isolator extends along the first direction to separate the conductive layer at a bottom portion of the stacked structure and defines a ground selection line, and the bottom isolator is in contact with the isolation sidewall. The circuit structure is disposed under the connection area and exposed by the unprocessed area. The vertical contact passes through the untreated area and electrically connects the circuit structure to the corresponding conductive layer.

Compared with the comparative example in which the connection region in one block is only arranged on a single side of the array region, since the connection region in this case is arranged between the first array region and the second array region, the current/voltage transmission path The distance can be shortened, so the electricity can be reduced resistance and capacitance, thereby increasing the operating speed of the memory device. In addition, the volume occupied by the stepped area can be reduced by setting the word lines of the same layer electrically connecting the first array area and the second array area by sharing the wall.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

10: Memory device

BK1, BK2: block

BK11~BK14, BK21~BK24: sub-blocks

CR: connection region

CW: Common Wall

DI: first direction

DII: second direction

DIII: Third Direction

GSLC: bottom spacer

GSLN: Ground Selection Line Contact

GSLR: Bottom Landing Zone

HP1: the first array area

HP2: second array area

LT: Groove

LT1: first groove

LT2: second groove

LT3: the third groove

LT4: fourth groove

LT5: fifth groove

OP: untreated area

OP1: The first untreated area

OP2: The second untreated area

OW: isolated side wall

S1, S2: side

SSLC: top spacer

SSLN: Serial selection line contact

ST: step area

TAC: vertical contact

VC1: the first channel column

VC2: second channel column

WLN: word line contact

Claims (15)

A memory device, comprising: a stacked structure, including: a plurality of conductive layers and a plurality of first insulating layers alternately stacked along a first direction; a first array region, including a plurality of layers extending along the first direction a first channel column; a second array area, including a plurality of second channel columns extending along the first direction; and a connection area, arranged between the first array area and the second array area, wherein The connection area includes a stepped area, an untreated area, a bottom spacer and a common wall, wherein the untreated area extends along the first direction and has an isolation sidewall, and the isolation sidewall electrically connects the conductive layers. isolated from the untreated area, the stepped area is adjacent to a first side of the untreated area, the common wall is adjacent to a second side of the untreated area, the first side is opposite to the second side, and part of The conductive layers extend continuously in the step area, the first array area, the common wall and the second array area, and wherein the bottom spacer extends along the first direction, so as to be located at the stacked structure The conductive layers of a bottom portion are separated and define a plurality of ground selection lines, the bottom spacer is in contact with the isolation sidewall; a circuit structure is disposed under the connection area; and A vertical contact passes through the untreated area and electrically connects the circuit structure to the corresponding conductive layer of the conductive layers. The memory device of claim 1, wherein the unprocessed region comprises a stack of alternating pairs of first insulating layers and second insulating layers. The memory device according to claim 1, wherein the unprocessed area includes a first unprocessed area and a second unprocessed area, and the isolation sidewall extends from the first unprocessed area to the second unprocessed area, And surround the second untreated area. The memory device as claimed in claim 3, further comprising a bottom landing area, the bottom landing area is disposed between the first untreated area and the second untreated area, the bottom parts of the stacked structure A conductive layer is exposed in the bottom land area. The memory device according to claim 4, further comprising a plurality of ground selection line contacts, and the ground selection line contacts are disposed in the bottom landing area. The memory device as claimed in claim 4, further comprising a plurality of ground selection line contacts electrically connected to the corresponding ones of the bottom portion of the stacked structure in the bottom landing area conductive layer. The memory device according to claim 2, further comprising at least one trench, wherein the at least one trench extends through the stacked structure along the first direction, and extends along a second direction perpendicular to the first direction. Extending in the direction, the stacked structure is divided into two blocks. The memory device of claim 7, wherein the at least one trench includes a conductive strip and an insulating sidewall. A memory device, comprising: a stacked structure, including: a plurality of conductive layers and a plurality of first insulating layers alternately stacked along a first direction; a first array region, including a plurality of layers extending along the first direction a first channel column; a second array area, including a plurality of second channel columns extending along the first direction; and a connection area, arranged between the first array area and the second array area, wherein The connecting area includes a stepped area, an untreated area, a bottom spacer, and a common wall; a plurality of grooves extend along the first direction and pass through the stacked structure, and along a direction perpendicular to the first direction extending in a second direction, wherein the grooves include a first groove, a second groove, a third groove, a fourth groove and a fifth groove, the second groove The groove is arranged between the first groove and the third groove, the fourth groove is arranged between the third groove and the fifth groove, a plurality of top spacers, along the first direction extending and passing through the corresponding conductive layers disposed in a top portion of the stacked structure; wherein the first trench, the third trench and the fifth trench respectively extend continuously along the second direction , so that the stacked structure is divided into a first block and a second block, wherein the second trench and the top spacers on opposite sides of the second trench divide the first block into 4 sub-blocks, the fourth trench and the top spacers on opposite sides of the fourth trench divide the second block into 4 sub-blocks, wherein, in each of the first block and In the second block, the stepped area is adjacent to a first side of the untreated area, the common wall is adjacent to a second side of the untreated area, the first side is opposite to the second side, and Parts of the conductive layers extend continuously in the step area, the first array area, the common wall and the second array area, wherein the untreated area extends along the first direction and has an isolation sidewall, the isolation sidewalls electrically isolate the conductive layers from the untreated region; and wherein the bottom spacer extends along the first direction to separate the conductive layers at a bottom portion of the stacked structure and define a plurality of ground selection lines, the bottom isolation member is in contact with the isolation sidewall; a circuit structure is disposed under the connection area; and a vertical contact member passes through the unprocessed area and electrically connects the circuit structure The conductive layer corresponding to the conductive layers. The memory device of claim 9, wherein the unprocessed region comprises a stack of alternating pairs of first insulating layers and second insulating layers. The memory device according to claim 9, wherein the unprocessed area includes a first unprocessed area and a second unprocessed area, and the isolation sidewall extends from the first unprocessed area to the second unprocessed area, And surround the second untreated area. The memory device according to claim 11, further comprising a bottom landing area, the bottom landing area is disposed between the first untreated area and the second untreated area, and the bottom parts of the stacked structure A conductive layer is exposed in the bottom land area. The memory device according to claim 12, further comprising a plurality of ground selection line contacts, and the ground selection line contacts are disposed in the bottom landing area. The memory device as claimed in claim 12, further comprising a plurality of ground selection line contacts electrically connected to the corresponding ones of the bottom portion of the stacked structure in the bottom landing area conductive layer. The memory device of claim 9, wherein the at least one trench includes a conductive strip and an insulating sidewall.

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