TWI508257B - Three dimensional stacked semiconductor structure and method for manufacturing the same - Google Patents

Description

Three-dimensional stacked semiconductor structure and manufacturing method thereof

The present invention relates to a three-dimensional stacked semiconductor structure and a method of fabricating the same, and more particularly to a three-dimensional stacked semiconductor structure having a conductive strip connected to source contacts and a method of fabricating the same.

A very important feature of non-volatile memory components is the ability to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some three-dimensional stacked NAND (NAND) type flash memory structures have been proposed. However, there are still some problems that need to be solved in the traditional three-dimensional stacked memory structure.

Figure 1 is a perspective view of a 3D stacked semiconductor structure. In the first figure, a 3D NAND memory array structure is illustrated as an example. 3D stacking The semiconductor structure includes an array region 11 and a fan-out region 13. The multilayer array is formed on an insulating layer and includes a plurality of word lines 125-1 WL, ..., 125-N WL which are formed isotropically formed with a plurality of stacks. The plurality of stacks includes semiconductor strips 112, 113, 114, 115. The semiconductor strips in the same plane are electrically coupled together by a step structure (also referred to as a bit line structure). The ladder structures 102B, 103B, 104B, 105B terminate semiconductor strips (eg, semiconductor strips 102, 103, 104, 105). As shown in the figure, these stepped structures 102B, 103B, 104B, 105B are electrically connected to different bit lines for connection to a decoding circuit for selecting a plane within the array. The stacked semiconductor strips 102, 103, 104, 105 have a source line end to a bit line end direction. The stacked semiconductor strips 102, 103, 104, 105 are terminated at one end by step structures 102B, 103B, 104B, 105B, through SSL gate structure 109, ground select line GSL 127, word line 125-N WL to 125-1 WL, ground select line GSL 126, and terminated at the other end by a source line (covered by other parts of the figure). The stacked semiconductor strips 112, 113, 114, 115 are terminated at one end by stepped structures 112A, 113A, 114A, 115A, through SSL gate structure 119, ground select line GSL 126, word lines 125-1 WL through 125-N WL, ground select line GSL 127, and terminated by source line 128 at the other end.

Take a source line 128 as an example. The source line 128 includes a staggered stacked insulating layer (such as an oxide layer) and a conductive layer (such as a polysilicon as a gate material), and has a contact hole perpendicular to the stacked structure and a conductive material filled in the hole to externally connect the conductive layers of the layers. . Traditionally, for self-alignment, filling the conductive material in the contact hole is done before the deposition of the bit line hard mask layer, however, the hard mask material may be redeposited in contact. Inside the hole. This can cause problems in the SC pick-up process. Furthermore, in a conventional 3D stacked semiconductor structure, the source contact region is an open area during word line etching (eg, ion reactive etching), and the influence of the word line process on the source contact region (WL) The loading effect is more severe than the effect of the memory cell area. Traditionally, the source contact area requires a thicker hard mask layer to protect against damage that may occur when the word line is etched. Moreover, the source contact and the bit line of the conventional stacked structure are constructed on the same horizontal surface, which increases the difficulty in alignment between the source contact and the upper conductive plug when the source contact process is performed.

The present invention relates to a three-dimensional stacked semiconductor structure and related fabrication methods. According to an embodiment, the patterning step of the source contact (filling the conductive material in the contact hole) is performed after the deposition of the hard mask layer (such as the dielectric layer) of the bit line, so that the conductive material in the contact hole is rigid and hard. The mask layer (such as the dielectric layer) is the same as the horizontal plane. Furthermore, one of the embodiments has a conductive strap that spans over a plurality of source contacts. Therefore, the three-dimensional stacked semiconductor structure of the embodiment has a lower source contact resistance, a stable construction capable of reducing the word line effect (WL loading effect), and an electronic property having good reliability.

According to an embodiment, a three-dimensional stacked semiconductor structure is provided, including: a plurality of stacks formed on a substrate, at least one contact hole formed vertically on one of the stacks, and a conductor (conductor) Formed in the contact hole, a charging trapping layer is formed at least in the At the side wall of the stack. One of the stacks includes a multi-layered pillar including a plurality of insulating layers and a plurality of conductive layers alternately stacked, and a dielectric layer formed on the plurality of pillars. The contact holes pass through the corresponding stacked dielectric layers, the insulating layers, and the conductive layers. Conductors in the contact holes are connected to the conductive layers of the stack. Wherein, the upper surface of the electrical conductor is higher than the upper surface of the stacked multi-layer cylinder.

According to an embodiment, a method for fabricating a three-dimensional stacked semiconductor structure is provided, comprising: forming a plurality of stacked on a substrate, wherein one of the stacks comprises a plurality of pillars having a plurality of insulating layers and a plurality of conductive layers alternately Stacked, and a dielectric layer is formed on the multi-layered pillar; forming at least one contact hole perpendicular to one of the stacks, and the contact hole is passed through the corresponding stacked dielectric layer, the insulating layers, and the a conductive layer; filling a conductive body in the contact hole and connecting the conductive layers corresponding to the stack, wherein an upper surface of the conductive body is higher than an upper surface of the stacked multi-layer cylinder; forming a charge trapping layer Located at the side walls of the stacks.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.

11‧‧‧Array area

13‧‧‧Fan area

102, 103, 104, 105, 112, 113, 114, 115‧‧ ‧ semiconductor strips

102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A‧‧‧ ladder structure

128‧‧‧ source line

20, 40‧‧‧ substrate

21, 41‧‧‧ Stacking

21P, 41P‧‧‧ multilayer cylinder

211, 411‧‧‧ insulation

213, 413‧‧‧ conductive layer

23, 43‧‧‧ hard mask layer

23a, 43a‧‧‧Top surface of hard mask layer

24, 44‧‧‧ contact holes

25, 45‧‧‧ Electrical conductors

25a, 45a‧‧‧ Upper surface of electrical conductor

26, 46‧‧‧ Charge trapping layer

27, 47‧‧‧ Conductive strips

48‧‧‧Isolation

49‧‧‧ Conductive embolization

49’‧‧‧ Conductive trace

Rsc‧‧‧ source contact area

125-1 WL,...,125-N WL, WL‧‧‧ character line

BL‧‧‧ bit line

109, 119‧‧‧SSL gate structure

SSL‧‧‧ tandem selection line

126, 127, GSL‧‧‧ grounding selection line

Figure 1 is a perspective view of a 3D stacked semiconductor structure.

2 is a cross-sectional view showing a source contact region of a portion of a three-dimensional stacked semiconductor structure according to an embodiment of the present invention.

Figure 3 is a top plan view of a portion of a three-dimensional stacked semiconductor structure in accordance with an embodiment of the present invention.

4A-11A and 4B-11B illustrate a method of fabricating a three-dimensional stacked semiconductor structure according to an embodiment of the present invention.

Figure 12 is a schematic diagram showing another way of carrying the source contacts.

In an embodiment of the present disclosure, a three-dimensional stacked semiconductor structure and associated fabrication method are presented. The three-dimensional stacked semiconductor structure proposed in the embodiment has a low source contact resistance, a stable construction capable of reducing the WL loading effect, and an electron with good reliability. characteristic. Moreover, the three-dimensional stacked semiconductor structure of the embodiment has a simple process of fabrication, which can be accomplished without the use of time consuming and expensive processes.

The embodiments of the present disclosure are widely used. For example, it can be applied to a three-dimensional flash memory, such as a fan-out area of a three-dimensional NAND type flash memory, but the disclosure is not limited to this application. The related embodiments are presented below in conjunction with the drawings to explain in detail the three-dimensional stacked semiconductor structure proposed in the present disclosure and related manufacturing methods. However, the disclosure is not limited to this. The description of the embodiments, such as the detailed structure, the process steps, the application of the materials, and the like, are for illustrative purposes only and are not intended to limit the scope of the disclosure.

Furthermore, the disclosure does not show all possible embodiments. The structure and process may be modified and modified to meet the needs of the actual application process without departing from the spirit and scope of the disclosure. Therefore, other implementations not presented in the present disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

According to an embodiment, the patterning step of the source contacts of the three-dimensional stacked semiconductor structure is performed after the hard mask deposition of the bit lines, the material of the hard mask layer being, for example, a dielectric layer material. 2 is a cross-sectional view showing a source contact region of a portion of a three-dimensional stacked semiconductor structure according to an embodiment of the present invention. A semiconductor structure of an embodiment includes a plurality of stacks 21 formed on a substrate 20, and one of the stacks 21 includes a multi-layered pillar 21P and a hard mask layer. 23 is formed on the multilayer cylinder 21P. The multilayer pillar 21P includes a plurality of insulating layers 211 (for example, an oxide layer) and a plurality of conductive layers 213 (for example, a polysilicon layer) alternately stacked. The hard mask layer 23 is formed on the insulating layer 211 of the uppermost layer of the multilayer pillar 21P. The material of the hard mask layer 23 is, for example, a material of a dielectric layer, but the disclosure is not limited thereto.

The semiconductor structure of the embodiment also includes at least one contact hole 24 formed vertically in one of the stacks 21, and the contact holes 24 are passed through the hard mask layer 23 of the corresponding stack 21, the insulating layers 211 and the Some conductive layers 213. Two contact holes 24 as shown in Fig. 2, but of course the disclosure does not refer to the number of contact holes. There are many restrictions. Furthermore, a conductor 25 is formed in the contact hole 24 and connected to the conductive layers 213 of the corresponding stack 21 (i.e. where the contact holes 24 extend).

The semiconductor structure of the embodiment also includes a charging trapping layer 26, such as an ONO layer (oxide layer-nitride layer-oxide layer) or an ONONO layer (oxide layer-nitride layer-oxide layer-nitridation layer). A layer-oxide layer is formed at least at the sidewalls of the stacks 21. As shown in Fig. 2, a charge trapping layer 26 is formed at the sidewall of the stack 21, and an upper surface 25a of the conductor 25 and an upper surface 23a of the hard mask layer 23 are exposed and are not trapped by the charge. Layer 26 is covered.

The above-mentioned electrical conductor 25 can be used as a source contact of the three-dimensional stacked semiconductor structure of an embodiment. As shown in Fig. 2, one upper surface 25a of the conductor 25 is higher than the upper surface of one of the multilayer cylinders 21P of the stack 21. In one embodiment, the upper surface 25a of the electrical conductor 25 is substantially aligned with the upper surface 23a of the hard mask layer 23.

According to an embodiment, a conductive strap 27 is formed over the stacks 21 and contacts the charge trapping layer 26. The conductive strips 27 are formed over and across the electrical conductors 25 in the contact holes 24. The conductive strips 27 are electrically connected to the conductors 25 in the contact holes 24 and the charge trapping layer 26 at the sidewalls of the stack 21. 3 is a top view of a portion of a three-dimensional stacked semiconductor structure in accordance with an embodiment of the present invention, wherein the conductive strips 27 are formed on the conductors 25 in the contact holes 24 and are parallel to the plurality of word lines (WL). .

According to an embodiment, the conductive strip 27 is a conductive strip of a contact contact (source contact strap), thereby reducing the resistance of the contact contacts. In an embodiment, the conductive strips 27 can be fabricated simultaneously with the word lines in the same material. Furthermore, the conductive strip 27 of the embodiment is constructed in the source region (SC region), and therefore, the source contact (ie, the conductor 25) is covered and protected by the conductive strip 27 (rather than the source in the conventional structure) The contacts are covered by a bit line hard mask layer (/dielectric layer), thereby reducing the effect of the word line process on the source contact area (WL loading effect). Moreover, since the patterning step of the source contact of the embodiment is performed after the deposition of the bit line hard mask layer, the material of the hard mask layer is not deposited in the source contact.

The following is a method of manufacturing a three-dimensional stacked semiconductor structure. However, the disclosure is not limited to the details of the structure and the steps, but may be appropriately adjusted and changed as needed for the process or the actual application.

4A-11A and 4B-11B illustrate a method of fabricating a three-dimensional stacked semiconductor structure according to an embodiment of the present invention. Here, the illustration labeled A is as shown in FIGS. 4A, 5A, 6A, 11A, and is a top view of the three-dimensional stacked semiconductor structure of the embodiment. The diagrams labeled B are as shown in sections 4B, 5B, 6B, ... 11B, respectively, along the section line AA of Figs. 4A, 5A, 6A, ... 11A. The position of the hatching AA corresponds to a source contact region.

As shown in FIG. 4A and FIG. 4B, a plurality of stacks 41 are formed on a substrate 40, and a plurality of insulating layers 411 (eg, an oxide layer) and a plurality of conductive layers 413 (eg, polysilicon layers) are alternately stacked to form a stack. A multi-layered pillar 41P of the stack 41 is formed, and a hard mask layer 43 is formed on the uppermost insulating layer 411 of the multilayer pillar 41P. Hard mask layer The material of 43 may be a dielectric layer material, such as tantalum nitride or oxide, deposited over insulating layer 411.

As shown in FIGS. 5A and 5B, at least one contact hole 44 is formed vertically, and the contact hole 44 passes through the hard mask layer 43, the insulating layer 411, and the conductive layers 413.

After the step of patterning the source contacts as shown in FIGS. 5A and 5B, a conductive material is filled at the contact holes 44 to construct a source contact. In one embodiment, a conductive layer (such as N+ polysilicon) is deposited on the hard mask layer 43 and fills the contact holes 44, and then the conductive layer is planarized to form the conductors 45 in the contact holes 44. In one embodiment, the planarization of the conductive layer is performed by chemical mechanical polishing (CMP) or other suitable steps. As shown in FIGS. 6A and 6B, the upper surface 45a of the conductor 45 is substantially aligned with the upper surface 43a of the hard mask layer 43. According to the manufacturing method of the embodiment, the upper surface 45a of the conductor 45 is higher than the upper surface of the uppermost insulating layer 411.

As shown in FIGS. 7A and 7B, the structure of FIG. 6B is then patterned to form bit lines (BL) and stack 41. In one embodiment, when the ATF process is used to pattern the bit lines, the hard mask layer (/dielectric layer) of the bit lines will not be damaged. As shown in FIG. 7B, one bit line (BL) is formed between the two stacks 41, and each stack 41 has a source contact (ie, conductor 45). Wherein, each stack 41 includes a multi-layered pillar 41P and a hard mask layer 43 formed on the multilayer pillar 41P, and the multilayer pillar 41P includes several layers. The edge layer 411 and the plurality of conductive layers 413 are alternately stacked; the conductors 45 filled in the contact holes 44 pass through the hard mask layer 43, the insulating layer 411 and the conductive layer 413 of the corresponding stack 41 vertically.

Thereafter, a charge trapping layer 46 (such as an ONO layer or an ONONO layer) is formed on the stack 41 and at least sidewalls of the bit lines. In the present disclosure, different steps can be applied to make the structure, such as steps 8B and 9B.

As shown in FIGS. 8A and 8B, a charge trapping layer 46 (such as an ONO layer or an ONONO layer) is deposited to cover the stack 41, the bit line (BL), and the substrate. Thereafter, a portion (eg, upper portion) of the charge trapping layer 46 is removed to expose the upper surface 45a of the conductor 45, the upper surface of the bit line, and the upper surface 43a of the hard mask layer 43, as shown in FIG. And Figure 9B shows. In one embodiment, a lithography process can be applied to a photoresist to define (turn on) the source contact region Rsc, and only the upper portion of the charge trapping layer 46 corresponding to the source contact region Rsc is removed, such as Figure 9A shows. The region other than the source contact region Rsc is still covered by the charge trapping layer 46. In another embodiment, instead of photoresist, all of the stack 41 and the upper portion of the charge trapping layer 46 of the bit line (BL) are removed and may be applied. This disclosure does not limit this much. The charge trapping layer 46 is removed, for example, by reactive ion etching (RIE) to expose the electrical conductors 45 within the contact holes 44. Furthermore, an organic dielectric layer (ODL)/SHB process can be applied to overcome the problem of the structural height of the conductor 45.

Thereafter, a conductive strap 47 is formed over and across (as shown in FIG. 3) the stacks 41 and corresponding to the source contact regions Rsc. As shown in FIGS. 10A and 10B, the conductive strip 47 and the plurality of word lines (WL) may be simultaneously formed over the stack 41 and the bit line (BL). Therefore, the conductive strip 47 and the word line system of the embodiment can be made of the same material. In one embodiment, the conductive strips 47 and the word lines are, for example, polycrystalline germanium (made in a self-aligned metal germanide process). However, the disclosure does not limit this. The materials of the conductive strips 47 and the word lines may be the same or different, and may be made at the same time or at different times, and the materials may be appropriately selected according to actual application requirements.

As shown in Fig. 10A, the conductive strips 47 are arranged in parallel with the word lines (WL) and spaced apart from each other by a distance. As shown in FIG. 10B, the conductive strip 47 is electrically connected to the conductor 45 (for example, the upper surface 45a of the contact conductor 45) and the charge trapping layer 46 in the contact hole 44. The conductive strip 47 also contacts the upper surface 43a of the hard mask layer 43.

Thereafter, a conducting portion is formed on the conductive strip 47 to receive the signal from the source contact (e.g., the electrical conductor 45). The conductive portion is separated from the conductor 45 and the hard mask layer 43 by a distance. In an embodiment, the conductive portion may be a conductive line or a conductive plug.

As shown in FIGS. 11A and 11B, an isolation layer (such as an inner dielectric layer ILD) 48 is formed on the conductive strip 47, and a plurality of holes are formed in the isolation layer 48 and through the isolation layer 48, and then A conductive material such as tungsten or other suitable metal fills the holes. As shown in FIG. 11B, a conductive plug 49 is formed in the hole of the isolation layer 48. The conductive plugs 49 are electrically connected to the electrical conductors 45 in the contact holes 44 by the conductive strips 47. In addition, as shown in FIG. 12, it is a schematic diagram showing another way of carrying the source contact, wherein the conductive portion is a conductive walking. A line 49' is formed over the conductive strips 47 and spans the stacks 41. The conductive trace 49' is, for example, tungsten, or the same material as the word line, or other suitable conductive material.

According to the structure of the embodiment, that is, the construction of the conductor 45, the bus bar 47, and the conductive portion (49/49'), it is not necessary to consider whether or not there is a problem of misalignment between the conductive plug and the source contact. Therefore, the three-dimensional stacked semiconductor structure proposed in the embodiment has good electronic properties with good reliability.

According to the above embodiment, the source contact patterning in the three-dimensional stacked semiconductor structure is performed after the deposition of the bit line hard mask layer (dielectric material), and the hard mask layer is not deposited in the source contact. material. Furthermore, the conductor 25/45 of a source contact of the three-dimensional stacked semiconductor structure of the embodiment protrudes from the upper surface of the multilayer pillar 21P/41P, that is, higher than the height of the conventional source contact, thereby reducing The resistance of the source contact. Furthermore, the conductive strips 27/47 of the embodiment are constructed in the source contact region, so that the source contact (ie, the conductor 25) is protected by the conductive strip 27 (instead of the source contact in the conventional structure is subject to The bit line is covered by a hard mask layer, thereby reducing the effect of the word line process on the source contact area (WL loading effect). Furthermore, the conductive strips 27/47 of the embodiment can be fabricated simultaneously with the word lines in the same material, which is simple and time-saving in the production steps, and is suitable for mass production.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

25‧‧‧Electric conductor

27‧‧‧ Conductive strip

Poly‧‧‧ polycrystalline layer

WL‧‧‧ character line

SSL‧‧‧ tandem selection line

GSL‧‧‧ Grounding selection line

Claims (10)

A three-dimensional stacked semiconductor structure includes: a plurality of stacked stacks formed on a substrate, and one of the stacks includes: a multi-layered pillar including a plurality of layers of insulation a layer and a plurality of layers of conductive layers are alternately stacked; a dielectric layer is formed on the plurality of pillars; at least one contact hole is vertically formed on one of the stacks, and the contact hole is Passing through the corresponding dielectric layer of the stack, the insulating layers and the conductive layers; a conductor formed in the contact hole and connecting the conductive layers corresponding to the stack; and a charge compensation A catching layer is formed at least at sidewalls of the stack; wherein an upper surface of the conductor is higher than an upper surface of the stacked plurality of pillars. The three-dimensional stacked semiconductor structure of claim 1, further comprising a conductive strap formed over the stack and contacting the charge trapping layer. The three-dimensional stacked semiconductor structure of claim 2, wherein the conductive strip contacts the upper surface of the electrical conductor and an upper surface of the dielectric layer. The three-dimensional stacked semiconductor structure of claim 2, further comprising a conducting portion formed on the conductive strip, wherein the conductive portion and the dielectric layer and the conductive body in the contact hole Separated by a distance. The three-dimensional stacked semiconductor structure of claim 2, further comprising: an isolating layer formed on the conductive strip; and at least one conductive plug formed in the isolation layer and passing through The isolation layer, wherein the conductive plug is electrically connected to the conductive body in the contact hole by the conductive strip. A method for fabricating a three-dimensional stacked semiconductor structure, comprising: forming a plurality of stacks on a substrate, one of the stacks comprising: a multi-layered pillar comprising a plurality of insulating layers and a plurality of Layers of conductive layers are alternately stacked; a dielectric layer is formed on the plurality of pillars; at least one contact hole is formed perpendicular to one of the stacks, and the contact holes are passed through The stacked dielectric layer, the insulating layers and the conductive layers; filling a conductor in the contact hole and connecting the conductive layers corresponding to the stack, wherein one of the conductive layers The surface is higher than the corresponding heap Stacking an upper surface of one of the plurality of pillars; forming a charging trapping layer at least at sidewalls of the stacks. The method of claim 6, wherein the conductive strip contacts the upper surface of the electrical conductor and an upper surface of the dielectric layer. The method of claim 7, wherein the conductive strip is made of the same material as the word lines. The method of claim 6, further comprising forming a conducting portion on the conductive strip, wherein the conductive portion is separated from the dielectric layer and the conductive body in the contact hole distance. The method of claim 6, further comprising forming an isolating layer on the conductive strip; forming at least one hole in the isolation layer and passing through the isolation layer; and forming a conductive plug ( The conductive plug is in the hole of the isolation layer, wherein the conductive plug is electrically connected to the conductive body in the contact hole by the conductive strip.