TWI607528B - Semiconductor device and manufacturing method thereof - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a vertical channel semiconductor device and a method of fabricating the same.

In recent years, the structure of semiconductor devices has continually evolved, and the storage capacity of devices has continually increased. The memory device is used to store many electronic products, such as MP3 files, digital images, computer files, and the like. As the range of applications continues to increase, the demand for memory devices is focused on small size and large capacity. In order to meet the requirements, a memory device having a high component density and a small volume and a method of manufacturing the same are required.

Therefore, a vertical channel memory device capable of achieving a large storage capacity, a small volume, and having good performance and stability has become an important direction for research and development.

The present invention relates to a semiconductor device and a method of fabricating the same that etches a portion of a charge trapping structure to form a pad layer to form a thick and wide pad for securely connecting a bit line.

According to a first aspect of the present invention, a semiconductor device system is proposed Method of making. The manufacturing method includes the following steps. Forming a two stacked structure on a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, and a top insulating layer. The gate layer and the gate insulating layer are alternately disposed. The top insulating layer is disposed on the gate layer and the gate insulating layer. A charge trapping structure and a channel layer are formed on one side surface of each of the stacked structures. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Each of the first dielectric layers is etched and a portion of each of the second dielectric layers is etched to expose a portion of the channel layer. A pad layer is formed on the first dielectric layer and the second dielectric layer to connect the channel layer.

According to a second aspect of the invention, a semiconductor device is provided. The semiconductor includes a substrate, a two-stack structure, a charge trapping structure, a channel layer, and a pad layer. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, and a top insulating layer. The gate layer and the gate insulating layer are alternately disposed. The top insulating layer is disposed on the gate layer and the gate insulating layer. The charge trapping structure and the channel layer are disposed on one side surface of each of the stacked structures. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. The top of the channel layer is higher than the top of each of the first dielectric layers and the top of each of the second dielectric layers. The pad layer is disposed on the first dielectric layer and the second dielectric layer to connect the channel layer.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100, 200, 300, 400‧‧‧ semiconductor devices

110, 310‧‧‧ substrate

120‧‧‧Bottom insulation

120a‧‧‧ upper surface

130, 230, 330, 430‧‧‧ stacked structure

130a‧‧‧ trench

130b, 330b‧‧‧ side surface

131, 331‧‧ ‧ gate layer

132, 332‧‧ ‧ gate insulation

133, 333, 433‧‧‧ top insulation

134, 234‧‧‧ conductive mask layer

135, 335‧‧ ‧ insulating mask layer

140, 340‧‧‧ Charge trapping structure

141, 341‧‧‧ first dielectric layer

142, 342‧‧‧ second dielectric layer

150, 350‧‧‧ channel layer

160, 260, 360, 460‧‧‧

170, 370‧‧‧ spaced insulation

370G‧‧‧Air gap

380‧‧‧ bottom conductive layer

390‧‧‧Connection layer

D‧‧‧汲

G‧‧‧ gate

T1, T2, T3, T4, T5, T6‧‧‧ thickness

S‧‧‧ source

W1, W2‧‧‧ width

Figure 1 illustrates a semiconductor device.

2A-2F are flow charts showing a method of manufacturing a semiconductor device according to an embodiment.

3A to 3F are flowcharts showing a method of manufacturing a semiconductor device according to another embodiment.

Figure 4 illustrates another semiconductor device.

5A-5F are flow charts showing a method of fabricating a semiconductor device according to an embodiment.

6A-6F are flow charts showing a method of fabricating a semiconductor device according to another embodiment.

The following is a detailed description of various embodiments, which utilize an etched portion of a charge trapping structure and a landing pad layer to form a thick and wide landing pad. Connect firmly to a bit line. However, the examples are for illustrative purposes only and are not intended to limit the scope of the invention. In addition, the drawings in the embodiments omit unnecessary elements to clearly show the technical features of the present invention.

Please refer to FIG. 1 , which illustrates a schematic diagram of a semiconductor device 100 . For example, the semiconductor device 100 can be a three-dimensional vertical channel NAND device. The semiconductor device 100 includes a substrate 110, a bottom insulating layer 120, at least two stacked structures 130, a charge trapping structure 140, a channel layer 150, and a connection. The pad layer 160 and a spaced insulating layer 170. In this embodiment, electricity The charge trapping structure 140 and the channel layer 150 are U-shaped.

Each of the stacked structures 130 includes a plurality of gate layers 131, a plurality of gate insulating layers 132, a top insulating layer 133, and a conductive mask layer. 134. The charge trapping structure 140 includes a plurality of first dielectric layers 141 and a plurality of second dielectric layers 142. Each gate layer 131 is connected to a gate G. The pad layer 160 is connected to a source S or a drain D.

The pad layer 160 is connected to a one-dimensional line. As shown in FIG. 1, since the thickness T1 of the combination of the conductive mask layer 134 and the pad layer 160 is larger than the thickness T2 of the channel layer 150, the contact resistance between the bit line and the pad layer 160 can be lowered. In addition, the connection process between the bit line and the pad layer 160 is also made easier. In addition, the connection of the channel layer 150 and the pad layer 160 is located on the sidewall of the channel layer 150 rather than at the top of the channel layer 150. In this way, you can increase the process window and reduce the resistance. Moreover, the corner edge effect does not occur in this structure, because the first dielectric layer 141 is not located at any corner edge, so it is not easily stylized or erased by the electric field effect. .

Please refer to FIGS. 2A-2F for a flow chart of a method of fabricating a semiconductor device 100 in accordance with an embodiment. The manufacturing process is self-aligned and does not require an additional masking process. As shown in FIG. 2A, a substrate 110 is provided. Next, as shown in FIG. 2A, a bottom insulating layer 120 is formed on the substrate 110. For example, the material of the bottom insulating layer 120 is, for example, silicon oxide.

Then, as shown in FIG. 2A, the gate layer 131 and the gate insulating layer 132 are alternately formed on the bottom insulating layer 120 so that the respective gate layers 131 can be insulated from each other. The material of each of the gate layers 131 is, for example, N+ or P+ doped polysilicon, preferably P+ doped polysilicon. The material of each of the gate insulating layers 132 is, for example, yttrium oxide.

Next, as shown in FIG. 2A, a top insulating layer 133 is formed on the gate layer 131 and the gate insulating layer 132. The material of the top insulating layer 133 is, for example, silicon nitride.

Then, as shown in FIG. 2A, a conductive mask layer 134 is formed on the top insulating layer 133 to prevent the top insulating layer 133 from being etched, and can be used to connect the pad layer 160 (shown in FIG. 1) and the channel layer. 150 (shown in Figure 1).

Next, as shown in FIG. 2A, an insulating mask layer 135 is formed on the conductive mask layer 134. The material of the insulating mask layer 135 is, for example, tantalum nitride.

Then, as shown in FIG. 2B, the insulating mask layer 135, the conductive mask layer 134, the top insulating layer 133, the gate layer 131, and the gate insulating layer 132 are etched to form at least two stacked structures 130 and interphase Adjacent to the trench 130a of the stacked structure 130. The insulating mask layer 135 can stabilize the stacked structure 130 during fabrication to avoid collapse of the stacked structure 130.

Next, as shown in FIG. 2C, the charge trapping structure 140 and the channel layer 150 are formed on one of the side surfaces 130b of one of the stacked structures 130 and one of the upper surfaces 120a of the bottom insulating layer 120. The charge trapping structure 140 and the channel layer 150 are U-shaped. The material of the channel layer 150 may be an intrinsic or undoped polysilicon. Charge trapping structure 140 may be an O1N1O2N2O3N3O4 structure (O1 is close to channel layer 150, and O4 is close to stack structure 130). The four hafnium oxide layers (O1, O2, O3, O4) have different thicknesses and the three tantalum nitride layers (N1, N2, N3) have different thicknesses. Alternatively, the charge trapping structure 140 can be an O1N1O2N2O3 structure (O1 is close to the channel layer 150, and O3 is close to the stacked structure 130). The three yttrium oxide layers (O1, O2, O3) have different thicknesses, and the two tantalum nitride layers (N1, N2) have different thicknesses. These different thicknesses are designed for the purpose of O1N1O2 tunneling, N2 trapping, O3 or O3N3O4 blocking.

Next, as shown in FIG. 2C, the spacer insulating layer 170 is filled in the trench 130a between the stacked structures 130. The material of the spacer insulating layer 170 is, for example, yttrium oxide. The spacer insulating layer 170 may not completely fill the trench 130a such that an air gap is formed in the spacer insulating layer 170. Air is also a good insulator.

Furthermore, as shown in FIG. 2D, portions of each of the first dielectric layers 141 are etched to expose portions of the respective second dielectric layers 142. In this step, cesium nitride is etched using phosphoric acid (H3PO4). Since phosphoric acid is highly selective for polysilicon and yttrium oxide, conductive mask layer 134, channel layer 150, second dielectric layer 142, and spacer insulating layer 170 are not etched at this step. In this step, the insulating mask layer 135 (shown in FIG. 2C) is also removed such that the surface of the conductive mask layer 134 is exposed. Since portions of each of the first dielectric layers 141 are etched, the two sidewalls of at least one of the second dielectric layers 142 are partially exposed.

Due to the difference in thickness of the first dielectric layer 141, the first dielectric layer 141 is etched to different depths under an etching loading effect.

Next, as shown in FIG. 2E, portions of each of the second dielectric layers 142 are etched to expose portions of the via layer 150. In this step, the cerium oxide is etched using a dilute hydrofluoric acid solution (DHF). Since the dilute hydrofluoric acid solution is highly selective for polysilicon and tantalum nitride, the conductive mask layer 134, the channel layer 150, and the first dielectric layer 141 are not etched.

In this step, since portions of the respective second dielectric layers 142 are etched, the two sidewalls of the respective first dielectric layers 141 are partially exposed. Moreover, since a portion of the pitch insulating layer 170 is also etched, the two sidewalls of the channel layer 150 are also partially exposed, such that the top end of the channel layer 150 is higher than the top end of the first dielectric layer 141 and the second dielectric layer. The top of 142.

Due to the different thicknesses of the second dielectric layer 142, the second dielectric layer 142 is etched to different depths under the etch effect. In this step, the conductive mask layer 134 can prevent the top insulating layer 133 from being etched.

Next, as shown in FIG. 2F, a pad layer 160 is formed on the conductive mask layer 134, the first dielectric layer 141, and the second dielectric layer 142 to connect the conductive mask layer 134 and the channel layer 150. The material of the pad layer 160 is, for example, an N-type doped polysilicon.

In this step, the pad layer 160 and the channel layer 150 are further ground such that the tops of the pad layer 160, the channel layer 150, and the spacer insulating layer 170 are all at the same height. The combination of the conductive mask layer 134 and the pad layer 160 can be used as a pad to connect the bit lines. The thickness T1 of the combination of the conductive mask layer 134 and the pad layer 160 is greater than the thickness T2 of the channel layer 150, so that the contact resistance between the bit line and the pad layer 160 can be reduced. In addition, the connection between the channel layer 150 and the pad layer 160 is located The sidewall of the track layer 150, rather than the top of the channel layer 150. In this way, you can increase the process window and reduce the resistance. Furthermore, the connection process between the bit line and the pad layer 160 is also made easier. The corner edge effect does not occur in this structure because the first dielectric layer 141 is not located at any corner edge and is not easily stylized or erased by the electric field effect.

In the above manufacturing method, the insulating mask layer 135 is used to stabilize the stacked structure 130 during the process to prevent the stacked structure 130 from collapsing in the process. In another embodiment, the method of fabricating the semiconductor device may not use the insulating mask layer 135. Please refer to FIGS. 3A-3F for a flowchart of a method of fabricating the semiconductor device 200 of another embodiment. In this embodiment, the thickness of the conductive mask layer 234 is increased such that the conductive mask layer 234 can be used to stabilize the stacked structure 230.

As shown in FIG. 3F, the pad layer 260 and the conductive mask layer 234 are used as a pad to connect the bit lines. The thickness T3 of the conductive mask layer 234 and the pad layer 260 is greater than the thickness T2 of the channel layer 150, so that the contact resistance between the bit line and the pad layer 260 can be reduced. Furthermore, the process of connecting the bit line to the pad layer 260 is also made easier.

Please refer to FIG. 4 , which illustrates a schematic diagram of a semiconductor device 300 . For example, the semiconductor device 300 can be a three-dimensional vertical channel NAND device. The semiconductor device 300 includes a substrate 310, at least two stacked structures 330, a charge trapping structure 340, and a channel layer. 350, an insulating mask layer 335, a pad layer 360, a spaced insulating layer 370, a bottom conductive layer 380, and a connecting layer 390.

Each of the stacked structures 330 includes a plurality of gate layers 331 , a plurality of gate insulating layers 332 , and a top insulating layer 333 . The charge trapping device 340 includes a plurality of first dielectric layers 341 and a plurality of second dielectric layers 342 (second dielectric layers). Each gate layer 331 is connected to a gate G. The pad layer 360 is connected to the drain D. The bottom conductive layer 380 is connected to a source. The connection layer 390 connects the bottom conductive layer 380 and the channel layer 350.

The pad layer 360 is connected to a one-dimensional line. As shown in FIG. 4, since the thickness T4 of the pad layer 360 is greater than the thickness T5 of the channel layer 350, the contact resistance between the bit line and the pad layer 360 can be lowered. Furthermore, the pad layer 360 is further disposed on the spacer insulating layer 370. The width W1 of the pad layer 360 is relatively large, so that the connection process between the bit line and the pad layer 360 is also made easier. In addition, the connection of the channel layer 350 and the pad layer 360 is located on the sidewall of the channel layer 350 rather than at the top of the channel layer 350. In this way, you can increase the process window and reduce the resistance. Moreover, the corner edge effect does not occur in this structure, because the first dielectric layer 341 is not located at any corner edge, so it is not easily stylized or erased due to the electric field effect. .

Referring to FIGS. 5A-5F, a flow chart of a method of fabricating a semiconductor device 300 in accordance with an embodiment is shown. The manufacturing process is self-aligned and does not require an additional masking process. As shown in FIG. 5A, a substrate 310 is provided. then, As shown in FIG. 5A, a bottom conductive layer 380 is formed on the substrate 310.

Then, as shown in FIG. 5A, the gate layer 331 and the gate insulating layer 332 are alternately formed on the bottom conductive layer 380 so that the respective gate layers 331 can be insulated from each other. The material of each of the gate layers 331 is, for example, N+ or P+ doped polysilicon, preferably P+ doped polysilicon. The material of each of the gate insulating layers 332 is, for example, yttrium oxide.

Next, as shown in FIG. 5A, a top insulating layer 333 is formed on the gate layer 331 and the gate insulating layer 332. The material of the top insulating layer 333 is, for example, silicon nitride.

Next, as shown in FIG. 5A, an insulating mask layer 335 is formed on the top insulating layer 333. The material of the insulating mask layer 335 is, for example, tantalum nitride.

Then, as shown in FIG. 5B, the insulating mask layer 335, the top insulating layer, the gate layer 331 and the gate insulating layer 332 are etched to form at least two stacked structures 330 and trenches adjacent to the stacked structures 330. Slot 330a. The insulating mask layer 335 can stabilize the stacked structure 330 during fabrication to avoid collapse of the stacked structure 330.

Next, as shown in FIG. 5C, the charge trapping structure 340 and the channel layer 350 are formed on one side surface 330b of each of the stacked structures 330. A connection layer 390 is formed on the top surface of the bottom conductive layer 380 to connect the bottom conductive layer 380 and the channel layer 350. The material of the channel layer 350 may be an intrinsic or undoped polysilicon. The charge trapping structure 340 can be an O1N1O2N2O3N3O4 structure (O1 is close to the channel layer 150, and O4 is close to the stacked structure 330). Four layers of yttria (O1, O2, O3, O4) has different thicknesses and three tantalum nitride layers (N1, N2, N3) have different thicknesses. Alternatively, the charge trapping structure 340 can be an O1N1O2N2O3 structure (O1 is close to the channel layer 350, and O3 is close to the stacked structure 130). The three yttrium oxide layers (O1, O2, O3) have different thicknesses, and the two tantalum nitride layers (N1, N2) have different thicknesses. These different thicknesses are designed for the purpose of O1N1O2 tunneling, N2 trapping, O3 or O3N3O4 blocking.

Next, as shown in FIG. 5C, the spacer insulating layer 370 is filled in the trench 330a between the stacked structures 330. The material of the spacer insulating layer 370 is, for example, ruthenium oxide. The spacer insulating layer 370 may not completely fill the trench 330a such that the air gap 370G is formed in the spacer insulating layer 370. Air is also a good insulator.

Furthermore, as shown in FIG. 5D, portions of each of the second dielectric layers 342 are etched to expose portions of the respective first dielectric layers 341. In this step, the cerium oxide is etched using a dilute hydrofluoric acid solution (DHF). Since the diluted hydrofluoric acid solution is highly selective for polysilicon and tantalum nitride, the insulating mask layer 335, the channel layer 350, and the first dielectric layer 341 are not etched. Since portions of each of the second dielectric layers 342 are etched, the two sidewalls of at least one of the first dielectric layers 341 are partially exposed. Moreover, since a portion of the spacer insulating layer 370 is also etched, the sidewalls of the channel layer 350 are partially exposed.

Due to the different thicknesses of the second dielectric layer 342, the second dielectric layer 342 is etched to different depths under the etching loading effect.

Next, as shown in FIG. 5E, portions of the respective first dielectric layers 341 are etched. In this step, cesium nitride is etched using phosphoric acid (H3PO4). by Since phosphoric acid is highly selective for polycrystalline germanium and germanium oxide, the channel layer 350, the second dielectric layer 342, and the spacer insulating layer 370 are not etched at this step. In this step, the insulating mask layer 335 is also recessed.

In this step, since portions of the respective first dielectric layers 341 are etched, the two sidewalls of the respective second dielectric layers 342 are partially exposed. As such, the top end of the channel layer 350 is higher than the top end of the first dielectric layer 341 and the top end of the second dielectric layer 342.

Due to the different thicknesses of the first dielectric layer 341, the first dielectric layer 341 is etched to different depths under the etching effect.

Next, as shown in FIG. 5F, a pad layer 360 is formed on the first dielectric layer 341, the second dielectric layer 342, and the spacer insulating layer 370 to connect the channel layer 350. The material of the pad layer 360 is, for example, an N-type doped polysilicon.

The pad layer 360 can be used as a pad to connect the bit lines. The thickness T4 of the pad layer 360 is greater than the thickness T5 of the channel layer 350, so that the contact resistance between the bit line and the pad layer 360 can be lowered. In addition, the connection of the channel layer 350 and the pad layer 360 is located on the sidewall of the channel layer 350 rather than at the top of the channel layer 350. In this way, you can increase the process window and reduce the resistance. Moreover, the width W1 of the pad layer 360 is relatively large, so that the connection process for the bit line and the pad layer 360 is also made easier. The corner edge effect does not occur in this structure because the first dielectric layer 341 is not located at any corner edge and is not easily stylized or erased by the electric field effect.

In the above manufacturing method, the insulating mask layer 335 is used in the manufacturing process. The stacked structure 330 is stabilized to avoid collapse of the stacked structure 330 during the process. In another embodiment, the method of fabricating the semiconductor device may not use the insulating mask layer 335. Please refer to FIGS. 6A-6F for a flowchart of a method of fabricating the semiconductor device 400 of another embodiment. In this embodiment, the thickness of the top insulating layer 433 is increased such that the top insulating layer 433 can be used to stabilize the stacked structure 430.

As shown in FIG. 6F, the pad layer 460 is used as a pad to connect the bit lines. The thickness T6 of the pad layer 460 is greater than the thickness T5 of the channel layer 350 such that the contact resistance between the bit line and the pad layer 460 can be reduced. Moreover, the width W2 of the pad layer 460 is relatively large, so that the connection process for the bit line and the pad layer 460 is also made easier.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor device

110‧‧‧Substrate

120‧‧‧Bottom insulation

130‧‧‧Stack structure

131‧‧‧ gate layer

132‧‧‧ gate insulation

133‧‧‧Top insulation

134‧‧‧conductive mask layer

140‧‧‧Charge trapping structure

141‧‧‧First dielectric layer

142‧‧‧Second dielectric layer

150‧‧‧channel layer

160‧‧‧Pushing layer

170‧‧‧ spaced insulation

D‧‧‧汲

G‧‧‧ gate

S‧‧‧ source

T1, T2‧‧‧ thickness

Claims (9)

A method of fabricating a semiconductor device includes: forming a two-stack structure on a substrate, wherein each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, and a top insulating layer, the gate layers and the gate layer The gate insulating layers are alternately disposed, the top insulating layer is disposed on the gate layers and the gate insulating layers; forming a charge trapping structure and a channel layer on one side surface of each of the stacked structures, wherein each The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers; etching each of the first dielectric layers and etching portions of the second dielectric layers to expose portions of the channels And forming a landing pad layer on the first dielectric layer and the second dielectric layers to connect the channel layer. The method of fabricating a semiconductor device according to claim 1, wherein in the step of etching each of the first dielectric layers, each of the first dielectric layers is etched to a different depth, and each of the etched portions In the step of the second dielectric layer, each of the second dielectric layers is etched to a different depth. The method of fabricating a semiconductor device according to claim 1, wherein in the step of etching each of the first dielectric layers, the two sidewalls of at least one of the second dielectric layers are partially exposed. Stepping on each of the second dielectric layers in the etched portion In the step, the two sidewalls of at least one of the first dielectric layers are partially exposed. The method for fabricating a semiconductor device according to claim 1, further comprising: filling a spacer insulating layer in a trench, the trench being formed between the stacked structures; wherein each of the etching portions In the step of the two dielectric layers, part of the spacer insulating layer is also etched such that the top end of the channel layer is higher than the top ends of the first dielectric layers and the top ends of the second dielectric layers. The method of fabricating a semiconductor device according to claim 4, wherein in the step of forming the pad layer, the pad layer is further formed on the spacer insulating layer. The manufacturing method of the semiconductor device of claim 1, wherein in the step of forming the stacked structures, each of the stacked structures further comprises a conductive mask layer, and the conductive mask layer is disposed on the top insulating layer The step of forming the pad layer is further formed on the conductive mask layer. A semiconductor device comprising: a stacking structure, each of the stacking structures includes: a plurality of gate layers and a plurality of gate insulating layers, the gate layers and the gate insulating layers are alternately disposed; and a top insulating layer is disposed on The gate layer and the gate insulating layer; a charge trapping structure and a channel layer disposed on one side surface of each of the stacked structures, wherein each of the charge trapping structures comprises a plurality of first dielectric layers and a plurality of a second dielectric layer, the top of the channel layer is higher than the top of each of the first dielectric layers and the top of each of the second dielectric layers; a pad layer contacting the first dielectric layers and the The second dielectric layer is connected to the channel layer; and a spacer insulating layer is disposed in one of the trenches between the stacked structures, wherein the pad layer is further disposed on the spacer insulating layer. The semiconductor device of claim 7, wherein the tops of the first dielectric layers are at different heights, and the tops of the second dielectric layers are at different heights. The semiconductor device of claim 7, wherein the thickness of the pad layer is greater than the thickness of the channel layer.