TWI555127B - Memory device and method for fabricating the same - Google Patents

Description

Memory element and manufacturing method thereof

The present disclosure relates to a non-volatile memory element and a method of fabricating the same. In particular, there is a three-dimension (3D) non-volatile memory element and a method of fabricating the same.

Non-Volatile Memory (NVM) components, such as flash memory, have the property of not losing information stored in the memory unit when the power is removed. It has been widely used in solid-state mass storage applications for portable music players, mobile phones, digital cameras, and the like. Three-dimensional non-volatile memory components, such as vertical-channel (VC) three-dimensional NAND flash memory components, have many layer stack structures, can achieve higher storage capacity, and have superior electronic characteristics, such as Good data retention reliability and speed of operation.

A typical three-dimensional non-volatile memory element is composed of a plurality of multi-layer stacks in which an insulating layer and a conductive layer which are parallel to each other are alternately stacked. Please refer to FIG. 1 . FIG. 1 is a schematic cross-sectional view of a multi-layer structure 100 of a three-dimensional non-volatile memory device according to the prior art. Wherein, the multi-layer structure 100 includes at least one trench 101, and the multi-layer structure is divided into a plurality of ridge-shaped stacks 102, so that each ridge-shaped multilayer stack 102 has a plurality of patterns A conductive strip 102a formed by a conductive layer. The three-dimensional non-volatile memory element also includes a memory material layer 103 and a channel layer 104. Wherein, the memory material layer 103 is located on the sidewall of the trench 101; the channel layer 104 covers the ridge multilayer stack 102 and the memory material layer 103, and in each of the conductive strips 102a and the memory material layer 103 and the channel layer 104 The overlapping positions define a plurality of memory cells 105. The vertically aligned memory cells are vertically connected in series to form a memory cell string and are electrically connected to corresponding bit lines (not shown) through the metal contact structure 106. Therein, a metal contact structure 106 is formed over a portion of the channel layer 104 overlying the top of the ridge multilayer stack 102.

However, to provide better control of the components, the thickness of the channel layer 104 is generally relatively thin, such that the process window is rather limited (or even insufficient) when defining the metal contact structure 106 on the channel layer 104. In addition, the channel layer 104 is generally composed of polysilicon, which forms a metal silicide junction with the barrier layer of the metal contact structure 106, and the thin via layer 104 easily causes voids in the metal germanium junction (voids) And causing a problem that the contact resistance value is high between the metal contact structure 106 and the channel layer 104.

Therefore, there is a need to provide a more advanced memory component and method of making the same to improve the problems faced by conventional techniques.

According to an embodiment of the present specification, a memory component is provided, It includes a patterned multilayer stack structure, a semiconductor capping layer, a memory material layer, and a channel layer. The patterned multilayer stack structure is located on the substrate and has at least one trench to define a plurality of ridge multilayer stacks, wherein each ridge multilayer stack includes at least one conductive strip. A semiconductor cap layer overlies the ridge multilayer stack. A layer of memory material overlies the sidewalls of the trench. The channel layer overlies the memory material layer, the semiconductor cap layer, and the bottom of the trench and is in direct contact with the semiconductor cap layer.

According to another embodiment of the present specification, a method of fabricating a memory device is provided, comprising the steps of first providing a multilayer stack structure on a substrate. A semiconductor cap layer is formed over the multilayer stack structure. Then, the multilayer stack structure and the semiconductor cap layer are patterned, whereby at least one trench is formed in the multilayer stack structure to define a plurality of ridge multilayer stacks, and each of the ridge multilayer stacks includes at least one conductive strip . Thereafter, a layer of memory material is formed covering the semiconductor cap layer and the sidewalls and bottom of the trench. Subsequently, a portion of the memory material layer on the bottom of the semiconductor cap layer and trench is removed, and a channel layer is formed overlying the memory material layer, the semiconductor cap layer, and the bottom of the trench and in direct contact with the semiconductor cap layer.

According to the above embodiment, the present invention provides a three-dimensional memory element and a method of fabricating the same. The three-dimensional memory device is formed by additionally forming a semiconductor cap layer over the multi-layer stack structure, and then forming a plurality of trenches to separate the multi-layer stack structure and the semiconductor cap layer into a plurality of ridge-shaped multilayer stacks. . Subsequent formation of a memory material layer and a channel layer on the sidewalls of the trench, thereby defining A plurality of memory cells are outputted and vertically connected in series to at least one memory cell. Wherein, the semiconductor cap layer and the channel layer are in direct contact.

Since the semiconductor cap layer can be integrated with the channel layer covering the top of the multi-layer stack structure to form a contact region having a larger thickness, the metal contact structure subsequently formed on the contact region can have a larger process margin. At the same time, the contact area with larger thickness can provide more polycrystalline germanium, and the metal contact structure forms a metal germanide layer with smaller grain structure, thereby reducing the generation of voids and effectively reducing the metal contact structure and the channel layer. Contact resistance between. Moreover, since the semiconductor cap layer covers only the top of the multilayer stack structure, it does not increase the channel layer thickness of the memory cells located on the sidewalls of the trench. Therefore, it is possible to balance the control performance of the components.

100‧‧‧Multilayer structure

101‧‧‧ trench

102‧‧‧ ridge multilayer laminate

102a‧‧‧ Conductive strips

103‧‧‧ memory material layer

104‧‧‧Channel layer

105‧‧‧ memory cells

106‧‧‧Metal contact structure

200‧‧‧Three-dimensional memory components

201‧‧‧Substrate

202‧‧‧Semiconductor overlay

202a-202d‧‧‧ covered part of the patterning

202f‧‧‧Top surface of the semiconductor overlay

203‧‧‧Pattern Process

204‧‧‧ trench

204a‧‧‧ trench sidewall

205‧‧‧ Conductive strips

206‧‧‧ memory material layer

207‧‧‧ etching step

208‧‧‧ etchback process

209‧‧‧channel layer

210‧‧‧Multilayer stacking structure

210a-210d‧‧‧ ridge multilayer laminate

211-217‧‧‧ Conductive layer

219‧‧‧ grain interface

220‧‧‧Contact electrode

220a‧‧‧ barrier layer

222‧‧‧ openings

221-227‧‧‧Insulation

230‧‧‧ dielectric layer

300‧‧‧Three-dimensional memory components

301‧‧‧Semiconductor film

302‧‧ ‧ alcove

303‧‧‧Grain interface

The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood. FIG. 2 is a cross-sectional view showing a multi-layered structure of a three-dimensional non-volatile memory device; FIG. 2 is a perspective view showing a structure of a multi-layer stacked structure according to an embodiment of the present invention; FIGS. 2A to 2G A cross-sectional view of a process structure for fabricating a three-dimensional memory device in a multi-layer stacked structure is shown along a tangent line S2 of FIG. 2; and FIGS. 3A to 3E are diagrams showing a three-dimensional memory according to another embodiment of the present invention. A cross-sectional view of the process structure of the component.

The invention provides a three-dimensional memory component and a manufacturing method thereof, which can provide a large process margin of a three-dimensional memory component to form a metal contact structure and reduce the contact resistance of the metal contact structure. The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.

However, it must be noted that these specific embodiments and methods are not intended to limit the invention. The invention may be practiced with other features, elements, methods and parameters. The preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the invention. Equivalent modifications and variations will be made without departing from the spirit and scope of the invention. In the different embodiments and the drawings, the same elements will be denoted by the same reference numerals.

A method of making a three-dimensional memory element 200 includes the steps of first forming a multilayer stack structure 210 on a substrate 201. Please refer to FIG. 2 and FIG. 2A to FIG. 2G. FIG. 2 is a perspective view showing the structure of the multilayer stack structure 210 according to an embodiment of the present invention; FIG. 2A to FIG. 2G are along the second line. A tangent line S2 of the figure shows a cross-sectional view of a process structure for fabricating the stereo memory element 200 in the multilayer stack structure 210.

In some embodiments of the invention, the multilayer stack structure 210 includes a plurality of conductive layers 211-217 formed on a substrate 201 and a plurality of insulating layers 221-227. The insulating layers 221-227 and the conductive layers 211-217 are staggered with each other on the substrate 201 along the Z-axis direction depicted in FIG. 2, and are parallel to each other. In the present embodiment, the conductive layer 211 is located at the bottommost layer of the multilayer stack structure 210, and the insulating layer 227 is located at the top layer of the multilayer stack structure 210.

Conductive layers 211-217 can be constructed of a metal such as gold, copper, aluminum or other metal or alloy materials. In addition, the conductive layers 211-217 may also be composed of a semiconductor material such as tantalum, niobium or other doped or undoped semiconductor material. In the present embodiment, the conductive layers 211-217 are composed of undoped crystals. The insulating layers 221-227 may be composed of a dielectric material such as an oxide, a nitride, an oxynitride, a silicate or the like. In some embodiments of the present invention, the conductive layers 211-217 and the insulating layers 221-227 can be fabricated by, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) process. The thickness of the insulating layers 221-227 may be substantially between 20 nm and 40 nm.

Thereafter, a semiconductor cap layer 202 is formed on the multilayer stack structure 210 (as shown in FIGS. 2 and 2A). The semiconductor cap layer 202 is formed on the topmost insulating layer 227 of the multilayer stack structure 210. In some embodiments of the present invention, the semiconductor cap layer 202 is formed in the same manner as the conductive layers 211-217, but is not limited thereto. The material of the semiconductor cap layer 202 may preferably be polysilicon. The thickness of the semiconductor cap layer 202 is substantially between 300 Å and 500 Å.

Next, the multilayer stack structure 210 and the semiconductor cap layer 202 A patterning process 203 is performed to form a plurality of ridge multilayer laminates 210a, 210b, 210c, and 210d and a patterned semiconductor cap layer 202 overlying the ridge multilayer stacks 210a, 210b, 210c, and 210d (as depicted in FIG. 2B) Show). In some embodiments of the present invention, the patterning process 203 of the multilayer stack structure 210 and the semiconductor cap layer 202 includes patterning a hard mask layer (not shown) as an etch mask by an anisotropic etch process ( An anisotropic etching process, such as a reactive ion etch (RIE) process, etches the semiconductor cap layer 202 and the multilayer stack structure 210. By forming a trench 204 extending along the Z-axis direction among the semiconductor cap layer 202 and the multilayer stack structure 210, the multilayer stack structure 210 is divided into a plurality of ridge-shaped multilayer stacks extending in the Y-axis direction, such as ridges. The multilayer stacks 210a, 210b, 210c, and 210d expose a portion of the substrate 201 to the outside via the trenches 204. The semiconductor cover layer 202 is divided into a plurality of cover portions separated from each other, such as cover portions 202a, 202b, 202c, and 202d.

In the present embodiment, each of the ridge multilayer laminates 210a, 210b, 210c, and 210d includes a conductive strip 205 formed of a portion of the conductive layers 211-217. The cover portions 202a, 202b, 202c, and 202d of the patterned semiconductor cap layer 202 cover each of the ridge-like multilayer stacks 210a, 210b, 210c, and 210d, respectively.

Then, a memory material layer 206 is formed over the ridge multilayer stacks 210a, 210b, 210c, and 210d to cover the covered portions 202a, 202b, 202c, and 202d of the patterned semiconductor cap layer 202 and the bottom of the trench 204 (ie, The trench 204 is exposed to a portion of the outer substrate 201) and the trench sidewalls 204a (as depicted in FIG. 2C). In some embodiments of the invention, the memory material layer 206 comprises at least oxidation A composite layer of a silicon oxide layer, a silicon nitride layer, and a ruthenium oxide layer (ie, an ONO layer). In other embodiments of the present invention, the memory material layer 206 may be a Silicon Oxide Nitric Oxide Silicon (SONOS) structure (but not limited thereto). In this embodiment, the memory material layer 206 may be an ONO composite layer fabricated by a low pressure chemical vapor deposition process.

After forming the memory material layer 206, an etching step 207 is performed on the memory material layer 206 to remove overlying the cover portions 202a, 202b, 202c, and 202d, and a portion of the memory material layer overlying the bottom of the trench 204. 206, exposing the patterned semiconductor cap layer 202 to the outside, and exposing a portion of the substrate 201 to the outside via the trench 204 (as depicted in FIG. 2D). In some embodiments of the invention, the remaining layer of memory material 206 is preferably located only above sidewalls 204a of the trench.

In addition, in some embodiments of the present invention, after removing a portion of the memory material layer 206 overlying the cover portions 202a, 202b, 202c, and 202d and overlying the bottom of the trench 204, it is preferred to selectively perform one step. The etching process 208 is performed to remove a portion of the memory material layer 206 adjacent the opening of the trench 204 such that the memory material layer 206 is substantially lower than the top surface 202f of the patterned semiconductor cap layer 202 (as depicted in FIG. 2E).

Thereafter, conformal deposition is performed on the ridge multilayer laminates 210a, 210b, 210c, and 210d to form a channel layer 209 covering the memory material layer 206, the patterned semiconductor cap layer 202, and the trench 204. On the bottom, and the channel layer 209 and the top surface 202f of the patterned semiconductor cap layer 202 Direct contact (as shown in Figure 2F). In some embodiments of the present invention, the material constituting the channel layer 209 is a semiconductor material, and for example, it may preferably be a polysilicon, germanium or other suitable semiconductor material. The thickness of the channel layer 209 is substantially between 50 Å and 200 Å. In this embodiment, both the channel layer 209 and the patterned semiconductor cap layer 202 may be composed of polysilicon. Since the two are formed by different deposition processes, between the channel layer 209 and the patterned semiconductor cap layer 202, There will be a granular boundary 219 that can be observed by an electron microscope such as a Photoemission Electron Microscope (PEEM).

In addition, in the present embodiment, the channel layer 209 simultaneously covers the memory material layer 206, the patterned semiconductor cap layer 202, and the bottom of the trench 204. Thus, by the via layer 209, the patterned portions 204a, 202b, 202c, and 202d of the patterned semiconductor cap layer 202 on top of the ridge multilayer stacks 210a, 210b, 210c, and 210d can be electrically conducted.

Thereafter, a plurality of contact electrodes 220 are formed on the channel layer 209 to be in direct contact with the channel layer 209. In some embodiments of the invention, the manner in which the contact electrode 220 is formed includes the step of first forming a dielectric layer 230, such as a tantalum oxide layer, on the ridge multilayer stacks 210a, 210b, 210c, and 210d. The channel layer 209 is used as an etch stop layer, and the dielectric layer 230 is etched to form a plurality of openings 222 in the dielectric layer 230 to expose the covered portions 202a, 202b, 202c, and 202d of the patterned semiconductor cap layer 202. outer. Subsequently, the barrier layer 220a is further formed in the opening 222, and is made of a metal material such as gold (Au), copper (Cu), aluminum (Al) or the like. A suitable metal or alloy fill fills the opening 222 to form the contact electrode 220 in the opening 222. Subsequently, the preparation of the stereo memory device 300 is completed via a series of back-end processes (not shown) (as shown in FIG. 2G).

Since the patterned semiconductor cap layer 202 and the channel layer 209 are both made of a semiconductor material, they can be integrated into a thick contact region, which provides a process margin for defining an opening 222 with a large etching process. In addition, the contact region having a larger thickness can also prevent voids in the metal telluride layer formed between the channel layer 209 and the barrier layer 220a, and the contact resistance between the contact electrode 220 and the channel layer 209 is lowered.

Referring to FIGS. 3A-3E, FIG. 3A to FIG. 3E are cross-sectional views showing a process structure for fabricating the stereo memory device 300 according to another embodiment of the present invention. The method of fabricating the stereo memory device 300 is similar to the method of fabricating the stereo memory component 200, except that the method of fabricating the stereo memory component 300 includes before performing the etching step 207 to remove a portion of the memory material layer 206. A semiconductor film 301 is selectively formed on the memory material layer 206. For the sake of brevity, the present embodiment begins with FIG. 3A, wherein FIG. 3A is continued to the 2Cth diagram, and the same process before the 2Cth embodiment will be omitted and will not be described again.

In some embodiments of the invention, the semiconductor film 301 may be a semiconductor coating that is blanketed on the memory material layer 206 by a low pressure chemical vapor deposition process. The material of the semiconductor thin film 301 is preferably polycrystalline germanium. The thickness of the semiconductor film 301 is substantially between 100 Å and 300 Å. In the present embodiment, the thickness of the semiconductor thin film 301 is preferably about 100 Å.

Thereafter, the semiconductor film 301 is used as an etch stop layer, and the memory material layer 206 is subjected to an etching step 207 to be removed on the covering portions 202a, 202b, 202c, and 202d, and a portion of the memory material covering the bottom of the trench 204. The layer 206 and the semiconductor film 301 expose the patterned semiconductor cap layer 202 on top of the ridge multilayer stacks 210a, 210b, 210c, and 210d, and expose a portion of the substrate 201 to the outside via the trench 204 (eg, 3B is shown). In the present embodiment, the remaining memory material layer 206 is only located on the sidewall 204a of the trench, and the remaining semiconductor film 301 covers the remaining memory material layer 206, forming a spacer on the sidewall 204a of the trench (spacer The remaining memory material layer 206 is protected from damage by subsequent etching processes.

After removing a portion of the memory material layer 206 overlying the cover portions 202a, 202b, 202c, and 202d and overlying the bottom of the trench 204, an etch back process 208 can be performed to remove portions of the opening adjacent the trench 204. The memory material layer 206 is such that the memory material layer 206 is substantially lower than the top surface 202f of the patterned semiconductor cap layer 202, and a plurality of recesses 302 are formed between the patterned semiconductor cap layer 202 and the semiconductor film 301 (as shown in FIG. 3C) Painted).

Thereafter, conformal deposition is performed on the ridge multilayer stacks 210a, 210b, 210c, and 210d to form a channel layer 209 overlying the memory material layer 206, the remaining semiconductor film 301, the patterned semiconductor cap layer 202, and the trench 204. The bottom layer and the channel layer 209 are in direct contact with the top surface 202f of the patterned semiconductor cap layer 202 and the remaining semiconductor film 301. The patterned semiconductor cap layer 202 is then placed on the ridge multilayer stack 210a, 210b, 210c by the via layer 209. The cover portions 202a, 202b, 202c, and 202d at the top of the 210d are electrically conductive (as shown in FIG. 3D).

Since the channel layer 209, the semiconductor film 301 and the patterned semiconductor cap layer 202 are all composed of polysilicon, the three are formed by different deposition processes, so the channel layer 209 and the patterned semiconductor cap layer 202 and the channel layer are formed. Between the 209 and the semiconductor film 301, there are respectively a grain boundaries 219 and 303 which can be observed by an electron microscope such as a light emission electron microscope. Wherein, the grain interfaces 219 and 303 are both U-shaped.

Thereafter, a plurality of contact electrodes 220 are formed on the channel layer 209 to be in direct contact with the channel layer 209. In some embodiments of the invention, the manner in which the contact electrode 220 is formed includes the step of first forming a dielectric layer 230, such as a tantalum oxide layer, on the ridge multilayer stacks 210a, 210b, 210c, and 210d. The channel layer 209 is used as an etch stop layer, and the dielectric layer 230 is etched to form a plurality of openings 222 in the dielectric layer 230 to expose the covered portions 202a, 202b, 202c, and 202d of the patterned semiconductor cap layer 202. outer. A barrier layer 220a is then formed in the opening 222 and the opening 222 is filled with a metallic material, such as gold, copper, aluminum, or other suitable metal or alloy material to form the contact electrode 220 in the opening 222. Subsequently, the preparation of the stereo memory component 300 is completed via a series of back-end processes (not shown) (as shown in FIG. 3E).

Since the patterned semiconductor cap layer 202 and the channel layer 209 are both made of a semiconductor material, they can be integrated into a thick contact region, which provides a process margin for defining an opening 222 with a large etching process. In addition, the thicker contact area can also be prevented The metal germanide junction between the channel layer 209 and the barrier layer 220a creates a void which, in turn, results in a contact resistance between the metal contact structure 106 and the channel layer 104.

According to the above embodiment, the present invention provides a three-dimensional memory element and a method of fabricating the same. The three-dimensional memory device is formed by additionally forming a semiconductor cap layer over the multi-layer stack structure, and then forming a plurality of trenches to separate the multi-layer stack structure and the semiconductor cap layer into a plurality of ridge-shaped multilayer stacks. . Subsequently forming a memory material layer and a channel layer on the sidewall of the trench, a plurality of memory cells are defined and vertically connected in series to at least one memory cell string. Wherein, the semiconductor cap layer and the channel layer are in direct contact.

Since the semiconductor cap layer can be integrated with the channel layer covering the top of the multi-layer stack structure to form a contact region having a larger thickness, the metal contact structure subsequently formed on the contact region can have a larger process margin. At the same time, the contact area with larger thickness can provide more polycrystalline germanium to form a metal telluride layer with a smaller grain structure with the metal contact structure, thereby reducing the generation of voids and effectively reducing the contact between the metal contact structure and the channel layer. resistance. Moreover, since the semiconductor cap layer covers only the top of the multilayer stack structure, it does not increase the channel layer thickness of the memory cells located on the sidewalls of the trench. Therefore, it is possible to balance the control performance of the components.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

200‧‧‧Three-dimensional memory components

201‧‧‧Substrate

202a-202d‧‧‧ covered part of the patterning

204‧‧‧ trench

204a‧‧‧ trench sidewall

205‧‧‧ Conductive strips

206‧‧‧ memory material layer

209‧‧‧channel layer

210‧‧‧Multilayer stacking structure

210a-210d‧‧‧ ridge multilayer laminate

211-217‧‧‧ Conductive layer

219‧‧‧ grain interface

220‧‧‧Contact electrode

220a‧‧‧ barrier layer

222‧‧‧ openings

221-227‧‧‧Insulation

230‧‧‧ dielectric layer

Claims (8)

A memory component comprising: a patterned multi-layer stacks on a substrate having at least one trench to define a plurality of ridge multilayer stacks, each of which has a plurality of ridges The layer stack includes at least one conductive strip; a semiconductor capping layer covering the ridge multilayer stack; a memory material layer covering a sidewall of the trench; and a channel layer covering The memory material layer, the semiconductor cap layer and a bottom of the trench are in direct contact with the semiconductor cap layer; and a contact electrode is located above the semiconductor cap layer and in direct contact with the channel layer And electrically connecting the channel layer to a one-dimensional line. The memory element of claim 1, wherein the patterned multilayer stack structure comprises a plurality of insulating layers and a plurality of conductor layers staggered with each other. The memory device of claim 1, wherein the semiconductor cap layer and the channel layer each comprise a polysilicon, and the semiconductor cap layer and the channel layer have a granular boundary therebetween. For example, the memory component described in claim 1 of the patent scope includes a half lead A bulk spacer is located between the memory material layer and the channel layer and is in direct contact with the channel layer. A method of fabricating a memory device, comprising: providing a multi-layer stack structure on a substrate; forming a semiconductor cap layer overlying the multi-layer stack structure; patterning the multi-layer stack structure and the semiconductor cap layer, thereby Forming at least one trench in the multilayer stack structure to define a plurality of ridge multilayer stacks, and each of the ridge multilayer stacks includes at least one conductive strip; forming a memory material layer covering the semiconductor cover a layer and a sidewall and a bottom of the trench; removing a portion of the memory material layer on the semiconductor cap layer and the bottom of the trench; forming a channel layer covering the memory material layer, the semiconductor cap layer, and The bottom of the trench is in direct contact with the semiconductor cap layer; a contact electrode is formed over the semiconductor cap layer and in direct contact with the via layer, and the via layer is electrically connected to the one bit line. The method of fabricating a memory device according to claim 5, wherein the semiconductor cap layer is formed on a topmost insulating layer of the multilayer stack structure. The method of fabricating a memory device according to claim 5, wherein a semiconductor film is further formed on the memory material layer before the portion of the memory material layer is removed. The method of fabricating a memory device according to claim 5, wherein the semiconductor cap layer and the channel layer each comprise a polysilicon, and the semiconductor cap layer and the channel layer have a grain boundary.