TWI580012B - Memory device and method for fabricating the same - Google Patents
Memory device and method for fabricating the same Download PDFInfo
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Description
本揭露係有關於一種半導體結構及其製作方法。本揭露更特別是有關於一種記憶體元件及其製作法。 The disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to a memory component and a method of making the same.
近來,由於對於更優異之記憶體元件的需求已逐漸增加,已提供各種三維(3D)記憶體元件,例如是具有多層疊層結構的環繞式閘極垂直通道(Surrounding-Gate Vertical-Channel,SGVC)立體反及閘(3D NAND)記憶體元件。此類三維記憶體元件可達到更高的儲存容量,具有更優異的電子特性,例如是具有良好的資料保存可靠性和操作速度。 Recently, as the demand for more excellent memory elements has gradually increased, various three-dimensional (3D) memory elements have been provided, such as Surrounding-Gate Vertical-Channel (SGVC) having a multi-layered laminated structure. 3D NAND memory components. Such three-dimensional memory components can achieve higher storage capacity and have superior electronic characteristics, such as good data storage reliability and operation speed.
典型的SGVC 3D NAND記憶體元件,包括交替堆疊的複數個絕緣層和複數個導電層(conducting layer)所構成的堆疊結構(stacks)以及縱向穿過堆疊結構的複數個記憶層和通道層,在各個導電層與記憶層的重疊位置(intersections)定義出複數個NAND記憶胞,藉由通道層串連成複數條NAND記憶胞串列,並且通過接地選擇線(Ground selecting Line,GSL)電晶體與位於堆疊結構下方的接地層電性接觸。 A typical SGVC 3D NAND memory component includes stacked stacks of alternating insulating layers and a plurality of conducting layers and a plurality of memory and channel layers extending longitudinally through the stacked structure. The intersections of the respective conductive layers and the memory layer define a plurality of NAND memory cells, which are connected in series to form a plurality of NAND memory cell strings, and pass through a Ground Selection Line (GSL) transistor and The ground plane under the stack structure is in electrical contact.
由於,習知的接地層多以多晶矽材質所構成,阻值相對較大,容易產生電阻電壓降效應(IR drop effect)。為了改善以此缺點,一般會在記憶區塊(block)之間設置金屬接觸結構縱向穿過堆疊結構,藉以引導接地層的電流接地。然而金屬接觸結構的設置,相對壓縮了記憶胞串列的佈線空間,進而降低SGVC 3D NAND記憶體元件的儲存空間。 Since the conventional ground layer is mostly composed of a polycrystalline silicon material, the resistance value is relatively large, and an IR drop effect is easily generated. In order to improve this disadvantage, a metal contact structure is generally disposed between the memory blocks to longitudinally pass through the stacked structure, thereby guiding the current of the ground layer to be grounded. However, the arrangement of the metal contact structure relatively compresses the wiring space of the memory string, thereby reducing the storage space of the SGVC 3D NAND memory device.
因此,有需要提出一種先進的記憶體元件及其製作方法以解決習知技術所面臨的問題。 Therefore, there is a need to propose an advanced memory component and its fabrication method to solve the problems faced by the prior art.
在本揭露中,提供一種記憶體元件及其製作方法,以解決至少一部分上述問題。 In the present disclosure, a memory component and a method of fabricating the same are provided to address at least some of the above problems.
根據本發明之一實施例,記憶體元件包括一基板、一接地層、一疊層結構、複數條記憶胞串列。接地層位於基板上,其中接地層包括一金屬層。疊層結構位於接地層上,且疊層結構包括交替堆疊的複數個絕緣層和複數個導電層。複數條記憶胞串列穿過疊層結構而與金屬層電性接觸。 According to an embodiment of the invention, the memory component includes a substrate, a ground layer, a stacked structure, and a plurality of memory cells. The ground layer is on the substrate, wherein the ground layer comprises a metal layer. The stacked structure is on the ground layer, and the stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked. A plurality of memory cells are serially passed through the laminated structure to be in electrical contact with the metal layer.
根據本發明之一實施例,記憶體元件中的接地層可為一多層結構。接地層可更包括一半導體層,半導體層位於金屬層之上。 According to an embodiment of the invention, the ground layer in the memory element can be a multi-layer structure. The ground layer may further include a semiconductor layer on the semiconductor layer.
根據本發明之一實施例,記憶體元件的製作方法包括下列步驟。首先,在一基板上依序形成一第一犧牲層以及一疊層結構;其中,疊層結構包括交替堆疊的複數個第二犧牲層和複數個絕緣層。其次,形成複數個串列開口,串列開口穿過疊層結構將一部份第二犧牲層暴露於外。接著,於串列開口的複數個側 壁上依序形成複數個記憶層和複數個通道層,使每一通道層鄰接記憶層之一者,而與第一犧牲層接觸。接著,移除第一犧牲層及第二犧牲層。此後,填充一金屬材料,藉以於絕緣層之間形成複數個導電層並且於疊層結構與基板之間形成一金屬層。導電層鄰接每一記憶層,且金屬層與通道層電性接觸。 According to an embodiment of the invention, a method of fabricating a memory device includes the following steps. First, a first sacrificial layer and a stacked structure are sequentially formed on a substrate; wherein the stacked structure includes a plurality of second sacrificial layers and a plurality of insulating layers alternately stacked. Next, a plurality of tandem openings are formed, and the tandem openings pass through the stacked structure to expose a portion of the second sacrificial layer. Next, on the multiple sides of the series of openings A plurality of memory layers and a plurality of channel layers are sequentially formed on the wall such that each channel layer is adjacent to one of the memory layers and is in contact with the first sacrificial layer. Next, the first sacrificial layer and the second sacrificial layer are removed. Thereafter, a metal material is filled, whereby a plurality of conductive layers are formed between the insulating layers and a metal layer is formed between the stacked structure and the substrate. The conductive layer is adjacent to each memory layer, and the metal layer is in electrical contact with the channel layer.
根據本發明之一實施例,記憶體元件的製作方法中,在形成疊層結構之前更包括形成一半導體層於第一犧牲層上。 According to an embodiment of the present invention, in the method of fabricating a memory device, a semiconductor layer is further formed on the first sacrificial layer before forming the stacked structure.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式,作詳細說明如下。然而,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.
10‧‧‧記憶體元件 10‧‧‧ memory components
100‧‧‧記憶胞串列 100‧‧‧Memory cell series
102‧‧‧基板 102‧‧‧Substrate
104‧‧‧絕緣層 104‧‧‧Insulation
104a‧‧‧底部絕緣層 104a‧‧‧Bottom insulation
106‧‧‧導電層 106‧‧‧ Conductive layer
110、310‧‧‧疊層結構 110, 310‧‧‧ laminated structure
120‧‧‧記憶層 120‧‧‧ memory layer
140‧‧‧通道層 140‧‧‧channel layer
180‧‧‧介電材質 180‧‧‧ dielectric material
10A、10B、100A、100B、100C‧‧‧區塊 10A, 10B, 100A, 100B, 100C‧‧‧ blocks
306‧‧‧第二犧牲層 306‧‧‧Second sacrificial layer
300‧‧‧串列開口 300‧‧‧Sorted openings
330‧‧‧通孔 330‧‧‧through hole
350‧‧‧回蝕開口 350‧‧‧ etch back openings
320‧‧‧氧化物-氮化物-氧化物結構層 320‧‧‧Oxide-nitride-oxide structure
340a‧‧‧多晶矽覆蓋層 340a‧‧‧Polysilicon overlay
340b‧‧‧多晶矽層 340b‧‧‧Polysilicon layer
370‧‧‧導電材料 370‧‧‧Electrical materials
BL1...BLN‧‧‧位元線 BL 1 ...BL N ‧‧‧ bit line
G1‧‧‧金屬層 G1‧‧‧ metal layer
G2‧‧‧半導體層 G2‧‧‧ semiconductor layer
G10‧‧‧第一犧牲層 G10‧‧‧First Sacrifice Layer
GSL、GSL1、GSL2‧‧‧接地選擇線 GSL, GSL1, GSL2‧‧‧ Grounding selection line
GND‧‧‧接地層 GND‧‧‧ Ground plane
M‧‧‧記憶胞 M‧‧‧ memory cell
SSL、SSL1、SSL2、SSL3‧‧‧串列選擇線 SSL, SSL1, SSL2, SSL3‧‧‧ tandem selection line
WL‧‧‧字元線 WL‧‧‧ character line
第1圖繪示根據本揭露之一實施例之記憶體元件的上視圖。 1 is a top view of a memory element in accordance with an embodiment of the present disclosure.
第2圖繪示沿第1圖之A-A’連線之根據本揭露之一實施例之記憶體元件的剖面圖。 Figure 2 is a cross-sectional view of the memory device in accordance with an embodiment of the present disclosure taken along line A-A' of Figure 1.
第3A圖至第3M圖繪示根據本揭露之一實施例之記憶體元件之形成方法的剖面圖。 3A through 3M are cross-sectional views showing a method of forming a memory device in accordance with an embodiment of the present disclosure.
第4圖繪示根據本揭露之一實施例之記憶體元件的等效電路圖。 FIG. 4 is an equivalent circuit diagram of a memory element according to an embodiment of the present disclosure.
在下文的詳細描述中,為了便於解釋,係提供各種的特定細節以整體理解本揭露之實施例。然而,應理解的是,一或多個實施例能夠在不採用這些特定細節的情況下實現。在其他 情況下,為了簡化圖式,已知的結構及元件係以示意圖表示。 In the following detailed description, for the purposes of illustration However, it should be understood that one or more embodiments can be practiced without these specific details. In other In the simplification of the drawings, known structures and elements are schematically illustrated.
以下將說明所述記憶體元件及其製作方法。為易於解釋,以下的實施例將特別以三維記憶體元件(例如是三維垂直通道記憶體元件)為例。然而,本發明並不受限於此,舉例來說,所述記憶體元件及其製作方法可應用於其他非揮發性記憶體、一般的記憶體、或一般的記憶體元件。 The memory element and its method of fabrication will be described below. For ease of explanation, the following embodiments will be exemplified, inter alia, by three-dimensional memory elements, such as three-dimensional vertical channel memory elements. However, the present invention is not limited thereto. For example, the memory element and the method of fabricating the same can be applied to other non-volatile memory, general memory, or general memory elements.
請參照第1圖和第2圖,第1圖繪示根據本揭露之一實施例之記憶體元件10的上視圖;第2圖繪示沿第1圖之A-A’連線之根據本揭露之一實施例之記憶體元件10的剖面圖。 Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a top view of a memory device 10 according to an embodiment of the present disclosure. FIG. 2 is a diagram showing a connection along the A-A′ of FIG. 1 . A cross-sectional view of a memory component 10 of one embodiment is disclosed.
記憶體元件10包括一基板102、一接地層GND一疊層結構110和記憶胞串列100。接地層GND位於基板102上,其中接地層GND包括一金屬層G1。疊層結構110位於接地層GND上,且疊層結構110包括交替堆疊的複數個絕緣層104和複數個導電層106。記憶胞串列100穿過疊層結構110而與金屬層G1電性接觸。在本發明的一些實施例中,可藉由將這些記憶胞串列100排列成複數個子及(subset)的方式,將記憶體元件10區分為區塊10A及10B。 The memory device 10 includes a substrate 102, a ground layer GND-lamination structure 110, and a memory cell string 100. The ground layer GND is located on the substrate 102, wherein the ground layer GND includes a metal layer G1. The stacked structure 110 is located on the ground layer GND, and the stacked structure 110 includes a plurality of insulating layers 104 and a plurality of conductive layers 106 alternately stacked. The memory cell string 100 passes through the stacked structure 110 to be in electrical contact with the metal layer G1. In some embodiments of the invention, the memory elements 10 can be divided into blocks 10A and 10B by arranging the memory strings 100 into a plurality of subsets.
根據本發明之一實施例的記憶體元件10,由於記憶胞串列100穿過疊層結構110而與金屬層G1電性接觸,記憶胞之電流能夠直接聚集至位於下方的金屬層G1。並且,由於金屬層G1具有低電阻,能夠避免產生電阻電壓降效應,故能夠減少記憶區塊之間之金屬接觸結構的設置,使得記憶胞串列的佈線空間能夠增加,進而增加SGVC 3D NAND記憶體元件的儲存空間。 According to the memory device 10 of one embodiment of the present invention, since the memory cell string 100 is electrically contacted with the metal layer G1 through the stacked structure 110, the current of the memory cell can be directly concentrated to the underlying metal layer G1. Moreover, since the metal layer G1 has a low resistance, the resistance voltage drop effect can be avoided, so that the arrangement of the metal contact structure between the memory blocks can be reduced, so that the wiring space of the memory cell series can be increased, thereby increasing the SGVC 3D NAND memory. Storage space for body components.
在一些實施例中,每一記憶胞串列100包括一記憶 層120、一通道層140及複數個記憶胞M。記憶層120穿過疊層結構110而與導電層106鄰接。通道層140係鄰接記憶層120並與金屬層G1電性接觸。記憶胞M形成於導電層106與記憶層120的複數個重疊位置(intersections),並藉由通道層140彼此串聯。 In some embodiments, each memory string 100 includes a memory Layer 120, a channel layer 140, and a plurality of memory cells M. The memory layer 120 passes through the laminate structure 110 to abut the conductive layer 106. The channel layer 140 is adjacent to the memory layer 120 and is in electrical contact with the metal layer G1. The memory cell M is formed in a plurality of overlapping portions of the conductive layer 106 and the memory layer 120, and is connected in series to each other by the channel layer 140.
在一些實施例中,基板102及絕緣層104可由氧化物所形成,例如是二氧化矽。 In some embodiments, substrate 102 and insulating layer 104 may be formed of an oxide, such as hafnium oxide.
在一些實施例中,導電層106與金屬層G1可由相同的導電材料所組成,此導電材料可以是,例如鎢(W)或氮化鈦(TiN)。 In some embodiments, the conductive layer 106 and the metal layer G1 may be composed of the same conductive material, such as tungsten (W) or titanium nitride (TiN).
在一些實施例中,通道層140可由半導體材質所形成,例如是摻雜或未摻雜的多晶矽。記憶層120可以由包含氧化矽(silicon oxide)層、氮化矽(silicon nitride)層和氧化矽層的複合層(即,ONO層)所構成。 In some embodiments, the channel layer 140 can be formed of a semiconductor material, such as a doped or undoped polysilicon. The memory layer 120 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a hafnium oxide layer.
在本發明的一些實施例中,由於接地層GND具有金屬層G1,金屬層G1與通道層140的接觸區域可能會產生蕭基障壁(schottky barrier),恐對於接觸電阻之穩定性有不良的影響。因此,可以選擇性地(optionally)將接地層GND設計為一多層結構,藉由設置一半導體層G2於金屬層G1之上,使半導體層G2能夠幫助記憶胞M之電流集中於金屬層G1中,改善接觸電阻之穩定性。 In some embodiments of the present invention, since the ground layer GND has the metal layer G1, the contact area of the metal layer G1 and the channel layer 140 may generate a Schottky barrier, which may adversely affect the stability of the contact resistance. . Therefore, the ground layer GND can be selectively designed as a multilayer structure. By providing a semiconductor layer G2 over the metal layer G1, the semiconductor layer G2 can help the current of the memory cell M concentrate on the metal layer G1. Improve the stability of contact resistance.
例如,在本實施例中,接地層GND可以為一多層結構。接地層GND更包括一半導體層G2,半導體層G2位於金屬層G1之上。金屬層G1之導電性係高於半導體層G2之導電性。半導體層G2之厚度HG2係大於每一導電層106之厚度H106。其 中,半導體層G1可以是一種重摻雜之多晶矽(heavily doped poly-silicon)層。例如,重摻雜之多晶矽層的摻雜濃度可以實質大於1020/cm3。且重摻雜之多晶矽層可以是P型摻雜或者是N型摻雜。 For example, in the embodiment, the ground layer GND may have a multilayer structure. The ground layer GND further includes a semiconductor layer G2, and the semiconductor layer G2 is located above the metal layer G1. The conductivity of the metal layer G1 is higher than that of the semiconductor layer G2. The thickness H G2 of the semiconductor layer G2 is greater than the thickness H 106 of each of the conductive layers 106 . The semiconductor layer G1 may be a heavily doped poly-silicon layer. For example, the doping concentration of the heavily doped polysilicon layer may be substantially greater than 10 20 /cm 3 . The heavily doped polysilicon layer may be P-type doped or N-type doped.
在一些實施例中,每一記憶胞串列100中包括至少一條位於導電層106和接地層GND之間的接地選擇線(Ground Selecting Line,GSL)以及至少一個位於記憶胞M與接地層GND之間的接地選擇線電晶體T。 In some embodiments, each memory string 100 includes at least one Ground Selecting Line (GSL) between the conductive layer 106 and the ground layer GND and at least one of the memory cell M and the ground layer GND. The ground connection selects the transistor T.
在一些實施例中,每一記憶胞串列100中包括複數條接地選擇線以及複數個接地選擇線電晶體,例如在本實施例中,可選擇最靠近接地層GND的導電層106來做為接地選擇線(以下簡稱接地選擇線GSL1與GSL2),並將接地選擇線GSL1與GSL2與通道層140和記憶層120所定義的記憶胞M當作為接地選擇線電晶體(以下簡稱接地選擇線電晶體T1與T2)。在本實施例之中,接地選擇線電晶體T1及T2係位於其他記憶胞M與接地層GND之間,且每一接地選擇線電晶體T1及T2係被施加於不同的電壓。 In some embodiments, each memory string 100 includes a plurality of ground select lines and a plurality of ground select line transistors. For example, in this embodiment, the conductive layer 106 closest to the ground plane GND may be selected as Ground selection lines (hereinafter referred to as ground selection lines GSL1 and GSL2), and the ground selection lines GSL1 and GSL2 and the memory cells M defined by the channel layer 140 and the memory layer 120 are used as ground selection line transistors (hereinafter referred to as ground selection lines) Crystals T1 and T2). In the present embodiment, the ground selection line transistors T1 and T2 are located between the other memory cells M and the ground layer GND, and each of the ground selection line transistors T1 and T2 is applied to a different voltage.
由於半導體層G2可以是一重摻雜之多晶矽層,摻雜質恐逸散至通道層140中,進而造成接地選擇線GSL的漏電流(current leakage)。藉由設置複數條接地選擇線(例如是GSL1與GSL2)及複數個施加不同電壓之接地選擇線電晶體T1與T2的設計,能夠使電流的控制有更多選擇性,避免單一的接地選擇線產生漏電流,造成記憶體元件之功率消耗(power consumption)上升的問題。 Since the semiconductor layer G2 can be a heavily doped polysilicon layer, the dopants are dissipated into the channel layer 140, thereby causing current leakage of the ground selection line GSL. By setting a plurality of ground selection lines (for example, GSL1 and GSL2) and a plurality of ground selection line transistors T1 and T2 applying different voltages, current control can be more selective, avoiding a single ground selection line. Leakage current is generated, causing an increase in power consumption of the memory component.
在一些實施例中,通道層140可進一步穿過接地層 GND(在本實施例中包含金屬層G1和半導體層G2)延伸至基板102之中。藉由穿透疊層結構110和接地層GND的通道層140的連結,可將疊層結構110和接地層GND連結並紮根固定於基板102中。因此,在製造記憶體元件10的過程中,特別是蝕刻製程之後,並不需要另外設置支持結構以提供支撐,即可防止疊層結構110和接地層GND因缺乏支撐而抬升或移位。 In some embodiments, the channel layer 140 can further pass through the ground plane GND (including the metal layer G1 and the semiconductor layer G2 in this embodiment) extends into the substrate 102. The laminated structure 110 and the ground layer GND can be connected and fixed in the substrate 102 by the connection of the via layer 140 that penetrates the stacked structure 110 and the ground layer GND. Therefore, in the process of fabricating the memory device 10, particularly after the etching process, it is not necessary to additionally provide a supporting structure to provide support, thereby preventing the stacked structure 110 and the ground layer GND from being lifted or displaced due to lack of support.
藉由設置厚度大於其他絕緣層104之任一者的底部絕緣層104a,能夠防止半導體層G2所逸散的摻雜質,造成接地選擇線GSL的漏電流的問題。例如,在一些實施例中,絕緣層104具有最接近基板102的一底部絕緣層104a,且底部絕緣層104a與其他絕緣層104之任一者之間的厚度比值實質介於1至3之間。 By providing the bottom insulating layer 104a having a thickness larger than any of the other insulating layers 104, it is possible to prevent the doping property which the semiconductor layer G2 escapes, causing a problem of leakage current of the ground selection line GSL. For example, in some embodiments, the insulating layer 104 has a bottom insulating layer 104a closest to the substrate 102, and the thickness ratio between the bottom insulating layer 104a and any of the other insulating layers 104 is substantially between 1 and 3. .
在一些實施例中,記憶體元件10還包括填充於通道層340之中並覆蓋疊層結構110的介電材質180可。介電材質180可以是氧化物,例如是二氧化矽。 In some embodiments, the memory component 10 further includes a dielectric material 180 that is filled in the channel layer 340 and overlies the stacked structure 110. The dielectric material 180 can be an oxide such as cerium oxide.
第3A圖至第3M圖繪示根據本揭露之一實施例之記憶體元件之形成方法的剖面圖。 3A through 3M are cross-sectional views showing a method of forming a memory device in accordance with an embodiment of the present disclosure.
請參照第3A圖,在一基板102上依序形成一第一犧牲層G10以及一疊層結構310。疊層結構310包括交替堆疊的複數個第二犧牲層306和複數個絕緣層104。 Referring to FIG. 3A, a first sacrificial layer G10 and a stacked structure 310 are sequentially formed on a substrate 102. The stacked structure 310 includes a plurality of second sacrificial layers 306 and a plurality of insulating layers 104 that are alternately stacked.
在一些實施例中,在形成疊層結構310之前更包括形成一半導體層G2於該第一犧牲層G10上。 In some embodiments, before forming the stacked structure 310, a semiconductor layer G2 is further formed on the first sacrificial layer G10.
在一些實施例中,基板102可由二氧化矽所形成。絕緣層104可由二氧化矽所形成。第二犧牲層306及第一犧牲層 G10可由氮化矽(SiN)所形成。 In some embodiments, the substrate 102 can be formed of hafnium oxide. The insulating layer 104 may be formed of hafnium oxide. Second sacrificial layer 306 and first sacrificial layer G10 may be formed of tantalum nitride (SiN).
在一些實施例中,半導體層G2可以是一重摻雜之多晶矽層,且具有實質大於1020/cm3的一摻雜濃度。 In some embodiments, the semiconductor layer G2 can be a heavily doped polysilicon layer and have a doping concentration substantially greater than 10 20 /cm 3 .
在一些實施例中,絕緣層104具有最接近基板102的一底部絕緣層104a,且底部絕緣層104a與其他絕緣層104之任一者之間具有實質介於1至3之間的一厚度比值。 In some embodiments, the insulating layer 104 has a bottom insulating layer 104a closest to the substrate 102, and the bottom insulating layer 104a and any of the other insulating layers 104 have a thickness ratio substantially between 1 and 3. .
請參照第3B圖,形成複數個串列開口300,穿過疊層結構310將一部份第二犧牲層306暴露於外。 Referring to FIG. 3B, a plurality of tandem openings 300 are formed through which a portion of the second sacrificial layer 306 is exposed.
在一些實施例中,複數個串列開口300係穿過疊層結構310將一部份半導體層G2暴露於外。 In some embodiments, the plurality of tandem openings 300 expose a portion of the semiconductor layer G2 through the laminate structure 310.
在一些實施例中,串列開口300可藉由蝕刻法所形成,例如是乾蝕刻法。 In some embodiments, the tandem opening 300 can be formed by an etching process, such as a dry etching process.
請參照第3C圖,形成一氧化物-氮化物-氧化物(Oxide-Nitride-Oxide,ONO)結構層320共形毯覆於疊層結構310上以及串列開口300之中。 Referring to FIG. 3C, an Oxide-Nitride-Oxide (ONO) structure layer 320 is formed on the laminate structure 310 and in the tandem opening 300.
在一些實施例中,氧化物-氮化物-氧化物結構層320可藉由一沉積製程(deposition process)所形成。 In some embodiments, the oxide-nitride-oxide structure layer 320 can be formed by a deposition process.
請參照第3D圖,形成一多晶矽覆蓋層340a於氧化物-氮化物-氧化物結構層320上。多晶矽覆蓋層340a可以由未摻雜的多晶矽材料所形成。多晶矽覆蓋層340a可藉由一沉積製程所形成。 Referring to FIG. 3D, a polysilicon cap layer 340a is formed on the oxide-nitride-oxide structure layer 320. The polysilicon cap layer 340a may be formed of an undoped polysilicon material. The polysilicon cap layer 340a can be formed by a deposition process.
請參照第3E圖,移除高於串列開口300的一部份氧化物-氮化物-氧化物結構層320和一部份多晶矽覆蓋層340a。於每一串列開口300中形成一通孔(via)330,將一部分的第一犧牲 層G10暴露於外。通孔330係延伸穿過第一犧牲層G10,並將一部份基板102暴露於外。通孔330可藉由蝕刻法所形成,例如是乾蝕刻法。 Referring to FIG. 3E, a portion of the oxide-nitride-oxide structure layer 320 and a portion of the polysilicon cap layer 340a are removed above the tandem opening 300. Forming a via 330 in each of the series of openings 300 to place a portion of the first sacrifice Layer G10 is exposed to the outside. The via 330 extends through the first sacrificial layer G10 and exposes a portion of the substrate 102 to the outside. The via 330 can be formed by an etching method such as dry etching.
在一些實施例中,通孔330更將一部分的半導體層G2暴露於外。 In some embodiments, the via 330 further exposes a portion of the semiconductor layer G2.
請參照第3F圖,於每一串列開口300和通孔330之中形成一多晶矽層340b,使多晶矽層340b與多晶矽覆蓋層340a和第一犧性層G10接觸。多晶矽層340b部分地延伸進入基板102之中。 Referring to FIG. 3F, a polysilicon layer 340b is formed in each of the series of openings 300 and vias 330 to bring the polysilicon layer 340b into contact with the polysilicon layer 340a and the first sacrificial layer G10. The polysilicon layer 340b extends partially into the substrate 102.
在一些實施例中,多晶矽層340b可以由未摻雜的多晶矽材料所形成。多晶矽覆蓋層340a及多晶矽層340b可以由相同的材料所形成。多晶矽層340b可藉由一沉積製程所形成。 In some embodiments, the polysilicon layer 340b can be formed from an undoped polysilicon material. The polysilicon cap layer 340a and the polysilicon layer 340b may be formed of the same material. The polysilicon layer 340b can be formed by a deposition process.
請參照第3G圖,沉積一介電材質180於多晶矽層340b上。介電材質180係由氧化物所形成,例如是二氧化矽。 Referring to FIG. 3G, a dielectric material 180 is deposited on the polysilicon layer 340b. The dielectric material 180 is formed of an oxide such as cerium oxide.
請參照第3H圖,移除高於串列開口300的一部份多晶矽層340b及介電材質180。藉此,於串列開口300的側壁上形成記憶層120以及由剩餘的多晶矽覆蓋層340a與多晶矽層340b共同形成的通道層140。 Referring to FIG. 3H, a portion of the polysilicon layer 340b and the dielectric material 180 above the tandem opening 300 are removed. Thereby, the memory layer 120 and the channel layer 140 formed by the remaining polysilicon cap layer 340a and the polysilicon layer 340b are formed on the sidewall of the tandem opening 300.
請參照第3I圖,形成複數個回蝕開口350,穿過疊層結構310、和第一犧牲層G10。回蝕開口350的深度可大於串列開口300與通孔330所形成的深度。 Referring to FIG. 3I, a plurality of etch back openings 350 are formed through the stacked structure 310 and the first sacrificial layer G10. The depth of the etch back opening 350 may be greater than the depth formed by the tandem opening 300 and the via 330.
請參照第3J圖,進行一回蝕(pull back)製程,以經由回蝕開口350移除第一犧牲層G10及第二犧牲層306。回蝕製程可以是一等向蝕刻(isotropic etching)(例如是溼蝕刻法),且可以 是一高選擇性蝕刻,例如是選擇性蝕刻氮化矽而不蝕刻二氧化矽及多晶矽。 Referring to FIG. 3J, a pull back process is performed to remove the first sacrificial layer G10 and the second sacrificial layer 306 via the etch back opening 350. The etch back process can be an isotropic etching (for example, a wet etching method), and can It is a highly selective etch, such as selective etching of tantalum nitride without etching ruthenium dioxide and polysilicon.
在此步驟中,由於第二犧牲層306及第一犧牲層G10皆被移除,需要藉由穿過第一犧牲層G10至基板102中的通道層140來支撐並固定整個結構,以避免疊層結構310在回蝕製程之中被抬升(lift off)或位移,而不需使用另外的支撐結構來固定疊層結構310。 In this step, since both the second sacrificial layer 306 and the first sacrificial layer G10 are removed, it is necessary to support and fix the entire structure by passing through the first sacrificial layer G10 to the channel layer 140 in the substrate 102 to avoid stacking. The layer structure 310 is lifted off or displaced during the etch back process without the need to use additional support structures to secure the laminate structure 310.
請參照第3K圖,在被移除的第二犧牲層306原來的位置填充一導電材料370,藉以於絕緣層104之間形成導電層106,使絕緣層104與導電層106係形成疊層結構110;並且於疊層結構110與基板102之間形成一金屬層G1。導電層106鄰接記憶層120,且金屬層G1與通道層140電性接觸。導電材料370較佳包含金屬,例如是鎢(W)或氮化鈦(TiN)。在本實施例中,導電層106及金屬層G1係同時形成。 Referring to FIG. 3K, a conductive material 370 is filled in the original position of the removed second sacrificial layer 306, thereby forming a conductive layer 106 between the insulating layers 104, so that the insulating layer 104 and the conductive layer 106 form a stacked structure. And forming a metal layer G1 between the laminated structure 110 and the substrate 102. The conductive layer 106 is adjacent to the memory layer 120, and the metal layer G1 is in electrical contact with the channel layer 140. Conductive material 370 preferably comprises a metal such as tungsten (W) or titanium nitride (TiN). In the present embodiment, the conductive layer 106 and the metal layer G1 are simultaneously formed.
請參照第3L圖,可藉由一蝕刻法(例如是一等向蝕刻法)移除高於串列開口300以及位於回蝕開口350中的導電材料370。 Referring to FIG. 3L, the conductive material 370 above the tandem opening 300 and in the etch back opening 350 can be removed by an etching process such as an isotropic etching process.
請參照第3M圖,以介電材質180填充回蝕開口350,且介電材質180覆蓋疊層結構110。 Referring to FIG. 3M, the etch back opening 350 is filled with a dielectric material 180, and the dielectric material 180 covers the stacked structure 110.
第4圖繪示根據本揭露之一實施例之記憶體元件的等效電路圖。 FIG. 4 is an equivalent circuit diagram of a memory element according to an embodiment of the present disclosure.
請參照第4圖,記憶體元件10可包括區塊100A、100B及100C。在區塊100A、100B及100C中,接地層GND上具有複數條接地選擇線GSL1及GSL2,接地選擇線GSL1及GSL2 上具有複數條字元線WL,字元線WL之上具有複數條串列選擇線SSL。串列選擇線SSL1、SSL2及SSL3分別對應於區塊100A、100B及100C。串列選擇線SSL1、SSL2與SSL3分別連接於複數條位元線BL1...BLN。串列選擇線SSL1、SSL2與SSL3分別藉由複數條記憶胞串列100電性連接於字元線WL及接地層GND。記憶胞串列100與字元線WL的交叉點係形成複數個記憶胞M。每一記憶胞串列100與接地選擇線GSL1及GSL2的交叉點係形成接地選擇線電晶體T。接地選擇線電晶體T係被連續連接,且具有捕捉層(trapping layer)。接地選擇線電晶體T與記憶胞M可具有相同的物理性質。 Referring to FIG. 4, the memory component 10 can include blocks 100A, 100B, and 100C. In blocks 100A, 100B, and 100C, the ground layer GND has a plurality of ground selection lines GSL1 and GSL2, and the ground selection lines GSL1 and GSL2 have a plurality of word lines WL, and the word lines WL have a plurality of strings. Select the line SSL. The tandem selection lines SSL1, SSL2, and SSL3 correspond to the blocks 100A, 100B, and 100C, respectively. Serial select lines SSL1, SSL2 and SSL3 are respectively connected to the plurality of bit line bar BL 1 ... BL N. The serial selection lines SSL1, SSL2, and SSL3 are electrically connected to the word line WL and the ground layer GND by a plurality of memory cell strings 100, respectively. The intersection of the memory cell string 100 and the word line WL forms a plurality of memory cells M. The intersection of each memory cell string 100 with the ground select lines GSL1 and GSL2 forms a ground select line transistor T. The ground selection line transistor T is continuously connected and has a trapping layer. The ground selection line transistor T and the memory cell M may have the same physical properties.
根據上述實施例,本發明提供一種記憶體元件及其製作方法。記憶體元件至少包括一基板、一接地層、一疊層結構、複數條記憶胞串列。接地層位於基板上,其中接地層包括一金屬層。疊層結構位於接地層上,且疊層結構包括交替堆疊的複數個絕緣層和複數個導電層。複數條記憶胞串列穿過疊層結構而與金屬層電性接觸。 According to the above embodiment, the present invention provides a memory element and a method of fabricating the same. The memory component includes at least a substrate, a ground layer, a stacked structure, and a plurality of memory cells. The ground layer is on the substrate, wherein the ground layer comprises a metal layer. The stacked structure is on the ground layer, and the stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked. A plurality of memory cells are serially passed through the laminated structure to be in electrical contact with the metal layer.
由於記憶胞串列穿過疊層結構而與金屬層電性接觸,能夠將記憶胞串列中所有記憶胞的電流直接傳送於下方的金屬層。並且,由於金屬層具有低電阻,能夠避免產生電阻電壓降效應,故能夠減少記憶區塊之間之金屬接觸結構的設置,使得記憶胞串列的佈線空間能夠增加,進而增加SGVC 3D NAND記憶體元件的儲存空間。 Since the memory cell string is electrically connected to the metal layer through the stacked structure, the current of all the memory cells in the memory cell string can be directly transmitted to the underlying metal layer. Moreover, since the metal layer has low resistance, the resistance voltage drop effect can be avoided, so that the arrangement of the metal contact structure between the memory blocks can be reduced, so that the wiring space of the memory cell series can be increased, thereby increasing the SGVC 3D NAND memory. The storage space of the components.
選擇性地,接地層可為一多層結構。接地層可更包括一半導體層,半導體層位於金屬層之上。半導體層可以是一重 摻雜之多晶矽結構。由於接地層具有金屬層,金屬層與通道層的接觸區域可能會產生蕭基障壁,恐對於接觸電阻之穩定性有不良的影響。因此,藉由將接地層設計為一多層結構,設置一半導體層於金屬層之上,半導體層能夠幫助記憶胞之電流集中於金屬層中,改善接觸電阻之穩定性。 Alternatively, the ground layer can be a multi-layer structure. The ground layer may further include a semiconductor layer on the semiconductor layer. The semiconductor layer can be a heavy Doped polycrystalline germanium structure. Since the ground layer has a metal layer, the contact area between the metal layer and the channel layer may generate a Schottky barrier, which may adversely affect the stability of the contact resistance. Therefore, by designing the ground layer as a multilayer structure, a semiconductor layer is disposed on the metal layer, and the semiconductor layer can help the current of the memory cell to concentrate in the metal layer, thereby improving the stability of the contact resistance.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
10‧‧‧記憶體元件 10‧‧‧ memory components
100‧‧‧記憶胞串列 100‧‧‧Memory cell series
102‧‧‧基板 102‧‧‧Substrate
104‧‧‧絕緣層 104‧‧‧Insulation
104a‧‧‧底部絕緣層 104a‧‧‧Bottom insulation
106‧‧‧導電層 106‧‧‧ Conductive layer
110‧‧‧疊層結構 110‧‧‧Laminated structure
120‧‧‧記憶層 120‧‧‧ memory layer
140‧‧‧通道層 140‧‧‧channel layer
180‧‧‧介電材質 180‧‧‧ dielectric material
G1‧‧‧金屬層 G1‧‧‧ metal layer
G2‧‧‧半導體層 G2‧‧‧ semiconductor layer
GND‧‧‧接地層 GND‧‧‧ Ground plane
HG2、H106‧‧‧厚度 H G2 , H 106 ‧‧‧ thickness
M‧‧‧記憶胞 M‧‧‧ memory cell
T、T1、T2‧‧‧接地選擇線電晶體 T, T1, T2‧‧‧ ground selection line transistor
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KR101056113B1 (en) * | 2010-07-02 | 2011-08-10 | 서울대학교산학협력단 | 3d vertical type memory cell string with shield electrode encompassed by isolating dielectric stacks, memory array using the same and fabrication method thereof |
US20120205722A1 (en) * | 2011-02-16 | 2012-08-16 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices and methods of fabricating the same |
US20140175532A1 (en) * | 2012-12-26 | 2014-06-26 | Macronix International Co., Ltd. | Method for manufacturing semiconductor device |
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2015
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US20100177566A1 (en) * | 2009-01-14 | 2010-07-15 | Kim Won-Joo | Non-volatile memory device having stacked structure, and memory card and electronic system including the same |
KR101056113B1 (en) * | 2010-07-02 | 2011-08-10 | 서울대학교산학협력단 | 3d vertical type memory cell string with shield electrode encompassed by isolating dielectric stacks, memory array using the same and fabrication method thereof |
US20120205722A1 (en) * | 2011-02-16 | 2012-08-16 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices and methods of fabricating the same |
US20140175532A1 (en) * | 2012-12-26 | 2014-06-26 | Macronix International Co., Ltd. | Method for manufacturing semiconductor device |
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