TWI727960B - Memory device having programmable impedance elements with a common conductor formed below bit lines - Google Patents

Abstract

An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.

Description

Memory device with programmable impedance element with common conductor formed under bit line

The present disclosure is generally related to integrated circuits (ICs) including programmable impedance components, and more particularly to ICs having such components connected to a common conductor (for example, a board structure) formed under the bit line related.

Traditional variable resistance memory (RRAM) devices, such as CBRAM type devices, may include two terminal storage elements that can be programmed between different resistance values. Some conventional CBRAM devices may have memory devices that have a terminal (ie, anode or cathode) that is usually connected to each other by means of a conductive layer, sometimes called a board. Conventional CBRAM devices typically form memory elements near the end of the manufacturing process. In particular, such an element is formed after formation including formation of a metallization layer forming a bit line. Therefore, conventional CBRAM type devices typically include boards formed on bit lines.

The integrated circuit device may include an access transistor formed in the substrate. A plurality of two-terminal programmable impedance elements can be formed on the substrate. One or more conductive plate structures can be formed with a common conductive connection to the programmable impedance element. The plate structure may extend in at least a first direction. A plurality of storage contacts can extend vertically from each access transistor to one of the programmable impedance elements. Bit lines can be formed on the board structure. The bit line may extend in a second direction different from the first (word line) direction. The bit line contact can extend vertically from each access transistor through the opening in the plate structure to one of the bit lines.

The IC device may include an access transistor formed in the substrate and connected to the word line. The word line may extend in the first direction. Two-terminal programmable impedance elements can be formed on the substrate and arranged in groups. The conductive plate structure can be formed with a common conductive connection connected to different sets of programmable impedance elements. Each conductive plate structure may extend in the first direction. The storage contact can extend vertically from each access transistor to one of the programmable impedance elements. A bit line extending in the second direction may be formed over the plate structure. The bit line contact can extend vertically from each access transistor through the opening in the plate structure to the bit line.

The IC device may include a bit line extending in the first direction. One or more conductive plate structures can be formed between the bit line of the IC device and the substrate. The plate structure may extend in the second direction. The two-terminal programmable impedance element can have a common conductive connection to the board structure. The access transistor may be formed in the substrate and has a control terminal connected to the word line extending in the second direction. The bit line contact can extend vertically from one of the bit lines through the opening in the plate structure to the access transistor. The storage contact can extend vertically from the corresponding programmable impedance element to the access transistor.

Embodiments may include memory devices having memory cells, each of which includes an access transistor and one or more programmable impedance storage elements. The storage element may generally be connected to a plate-shaped conductor formed under the bit line. The bit line can be connected to the memory cell by the bit line contact extending through the opening in the plate-shaped conductor. The access transistor may have a gate normally connected to the word line, and the word line may extend in the first direction. The plate-shaped conductor may also extend in the first direction.

In this way, the programmable impedance element can be incorporated into the integrated circuit device at a certain level below the metallization layer (including below the first metallization layer).

In the following various embodiments, similar items are referred to by the same reference symbols but with the initial numbers corresponding to the figures in the figures.

Fig. 1 is a side cross-sectional view of an integrated circuit device 100 according to an embodiment. The IC device 100 may include an access device (one is shown as 102), a programmable impedance storage element 104, a conductive plate structure 106, a bit line (one is shown as 108), and a board tap structure 110. The storage contact 112 may extend vertically from the substrate 114 to the storage element 104. The bit line contact 116 may extend vertically from the substrate 114 to the bit line 108.

The access device 102 can be any suitable circuit element that can be controlled to allow current to flow through the corresponding storage element 104. To cite some non-limiting examples, the access device 102 may include a diode type device, a thyristor type device, or a transistor. In the particular embodiment shown, the access device is an access transistor 102. The access transistor 102 can be any suitable transistor capable of allowing the current path to react to the signal at the control terminal. In the particular embodiment shown, the access transistor 102 may be an insulated gate field effect transistor, referred to herein as a metal oxide semiconductor (MOS) transistor, but is not limited to any special gate insulator. The access transistor 102 may have a control terminal 118 (ie, a gate) connected to the word line in a conductive manner. In some embodiments, the word line may be a continuous structure including access transistor control terminals as a whole. The word line may be an elongated structure extending substantially in one direction (for example, extending into and out of the page in the field of view in Figure 1). The access transistor may include a first current terminal (for example, source/drain) 120-0 and a second current terminal (for example, drain/source) 120-1. By controlling the operation of the terminal 118, the current can be Flow through the current terminal. In the illustrated embodiment, adjacent access transistors can share one current terminal 120-0. However, other embodiments may include an access transistor that does not share the source or drain with another access transistor.

The storage contact 112 can provide a conductive connection between the second current terminal 120-1 and the corresponding storage element 104. The storage contact may include a single conductive structure (eg, contact), or may include multiple conductive structures stacked on top of each other (eg, contacts with vias or metalized platform pads, etc.). The storage contact 112 may be formed in openings created in one or more insulating layers.

The storage element 104 can be a two-terminal element that can be programmed between two or more impedance states to store data values. In some embodiments, the storage element 104 can be programmed by the application of an electric field. In the illustrated embodiment, the storage element 104 may include a memory layer 122 that can be programmed between different impedance states by a redox reaction induced by the application of an electric field. In a very special embodiment, the storage element may be a CBRAM type memory element. The memory layer 122 may include a plurality of sub-layers (for example, formed by a stack of different layers). In addition, the memory layer 122 (or any of its sublayers) may be a continuous layer shared by multiple storage devices, or may be a layer (or sublayer) different from each storage device. Furthermore, although FIG. 1 shows the memory layer 122 as a flat, continuous layer, in alternative embodiments, all or part of the memory layer (or sublayer) may be located in the opening shared with the storage contact 112. That is, all or part of the storage element 104 may be formed in the contact opening or similar type of opening.

The plate structure 106 may extend beyond and conductively connect to, or form part of, some of the storage elements 104. In some embodiments, the plate structure 106 acts as, or is conductively connected to one terminal of each storage element 104. It is understood that the IC device may include a plurality of plate structures 106 corresponding to different sets of storage elements, and each plate structure can be separately driven between two or more plate voltages. Therefore, in the access operation of the IC device, one board can be driven to one voltage, and the other board can be driven (or maintained) with a different voltage. The plate structure 106 may extend in the same direction as the word line (for example, extend into and out of the page in the field of view in Figure 1). The plate structure 106 may be composed of a single conductive layer, or may include some conductive sublayers.

Still referring to FIG. 1, the IC device may include a plate opening 124, which may be conceptualized as extending through the plate structure 106 or existing between adjacent plate structures 106.

The board tap structure 110 can bias the board structure 106 to any of a number of different voltages. The board tap structure 110 can take any suitable form, which provides a conductive connection between the voltage drive circuit and the board structure 106. Some specific but non-limiting examples are shown in Figure 1. In some embodiments, the board tap conductor 110 may only include the first tap conductor 110-0 that is in direct contact with the board structure 106. The first tap conductor 110-0 may be patterned from one or more metallization layers, for example, to form other interconnected layers in the IC device 100. In a particular embodiment, the first tap conductor 110-0 can be formed from the same metallization layer that forms the bit line in the IC device.

In other embodiments, the board tap structure 110 may include multiple tap conductors. For example, in some embodiments, the board tap structure 110 may include a first tap conductor 110-0 and a second tap conductor 110-1. In such a configuration, the first tap conductor 110-0 may be a contact structure (eg, via) that extends from the plate structure 106 to the second tap conductor 110-1, which may be formed from one or more metallizations Layer formation, including those used to form the bit line 108. In still other embodiments, the board tap structure 110 may extend above the vertical level of the bit line 108, and includes any of a plurality of tap conductors (for example, any of 110-0/1/2/3). A) Or a large conductive structure.

In this way, the board tap structure can be below the bit line, the same as the bit line, or above the vertical level of the bit line.

The bit line contact 116 may provide a conductive connection between the first current terminal 120-0 and the bit line 108. As in the storage contact example, the bit line contact 116 may include a single conductive structure or multiple conductive structures stacked on top of each other. The bit line contact 116 extends through the board opening 124. It is understood that one bit line contact can be shared by multiple adjacent access transistors 102.

The bit line 108 can be patterned from one or more metallization layers formed on the plate structure 106. In some embodiments, the bit line 108 may be an elongated structure extending in a different direction from the word line. In a particular embodiment, the bit line 108 may be substantially perpendicular to the word line (for example, horizontally in the field of view in Figure 1). The bit line 108 may be located at a higher vertical level than the board structure 106. Although the bit line 108 is shown at a particularly vertical level in Figure 1, it is understood that the bit line 108 can be formed at a higher vertical level (ie, above the plate structure 106). In some embodiments, the bit line 108 may be formed from a "metal 1" (M1) layer (the first metallization layer formed during the manufacturing process). However, in other embodiments, the bit lines can be formed from any other higher vertical horizontal conduction layer. In another way, as long as the bit line 108 is above the plate structure 106, the plate structure 106 can be under any other conductive/metallized layer.

In this way, the IC device may include a plate structure extending in the word line direction and located between the bit line and the substrate, with the bit line contact extending from the bit line through the plate opening to the substrate.

2A to 2C are a series of top plan views of an IC device 200 according to another embodiment. Figure 2A shows the formation of word lines on the surface of the substrate (one is shown as 226). The word line 226 may integrally include, or be conductively connected to the control terminals of a plurality of access transistors. One possible location of the access transistor is shown by 202. The word line 226 may be an elongated structure extending in the first direction, as shown by arrow 230. Storage contacts (one shown as 212) can be formed adjacent to the word line, and can be conceptualized as a storage contact group 232-0/1/2 arranged to extend in the first direction 230. The storage contact group 232-0/1/2 can be conceptualized as different rows of storage contacts.

Optionally, the IC device 200 may include other additional word lines 228 as dummy word lines or isolated word lines. The dummy word line may not be biased and may be located on the isolation structure formed in the substrate. The isolated word line can be biased to electrically isolate adjacent storage contacts from each other. Other embodiments may not include the additional word line 228, and may optionally have a substrate isolation structure.

FIG. 2B shows the formation of the plate structure 206 on the word line 226. It is understood that a memory layer can be formed under the board structure 206 first to generate a storage element at the location of the storage contact 212. The plate structure 206 may have plate openings formed therein (one is shown as 224). In the special embodiment of FIG. 2B, the plate opening 224 may be formed at a future position where the bit line contacts. Although the opening 224 has a circular shape, embodiments may include any suitable shape. The plate structure 206 may extend in the first direction 230 on the storage contact group 232-0/1/2. In addition, in some embodiments, the plate structure 206 may also extend in a second direction different from the first direction (ie, in a direction perpendicular to the direction 230). The IC device 200 may include a plurality of such board structures that can be individually biased.

Figure 2C shows the formation of bit line contacts (one is shown as 216), the bit line contacts extending through the plate opening 224 to the substrate (and therefore to the access transistor). FIG. 2C also shows the formation of the bit line 208 on the plate structure 206 and in contact with the bit line contact 216. The bit line 208 may have an elongated shape and extend in a second direction different from the first direction 230 as shown by the arrow 234. In the illustrated embodiment, the first direction 230 may be perpendicular to the second direction 234. Although FIG. 2C shows the bit line 208 covering only one bit line contact 216 in the word line direction 230, alternative embodiments may include covering more than one bit line contact in the word line direction. Line (for example, bit line is wider than one line).

Although the embodiments of FIGS. 2A to 2C show a plate structure that can be continuous on the storage contact group, alternative embodiments may include a narrower plate structure that extends over different storage contact groups. This alternative embodiment is shown in Figures 3A and 3B.

Figure 3A is a top plan view of the IC device 300 according to one embodiment, and shows the formation of the plate structure 306-0/1 over the word lines and storage contacts as shown in Figure 2A. Each plate structure 306-0/1 can be formed on two sets (eg, rows) of storage contacts. In particular, the plate structure 306-0 may be formed on the storage contact column 332-0 (and another column not shown), and the plate structure 306-1 may be formed on the storage contact column 332-1/2. The area between adjacent plate structures 306-0/1 may be plate openings 324-0/1. The plate structure 306-0/1 can be biased separately. Bit lines can be formed on this structure, as shown in Figure 2C, but only as an example. FIG. 3A shows the width of the plate opening 335 in the bit line direction 334. According to embodiments, the narrowest width of the plate opening may not be more than twice the width of the bit line contact in the same direction.

Figure 3B is a top plan view of an IC device 300' according to another embodiment, and shows the formation of the plate structure 306-0'/1'/2' above the word line and the storage as in the example in Figure 3A contact. However, unlike Figure 3A, the plate structure 306-0'/1'/2' can be formed on a single set (e.g., column) of storage contacts. The bit lines can be formed on this structure as shown in Figure 2C, but it is only an example.

It is understood that although FIGS. 2A to 3B show word lines and bit lines having a substantially straight shape, alternative embodiments may include such structures having different shapes, including zigzag (for example, , Serpentine) and provide a contact platform so that the word line can be driven to a wide area of a special voltage.

4A to 4C are a series of top plan views of an IC device 400 according to another embodiment. The embodiments of Figs. 4A to 4C show items like those of Figs. 2A to 2C, and similar items are referred to by the same reference signs but with "4" instead of the leading numerals of "2" .

The difference between FIG. 4A and FIG. 2A is that the word line 426 can have a different configuration. In the example shown, word lines 426 may be interleaved with additional word lines 428. However, it is understood that, as mentioned in the description of FIG. 2A, any additional word lines can be dummy or isolated word lines. Additionally or alternatively, there may be an isolation structure at the location of the additional word line.

Fig. 4B and Fig. 4C respectively show the structures like those in Fig. 2B and Fig. 2C.

Figures 5A and 5B show the top of the board structure (506-0 to -2 and 506-0' to -2') above the word lines and storage contacts like those shown in Figure 4A Floor plan. Although each plate structure is formed on a set of storage contacts (532-0 to -2), each plate structure 506-0 to -2 can be formed on two word lines, and each plate structure 506-0 'To-2' can be formed on one word line. Although FIG. 5B shows a board structure that overlaps only one word line, in other embodiments, the board structure may not overlap the word line. But just as an example, when viewed from above, the board structure can be formed on a set of storage contacts and located between the word lines.

Although FIGS. 2A to 5B have shown configurations that may include additional word lines, alternative embodiments may not include additional word lines and/or isolation structures.

Although FIGS. 2A to 5B show a special embodiment having a plate structure connected in the word line direction, it is understood that the embodiment may include a plurality of The plate structure formed by the extension plate segment. Figure 6 shows an example of such an implementation.

FIG. 6 is a top plan view of the IC device 600 having a board structure 606 having a plurality of board segments 606-0 to -2 extending in the column direction 630. Each plate segment (606-0 to -2) may extend over one or more sets of storage contact groups and/or word lines or equivalents as described herein for the plate structure. In addition, the board segment may have one or more board tap structures connected to it to drive the board segment to between two or more different board voltages. The special embodiment of Figure 6 shows each board segment (606-0 to -2) with one board tap structure 610-0 to -2. The board tap structure 610-0 to -2 is positioned on each board. The central position of the fragment (606-0 to -2). However, alternative embodiments may include a board tap structure at another location of the board structure, and/or as previously mentioned, there may be multiple board tap structures per board segment.

In some embodiments, the board tap structure may contact the board segment/board structure at the top surface, for example, as shown in Figure 1. However, in an alternative embodiment, the board tap structure may contact the board segment/board structure from the bottom surface. One such embodiment is shown in Figure 7.

Figure 7 is a side cross-sectional view of an IC device 700 with storage contacts 712, which can extend upward from the substrate (or other lower structure) to a storage element 704 including one or more memory layers 722. The memory layer 722 can be directly or indirectly connected to the board structure 706. The board tap structure 710 may extend upward from the substrate (or other lower structure) and have a conductive connection to the board structure 706. As described herein, the plate structure 706 can be driven between two or more different plate voltages via the plate tap structure 710, or in an equivalent manner.

According to some embodiments, the IC device may include a plate structure formed under the bit line and driven to different plate voltages. In a special implementation, the board structure can be decoded based on address data and/or mode data. The address data can identify the memory cell to be accessed during the operation. The pattern data can identify the operation being performed by the IC device when accessing the memory cell. Therefore, the mode data can identify operations including, but not limited to, reading or impedance setting operations. Impedance setting operations may include those that set memory components to a special impedance state, including but not limited to "program" and "elimination", including individual and/or group elimination operations.

FIG. 8 is a diagram showing an IC device 800 having a decoder board structure according to an embodiment. The IC device 800 may include some plate structures 806-0 to -n, each of which may include storage elements (two shown as 812) or equivalents formed at storage contact locations as described herein.

The IC device 800 may further include a board decoder circuit 834 and some board driver circuits 836-0 to -n. The board decoder circuit 834 can receive address and/or mode signals (ADD/MODE), and optionally, timing signals (TIMING). From such signals, the board decoder circuit 834 can generate board drive signals (PDRV0 to PDRVn), and the board drive signals can determine the voltage to which the board structure can be driven. Each board driver circuit 836-0 to -n can receive the corresponding board driver signal (PDRV0 to PDRVn), and drive its corresponding board structure (806-0 to -n) to the board voltage VPL0 to VPLn. In the particular embodiment shown, each board driver circuit (836-0 to -n) can drive its board to the select voltage (VSEL) or the deselect voltage (VDSEL). However, alternative embodiments may include more than two possible plate voltages. But just as an example, the implementation may include different selection and/or deselection voltages based on the special operation performed (for example, reading selection/deselection is different from program selection/deselection).

9A and 9B are diagrams showing an IC device 900 according to a particular embodiment. The IC device 900 may include a memory cell having an access transistor and a programmable impedance storage element, wherein such a storage element can be conductively connected to a common board structure formed under the bit line.

FIG. 9A shows three cross-sectional views of the IC device 900. As shown in FIG. The view 950 is taken along the direction perpendicular to the word line (for example, the direction of the row) in the memory array of the IC device 900. The view 952 is taken through a set of storage contacts in the memory array of the IC device 900 along a direction parallel to the word line (for example, the direction of the column). The view 954 is taken from a location outside the memory of the IC device 900 (for example, the surroundings, or other circuit parts of the IC device 900). FIG. 9B is a top plan view of the IC device 900. FIG.

Referring to FIG. 9A, the IC device 900 may include access devices (two are shown as 902-0/1) formed on and in the substrate 914. In the embodiment shown, the access device 902-0/1 is a MOS type transistor with a control terminal (gate, one is shown as 918) and a current terminal 920-0/1 (source/drain ). The access device 902-0/1 can be connected to the storage element via the storage contact 912 (two are shown as 904-0/1). The storage element 904-0/1 may include a memory layer 922 disposed between the storage contact and the board structure 906-1. The memory layer 922 may be formed of multiple sub-layers. In the illustrated embodiment, additional word lines 928 (or dummy word lines) may be formed between adjacent word lines 926-1/2. Additionally or alternatively, column isolation 940 may be formed between adjacent word lines 926-1/2 in the substrate 914.

In the embodiment of FIG. 9A, each plate structure 906-0/1/2 can be formed on two word lines 926-1/2 (and dummy word lines 928) and can be in the word line direction. Extend (ie, extend into and out of the page in the field of view of 950). The plate opening 924-0/1 can separate adjacent plate structures from one another in the lateral direction (direction parallel to the surface of the substrate). In Figure 9A, the structure 906-1 can be biased between two or more plate voltages by means of the plate tap structure 910. In the particular embodiment shown, the board tap structure 910 may include a first board contact structure 910-0 and a second board contact structure 910-1. As shown in the view of FIG. 9B, the second plate contact structure 910-1 may be an elongated structure extending in the word line direction 930. As in the bit line contact example, in an alternative embodiment, the board tap structure is formed by a contact structure. In the embodiment of FIG. 9A, the plate structure 906-0/1/2 may be covered by the top plate insulator 909 on the top surface, and the plate tap structure 910 may extend through the top plate insulator 909 to contact the plate structure 906-0/ 1/2. In addition, FIG. 9A also shows the insulating sidewall 911 on the side surface of the board structure 906-0/1/2 and the memory layer 922.

In the embodiment of FIG. 9A, the bit line (BL) contact may be formed by the first and second contact structures stacked on top of each other. Therefore, the first BL contact (916-00/01) may include a first BL structure 916-00 extending through the opening 924-0 in the plate structure 906-0/1, and a first bit line contact structure 916 formed -00 second BL contact structure 916-01 on top. Similarly, the second BL contact (916-10/11) may include a first BL structure 916-10 extending through the opening 924-1 in the plate structure 906-1/2, and a first bit line contact structure formed The second BL contact structure 916-11 on top of 916-10. In some embodiments, the second BL contact structure 916-01/11 may be a metalized "platform pad" formed from a metalized pattern. However, in alternative embodiments, the bit line contact may be formed by a single contact structure, or more than two contact structures.

In the embodiment of FIG. 9A, the bit line 908 may be formed on and in contact with the BL contact 916-00/01-10/11. That is, the bit line 908 may be in contact with two rows of bit line contact (where such rows extend in the bit line direction perpendicular to the word line). However, in other embodiments, there is one bit line that can be used for each row of bit line contacts. It is mentioned that the bit line 908 is not shown in FIG. 9B, and is resolved to extend in a direction perpendicular to the word line direction 930 on the various layers shown.

In a particular embodiment, the first bit line contact structure 916-00/10 and the first plate contact structure 910-0 may have the same physical structure (for example, formed by the same process step), and the second bit The element wire contact structure 916-10/11 and the second board contact structure 910-1 may have the same physical structure.

A view 952 taken from parallel to the word line (and passing through a set of storage contacts 912) shows the bit line isolation structure 938 in the substrate 914, which can extend in the bit line direction and defines the active area (in the Shown as 956-0/1 in Figure 9B).

The view 954 taken from the area outside the array shows the peripheral transistor 948 formed in the substrate 914. In some embodiments, the peripheral transistor 948 may have the same structure as the access transistor 902-0/1. However, in an alternative embodiment, the peripheral transistor 948 may be formed in a different manufacturing step than the access transistor 902-0/1. In Figure 9A, the peripheral transistor 948 can be biased by the gate bias structure 958-0/1. In the particular embodiment shown, the gate bias structure 958-0/1 may include a first gate contact structure 958-0 and a second gate contact structure 958-1. In a particular embodiment, the first and second gate contact structures 958-0/958-1 may have the same as the first and second bit line contact structures 916-00/01 and 916-10/11, respectively structure.

FIG. 9A shows various insulating layers used in the IC device 900. As shown in FIG. The first insulating layer 942-0 may be formed on the transistors (902-0/1, 948). In addition, the storage contact 912 may be formed through the first insulating layer 942-0, and the plate structure 906-0/1/2 may be formed on the first insulating layer 942-0. The second insulating layer 942-1 may be formed on the first insulating layer 942-0. In addition, the first bit line contact structure 916-00/10 may extend through the first and second insulating layers 942-0/1 to contact the substrate 914. The first gate bias structure 958-1 may extend through the first and second insulating layers 942-0/1 to contact the gate of the peripheral transistor 948. The first board tap contact structure 910-0 may extend through the second insulating layer 942-1 to contact the board structure 906-1. A third insulating layer 942-2 may be formed on the second insulating layer 942-1. The second bit line contact structure 916-01/11, the second plate contact structure 910-1, and the second gate bias structure 958-1 may extend through the third insulating layer 942-2 to contact the first bit respectively The line contact structure 916-00/10, the first plate contact structure 910-0, and the first gate bias structure 958-0. A fourth insulating layer 942-3 may be formed on the third insulating layer 942-2. The bit line 908 may extend through the fourth insulating layer to contact the second bit line contact structure 916-10/11.

In the illustrated embodiment, the IC device 900 may further include a first intermediate insulating layer 944-0 between the second and third insulating layers 942-1/2. In a particular embodiment, the first intermediate insulating layer 944-0 can be used as an etching stop layer or a hard etching mask to define openings and/or to help prepare or adjust to the first bit line structure 916-00/10, An opening of the one-board tap structure 910-0 and the first gate bias structure 958-0. Similarly, a second intermediate insulating layer 944-1 may be formed between the third and fourth insulating layers 942-2/3. In a particular embodiment, the second intermediate insulating layer 944-1 can be used as an etching stop layer or a hard etching mask to define/prepare/adjust to the opening of the second bit line structure 916-10/11. It is understood that any of the insulating layers 942-0 to -3 and/or 944-0/1 may include multiple sub-layers.

Referring to FIG. 9B, the first board tap contact structure 910-0 is shown to be "misaligned" with respect to the bit line contact and the row of storage contacts. However, alternative embodiments may include board tap contact structures aligned with such rows, or, as mentioned elsewhere herein, may include alignment at the distal end of the board structure and/or contacts, upward from the substrate Extended contact.

In a very special embodiment, the first metallization layer (M1) of the IC process can be used to form the second bit line contact structure 916-01/11, the second plate contact structure 910-1, and the second gate bias The pressed structure 958-1, and the bit line 908 can be formed from the second metallization layer (M2) of the IC process. However, such a configuration should not be construed as restrictive.

10A and 10B are diagrams showing an IC device 1000 according to another special embodiment. The IC device 1000 may have a structure like FIG. 9A and FIG. 9B.

The IC device 1000 is different from FIG. 9A/FIG. 9B in that the storage contact 1012 may have the same structure as the first bit line contact structure 1016-00/10. Therefore, the storage contact 1012 and the first bit line contact structure 1016-00/10 can be formed by the same process.

The IC device 1000 may also be different from FIG. 9A/FIG. 9B in that the board tap structure 1010 may be formed from a single layer (for example, a metallization or other horizontal interconnection layer/pattern). In some embodiments, the same manufacturing steps used to form the second bit line contact structure 1016-01/11 can be used to form the board tap structure 1010.

The IC device 1000 may be further different from FIG. 9A/FIG. 9B in that the storage contact 1012 (and in the embodiment shown, the first bit line contact structure 1016-00/01) may include a modified contact surface (One is shown as 1060). The modified contact surface 1060 may be formed by processing the top of the contact structure and/or depositing one or more other layers on the top of the contact structure. In some embodiments, the modified contact surface 1060 can form part of the storage element 1004-0/1.

The special example of Fig. 10A/Fig. 10B is also different from Fig. 9A/Fig. 9B in that there may be fewer insulating layers. In particular, the first insulating layer 1042-0 may be formed on the transistors (1002-0/1, 1048). In addition, the storage contact 1012 and the first bit line contact structure 1016-00/10 may extend through the first insulating layer 1042-0 to contact the substrate 1014. The first gate bias structure 1058-0 may extend through the first insulating layer 1042-0 to contact the gate of the peripheral transistor 1048. A second insulating layer 1042-1 may be formed on the first insulating layer 1042-0. The second bit line contact structure 1016-01/11 and the second gate bias structure 1058-1 may extend through the second insulating layer 1042-1 to respectively contact the first bit line contact structure 1016-00/10 and The first gate bias structure 1058-0. The board tap structure 1010 may extend through the second insulating layer 1042-1 to the board structure 1006-1. A third insulating layer 1042-2 may be formed on the second insulating layer 1042-1. The bit line 1008 may extend through the third insulating layer to contact the second bit line contact structure 1016-01/11. In the illustrated embodiment, the IC device 1000 may further include an intermediate insulating layer 1044 between the second and third insulating layers 942-1/2, which may, in particular embodiments, serve as an etch stop Layer or hard etch mask to define and/or help prepare or adjust the opening to the second bit line structure 1016-01/11.

Figure 10A shows bit line 1008 in view 1052. It is understood that such a bit line 1008 extends in a direction perpendicular to the word line direction.

In a very special embodiment, the first metallization layer (M1) of the IC process can be used to form the second bit line contact structure 1016-01/11, the board tap structure 1010, and the second gate bias structure 1058 -1, and the bit line 1008 can be formed from the second metallization layer (M2) of the IC process. However, such a configuration should not be construed as restrictive.

11A and 11B are diagrams showing an IC device 1100 according to another special embodiment. The IC device 1100 may have a structure like FIG. 9A and FIG. 9B.

However, the difference between the IC device 1100 and FIG. 9A/B is that the bit line contact 1116 may be a single structure extending directly from the substrate 1114 to the bit line 1108. That is, there is no second bit line contact structure (ie, 916-01/11).

The IC device 1100 may also be different from FIG. 9A/FIG. 9B in that a board tap structure 1110 may be formed at the distal end of the board structure. In the embodiment of FIG. 11A/FIG. 11B, the view 1152 shows the board tap structure 1110 extending downward to contact the board structure 1106-1. The board tap structure 1110 may include a first board contact structure 1110-0 and a second board contact structure 1110-1. In some embodiments, the same process steps as forming the bit line contact 1116 can be used to form the first plate contact structure 1110-0. Additionally or alternatively, the same process steps as forming the bit line 1108 may be used to form the second plate contact structure 1110-1. Similarly, outside of the array (view 1154), the same process steps as forming the bit line contact 1116 can be used to form the first gate bias structure 1158-0 and/or the same process steps as forming the bit line 1108 To form a second gate bias structure 1158-1.

The special example of FIG. 11A/FIG. 11B is also different from that of FIG. 9A/FIG. 9B in that there may be fewer insulating layers. In particular, a storage contact 1112 passing through the first insulating layer 1142-0 may be formed, and a plate structure (1106-0/1/2) may be formed on the first insulating layer 1142-0. A second insulating layer 1142-1 may be formed on the first insulating layer 1142-0. The bit line contact 1116 can extend from the bit line 1108 through the first and second insulating layers 1142-0/1 within the plate opening 1124-0/1 to contact the access transistor 1102-0/1. The first gate bias structure 1158-0 may extend through the first and second insulating layers 1142-1/2 to contact the peripheral transistor 1148. The first plate contact structure 1110-0 may extend through the second insulating layer 1142-1 to contact the plate structure 1106-1. A third insulating layer 1142-2 may be formed on the second insulating layer 1142-1. The bit line 1108, the second plate contact structure 1110-1, and the second gate bias structure 1158-1 extend through the third insulating layer 1142-2 to respectively contact the bit line contact 1116 and the first plate contact structure 1110- 0 and the first gate bias structure 1158-0.

Figure 11A shows bit line 1108 in view 1152. In addition, FIG. 11B also shows a bit line, which extends in a direction perpendicular to the word line direction 1130.

In a very special embodiment, the first metallization layer (M1) of the IC process can be used to form the bit line 1108, the second plate contact structure 1110-1, and the second gate bias structure 1158-1. However, such a configuration should not be construed as restrictive.

FIG. 12A and FIG. 12B are diagrams showing an IC device 1200 according to a further specific embodiment. The IC device 1200 may have a structure like FIG. 9A and FIG. 9B.

The IC device 1200 is different from FIG. 9A/B in that the configuration of the word lines may include word lines 1202-0/1 interleaved with additional word lines 1228. As in the other examples above, additional word lines may not be included, and conversely, column isolation 1240 may isolate memory cells in the bit line direction.

The embodiment of Figure 12A/Figure 12B is also different from Figure 9A/Figure 9B in that the plate structure 1206-0/1/2 can be narrow in the bit line direction and does not extend beyond more than two words. line.

The embodiment shown in FIG. 12A/FIG. 12B differs from that in FIG. 9A/FIG. 9B further in the structure of bit line contact. Although the bit line contact of the IC device 1200 may include the first and second bit line structures 1216-0/1, the second bit line contact structure 1216-1 may be in the form of a contact/via type connection instead of a platform pad (For example, metallization) form. In some embodiments, the storage contact 1212 and the first bit line contact structure 1216-0 can be formed in the same process steps. In addition, the first plate contact structure 1210-0 and the second bit line contact structure 1216-1 can be formed in the same process steps.

In the embodiment of FIG. 12A/FIG. 12B, the modified contact surface 1260 may be provided on top of the storage contact 1212, and may be in any form described for 1060 in FIG. 11A.

It is understood that the board tap structure 1210 may not necessarily be aligned with the second bit line contact structure 1208, and may be offset as in the example of FIG. 9B, or located at the distal end as in the example of FIG. 11A.

Although FIG. 12A does not include a cross-sectional view of a non-array area (for example, surroundings), it is understood that the IC device 1200 may include a non-array area or an equivalent as shown in other embodiments.

In FIG. 12A, a storage contact 1212 passing through the first insulating layer 1142-0 and a first bit line contact structure 1216-0 can be formed, and a plate structure (1206- 0/1/2). A second insulating layer 1242-1 may be formed on the first insulating layer 1242-0. The second bit line contact structure 1216-1 and the first plate contact structure 1210-0 may extend through the second insulating layer 1242-1. A third insulating layer 1242-2 may be formed on the second insulating layer 1242-1. The bit line 1208 and the second plate contact structure 1210-1 respectively extend through the third insulating layer 1242-2 to contact the second bit line contact structure 1216-1 and the first plate contact structure 1210-0.

FIG. 12A also shows an insulating layer 1244-0 that can be formed between the first insulating layer 1242-0 and the second insulating layer 1242-1. A modified contact surface 1260 can be formed in such a layer. In addition, an insulating layer 1244-1 may be formed between the second insulating layer 1242-1 and the third insulating layer 1242-2. In some embodiments, the insulating layer 1244-1 can be used as an etch stop layer or a hard etch mask.

Figure 12A shows bit line 1208 in view 1252. In addition, a bit line is also shown in FIG. 12B, which extends in a direction perpendicular to the word line direction 1230.

In a very special embodiment, the bit line 1208 and the second plate contact structure 1210-1 can be formed by the first metallization layer (M1) of the IC process. However, such a configuration should not be construed as restrictive.

It should be appreciated that the reference to "one (one) embodiment" or "one (an) embodiment" in this specification means that the specific feature, structure, or characteristic described in relation to the embodiment is included in the present invention In at least one embodiment. Therefore, it should be emphasized and understood that the references to "an implementation", "one implementation" or "alternative implementation" in each part of this specification do not necessarily all mean the same的实施方式。 In addition, features, structures, or characteristics can be combined as appropriate in one or more embodiments of the present invention.

It should also be understood that other embodiments of the invention can be implemented without the elements/steps specifically disclosed herein.

Similarly, it should be appreciated that in the foregoing description of the exemplary embodiments of the present invention, in order to simplify the disclosure and help understand one or more various creative aspects, sometimes a single embodiment, drawing or description thereof The various features of the present invention are gathered together. However, this disclosure method is not to be interpreted as reflecting the intention that the scope of the patent application needs more than the features listed in the scope of each patent application. More precisely, the inventive aspect lies in less than all the features of the single aforementioned disclosed embodiment. Therefore, the scope of patent applications after the detailed description is hereby explicitly incorporated into this detailed description, and each scope of patent applications is independent as an individual embodiment of the invention.

100, 200, 300, 300’, 400, 600, 700, 800, 900, 1000, 1100, 1200‧‧‧Integrated Circuit (IC) device 102, 202, 902-0, 902-1‧‧‧Access device 104, 704, 904-0, 904-1, 1004-0, 1004-1‧‧‧Storage components 106, 206, 306-0, 306-1, 306-0', 306-1', 306-2', 606, 706, 806-0...806-n, 906-0, 906-1, 906-2 , 1006-1, 1106-0, 1106-1, 1106-2, 1206-0, 1206-1‧‧‧ Plate structure 108, 208, 908, 1008, 1108, 1208‧‧‧ bit lines 110, 610-0, 610-1, 610-2, 710, 1010, 1210‧‧‧board tap structure 110-0, 110-1, 110-2, 110-3‧‧‧Tap conductor 112, 212, 712, 812, 912, 1012, 1112, 1212‧‧‧Storage contact 114, 914, 1014, 1114‧‧‧Substrate 116, 216, 916-00, 916-01, 916-10, 916-11, 1016-00, 1016-01, 1016-10, 1016-11, 1116, 1216-0, 1216-1‧‧‧bit Line (BL) contact 118、918‧‧‧Control terminal 120-0, 120-1, 920-0, 920-1‧‧‧Current terminal 122, 722, 922‧‧‧Memory layer 124, 224, 324-0, 324-1, 924-0, 924-1, 1124-0, 1124-1‧‧‧ Plate opening 226, 228, 426, 428, 926-1, 926-2, 928, 1202-0, 1202-1‧‧‧Word line 230, 234, 330, 430, 530, 930, 1130, 1230‧‧‧Arrow, direction 232-0, 232-1, 232-2, 332-0, 332-1, 332-2‧‧‧Storage contact group 606-0, 606-1, 606-2‧‧‧ board segment 834‧‧‧ board decoder circuit 836-0…836-n‧‧‧Board driver circuit 909‧‧‧Top plate insulator 910-0, 910-1, 1110-0, 1110-1‧‧‧Contact structure 911‧‧‧Insulated side wall 938‧‧‧Bit line isolation structure 940, 1240‧‧‧column isolation 942-0, 942-1, 942-2, 942-3, 944-0, 944-1, 1042-0, 1042-1, 1044, 1142-0, 1142-1, 1142-2, 1242-0, 1242-1, 1244-0, 1244-1‧‧‧Insulation layer 948、1148‧‧‧Peripheral Transistor 950, 952, 954, 1052, 1152, 1154, 1252‧‧‧ views 956-0, 956-1‧‧‧active area 1002-0, 1002-1, 1048, 1102-0, 1102-1‧‧‧Transistor 1058-0, 1058-1, 1158-0, 1158-1‧‧‧Gate Bias Structure 1060‧‧‧Contact surface ADD/MODE‧‧‧Address and/or mode signal PDRV0…PDRVn‧‧‧Board drive signal TIMING‧‧‧Timing signal VDSEL‧‧‧Deselect voltage VPL0…VPLn‧‧‧Board voltage VSEL‧‧‧Select voltage

Fig. 1 is a side sectional view of an integrated circuit (IC) device according to an embodiment. 2A to 2C are plan views of an IC device according to an embodiment. FIGS. 3A and 3B are plan views of an IC device showing an alternative board structure for the contact pattern of the bit line like FIGS. 2A to 2C. 4A to 4C are plan views of an IC device according to another embodiment. FIG. 5A and FIG. 5B are plan views showing an IC device having an alternative board structure for bit line contact patterns like those in FIG. 4A to FIG. 4C. Figure 6 is a top plan view of a plate structure that can be included in the embodiment. Figure 7 is a side cross-sectional view of a board tap structure that can be included in the embodiment. Figure 8 is a block diagram of the board decoding configuration that can be included in the implementation. 9A and 9B are diagrams showing an IC device according to a particular embodiment. 10A and 10B are diagrams showing an IC device according to another special embodiment. FIG. 11A and FIG. 11B are diagrams showing an IC device according to a further specific embodiment. FIG. 12A and FIG. 12B are diagrams showing an IC device according to another special embodiment.

100‧‧‧Integrated circuit (IC) device

102‧‧‧Access device

104‧‧‧Storage element

106‧‧‧Board structure

108‧‧‧Bit Line

110‧‧‧Board tap structure

110-0, 110-1, 110-2, 110-3‧‧‧Tap conductor

112‧‧‧Storage Contact

114‧‧‧Substrate

116‧‧‧Bit Line (BL) Contact

118‧‧‧Control terminal

120-0, 120-1‧‧‧Current terminal

122‧‧‧Memory layer

124‧‧‧plate opening

Claims (20)

An integrated circuit (IC) device comprising: a plurality of access transistors formed in a substrate and having control terminals connected to a word line, the word line extending in a first direction; formed on the substrate A plurality of two-terminal programmable impedance elements; at least one conductive plate structure formed on a plurality of rows and columns of the programmable impedance element, and the at least one conductive plate structure is connected to the programmable impedance element A common conductive connection of a plurality of rows and columns, the at least one conductive plate structure extends in at least the first direction; a plurality of storage contacts, each of the plurality of storage contacts receives a first current from each access transistor A terminal extending to one of the programmable impedance elements; a plurality of bit lines formed on the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and A second current terminal of each access transistor extends through the opening of the at least one plate structure to a plurality of bit line contacts of one of the bit lines, wherein the access transistor and the programmable impedance The components form a transistor and a plurality of memory cells with programmable impedance components. The IC device according to claim 1, wherein: the at least one plate structure includes an opening corresponding to each bit line contact, and each bit line contact extends through the opening. The IC device according to claim 1, wherein: the at least one plate structure includes an opening, and a plurality of bit line contacts extend through the opening. The IC device according to claim 1, wherein: the at least one plate structure includes a plurality of extension plate members extending in the first direction, and the bit line is in contact with the extension plate member to the bit line Extend between. The IC device of claim 4, wherein: the storage contacts are arranged in two rows extending in the first direction; and each plate member is conductively connected to no more than two rows of storage contacts. The IC device described in the first item of the patent application further includes: a board tap structure having a conductive connection connected to the at least one board member and configured to apply a variable board voltage to the At least one plate member. The IC device according to claim 6, wherein: the board tap structure includes a board voltage conductor formed on the at least one board member, and a board voltage conductor extending from the at least one board member to the board voltage conductor Board tap access. The IC device of claim 1, wherein: the programmable impedance element includes at least one memory layer, and the at least one memory layer can respond to an electric field that induces a redox reaction in the memory layer It is programmed between at least two different impedance states. An integrated circuit (IC) device comprising: a plurality of access transistors formed in a substrate and having a control terminal connected to a word line, the word line extending in a first direction ; A plurality of two-terminal programmable impedance elements formed on the substrate and arranged in a plurality of groups; a plurality of conductive plate structures, each formed on a different group of the plurality of programmable impedance elements, and having A common conductive connection connected to the plurality of programmable impedance elements of the different groups, each group includes a plurality of rows and columns of the programmable impedance element, and each conductive plate structure extends in at least the first direction; A plurality of storage contacts, each of the plurality of storage contacts extends from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed on the board structure, The bit line is in a second direction different from the first direction Extending toward the middle; and a plurality of bit line contacts extending from a second current terminal of each access transistor through the opening of the at least one plate structure to one of the bit lines, wherein the access transistor A transistor and a plurality of memory cells of the programmable impedance element are formed with the programmable impedance element. The IC device according to claim 9, wherein: each storage contact includes at least one first-type contact structure extending perpendicularly from the substrate; and each bit line contact includes compared with the first-type contact Structure and at least one second type contact structure that terminates at a larger vertical distance from the substrate. The IC device according to claim 10, further comprising: a board tap structure having a conductive connection connected to at least one of the board members, the board tap structure including formed on the at least one A plate voltage conductor on the plate member, and a plate tap path extending from the at least one plate member to the plate voltage conductor. The plate tap path is on the substrate compared to the second type contact structure. One ends at the same distance. The IC device according to claim 9, wherein: each storage contact includes at least one first-type contact structure extending perpendicularly from the substrate; and each bit line contact includes at least the first-type contact structure . According to the IC device described in claim 12, each bit line contact further includes at least one second type contact structure extending perpendicularly from the corresponding first type contact structure. The IC device as claimed in claim 12, further comprising: a plate patterned from a metallization layer formed on the plate structure and having a conductive connection connected to at least one of the plate structure Tap structure. The IC device according to item 14 of the scope of patent application, wherein: the board tap structure is in direct contact with the at least one board structure. The IC device according to claim 9, wherein: the programmable impedance element includes at least one memory layer, and the at least one memory layer responds to an electric field included in a redox reaction in the memory layer Programmable between at least two different impedance states. An integrated circuit (IC) device, comprising: a plurality of bit lines extending in a first direction; a second bit line formed between the bit line and a substrate and different from the first direction At least one conductive plate structure extending in the direction; a plurality of two-end programmable impedance elements, the plurality of two-end programmable impedance elements are arranged in a plurality of rows and columns, and have a plate connected to the at least one Common conductive connection; a plurality of access transistors formed in the substrate and connected to a control terminal connection of a word line extending in the second direction; a plurality of bit line contacts, each of which is connected from the bit line One of them extends through an opening of the at least one plate structure to a first current terminal of one of the access transistors; and a plurality of storage contacts, each of which extends from a programmable impedance element to a phase A second current terminal of the corresponding access transistor, wherein each access transistor and its corresponding programmable impedance element form a memory cell. The IC device according to claim 17, wherein: the at least one conductive plate structure includes a plurality of plate members extending in the second direction. The IC device according to claim 17, wherein: each bit line contact includes a first type contact structure and a second type contact structure stacked on the first type contact structure; and Each storage contact includes the first type contact structure and does not include the second type contact structure. The IC device of claim 17, wherein: the programmable impedance element includes at least one memory layer, and the at least one memory layer responds to an electric field included in a redox reaction in the memory layer Programmable between at least two different impedance states.

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