TW201225100A - Dynamic optimization of back-end memory system interface - Google Patents

Abstract

A structure, and corresponding operating techniques, are presented for the internal controller to memory circuit interface for memory systems such a flash memory card or other similarly structured devices. The interface between the controller circuit and memory circuit (or circuits) includes a feedback process where the amount of error that arises due to controller-memory transfers is monitored and the transfer characteristics (such as clock rate, drive strength, etc. ) can be modified accordingly. Techniques are also presented for dynamically optimizing the performance of the controller-memory (or ''back-end'') interface of a non-volatile memory system. Memory systems are usually designed to have a certain amount of error tolerance for error that can then be corrected by ECC. In may circumstances, such as when a device is new, the ECC capabilities of the system exceed what is needed to correct data storage errors. In these circumstances the memory system internally allots a non-zero portion of this error correction capacity to the back-end interface. This allows for the interface to operate at, for example, higher speed or lower power, even though this will likely lead to transmission path error. The system can also calibrate the back-end interface to determine that amount of error that result from various operating conditions, allowing the operating parameters of the back-end interface to be set according to amount of error that is allotted to the transfer process.

Description

201225100 VI. Description of the Invention: [Technical Field] The present application relates to the operation of a reprogrammable non-volatile memory system such as a semiconductor flash memory, and more particularly to the memory system The internal interface between the controller and the memory circuit. [Prior Art] Recently, solid-state memories with non-volatile charge storage capability, especially as solid-state memories in the form of small form factor card packages, EEPRQM and flash eepr〇m, have become various mobile and handheld devices, It is the preferred storage device in information appliances and consumer electronics. Unlike RAM (random access memory), which is also a solid-state memory, the flash memory system is non-volatile and retains its stored data even after the power is turned off. In addition, unlike ROM (read-only memory), flash memory is similar to a disk storage device that is rewritable. Despite the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage devices based on rotating magnetic media, such as hard disk drives and floppy disks, are not suitable for mobile and handheld environments. This is due to the fact that the disk drive tends to be cumbersome and prone to mechanical failures' and has high latency and high power. Such undesired attributes make disk-based storage devices unsuitable for most mobile and portable applications. On the other hand, flash memory (both embedded and in a removable card) is ideally suited for mobile and handheld environments due to its small size, low power consumption, high speed and high reliability. Flash EEPROM is similar to EEPROM (Electrically Erasable and Programmable Read Only Memory) because it can be erased and new data can be written or "processed" to "Memory 157533.doc 201225100" In the body cell - non-volatile memory. Both are used in the field effect transistor structure - floating (unconnected) conductive gate 1 floating conductive gate is positioned in the semiconductor substrate - above the channel region, between the source and the drain region. Next, a - control closure is provided above the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge held on the floating gate. That is, for a given charge level on one of the floating gates, there is a corresponding voltage that must be applied to the control gate before the J transistor is turned on to permit conduction between its source and drain regions. In particular, flash memory such as flash EEPROM allows several complete memory cell blocks to be erased simultaneously. The floating gate maintains a range of charges and can therefore be programmed to a threshold voltage window. Any threshold voltage level within the threshold voltage. The size of the threshold voltage window is delimited by the minimum threshold level and the maximum threshold level of the device, and the minimum threshold level and the maximum threshold level of the device are Corresponding to the range of charge that can be programmed onto the floating gate. The threshold window generally depends on the characteristics, operating conditions and history of the memory device. In principle, each different analyzable threshold voltage level range within the window It can be used to specify one of the cells to define the state of the memory. A transistor that acts as a memory cell is usually programmed into a "programmed" state by one of two mechanisms. In "hot electron injection", Applied to the endless The high voltage crosses the substrate channel region to accelerate the electrons. At the same time, a high voltage applied to one of the control gates pulls the hot electrons through a thin gate dielectric up to the floating gate. In "tunneling injection", The substrate applies a high voltage to the control gate. In this way, electrons are pulled from the substrate to the intermediate floating gate. Although historically the term "stylized" is used to describe the injection of electrons into the memory cell by 157533.doc 201225100 One writes to a memory by initially erasing the charge storage unit to change the state of the memory, but it is now used interchangeably with more common techniques such as "write" or "record". It can be erased by several mechanisms. Memory device. For eepr〇m, a high voltage can be applied to the substrate relative to the control gate to induce electrons in the floating gate to tunnel through the thin oxide to the substrate channel region (ie, Fule - Fowler-Nordheim tunneling) to erase a memory unit. Usually, EEpR〇N^ can be erased bit by byte. For flash EEPROM, the memory system can erase all of it at once. or Erasing one or more minimum erasable blocks at a time, wherein a minimum erasable block can be composed of one or more segments and each segment can store 512 bytes or more than 5n bytes The memory device typically includes one or more memory chips that can be mounted on a card. Each memory chip contains peripheral circuitry (such as a decoder and erase, write, and read circuitry). Supports one memory cell array. The more complex memory device also has a controller that performs smart and higher-order memory operations and interfaces. There are many commercially successful non-volatile solid-state memories currently in use today. Body devices. These memory devices may be flash EEPROM or other types of non-volatile memory cells. In Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063 and 5,661,〇53, Examples of flash memory and systems and methods of making the same are given in U.S. Patent Nos. 5, 3, 421, and 6, 222, 762. In particular, a flash memory device having a NAND string structure is described in No. 5, 570, 315, No. 5, 903, 495 157 533. doc -6 - 201225100 No. 6, (Μ 6,935 赖国专财n n also has a charge for storing A memory cell of a dielectric layer is used to fabricate a non-volatile memory device that uses a dielectric layer in place of the previously described conductive floating gate device. Such memory devices utilizing dielectric storage elements have been described by Eitan et al. , NROM . A Novel Localized Trapping, 2-Bit Nonvolatile

Memory Cell" (IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545). A dielectric layer extends across the channel between the source diffusion region and the drain diffusion region. The charge for one data bit is localized in the dielectric layer adjacent to the drain and the charge for the other data bit is localized in the dielectric layer adjacent to the source. For example, U.S. Patent Nos. 5,768,192 and 6, the entire disclosure of which is incorporated herein by reference. The multi-state data storage is implemented by separately reading the binary state of the charge storage region that is spatially separated within the dielectric. To improve read and program performance, multiple charge storage elements or memory transistors in an array are read or programmed in parallel. Therefore, the suffix element "page" is read or programmed together. In the existing memory architecture, a column contains a number of interlaced pages or it can constitute a page. All memory elements of a page will be read or programmed together. In the Shanyin C memory system, the erase operation can take longer than reading and programming = a long order of magnitude. Therefore, it is desirable to have a substantial size erase block. In this way, the erase time is spread over a large memory cell aggregate. The nature of flash memory means that the data must be written to the erased record. 157533.doc 201225100 Memory location. If a data from a logical address of a host is to be updated, one way is to rewrite the updated data in the same physical memory location. That is, the logical to physical address mapping is not changed. However, this would mean that the entire erase block containing the physical location will be erased first and then overwritten with the updated information. This update method is inefficient because it requires erasing and writing an entire erase block, especially if the data to be updated is only a small portion of the erased block. It will also result in a higher frequency erase recirculation of the memory block' which is undesirable in view of the limited durability of this type of memory device. The data transmitted through the external interface of the host system, the memory system, and other electronic systems is addressed and mapped to a physical location of a flash memory system. Usually, the address of the data file generated or received by the system is mapped to a different range of continuous logical address space established for the system based on the logical data block (hereinafter referred to as "LBA interface"). The breadth of the address space is usually sufficient to cover the full range of addresses that the system can handle. In one example, the drive communicates with a computer or other host system through this logical address space. This address space has a breadth of data storage capacity sufficient to address the drive. There is a constant effort to improve the performance of memory devices by reducing power consumption and increasing device speed. As mentioned above, non-volatile memory devices are typically formed by one controller circuit and one or more memory crystal cells connected to each other via a busbar structure. The controller/memory device interface settings (such as the voltage value and frequency used) are typically set according to the worst case scenario expected to have sufficient safety margins to avoid device failure. 157533.doc -8 - 201225100 Therefore, in most cases, the interface is operated under optimal conditions. Since this interface can be a limiting factor for device performance, there is room to improve the design of this interface. SUMMARY OF THE INVENTION In accordance with a general aspect of the present invention, an operational-non-volatile memory system method is presented. The non-volatile memory system includes: a controller circuit having a memory interface; a memory circuit having a non-volatile memory cell array and a controller interface; and the memory connected to the controller circuit The interface and the controller interface of the memory circuit are used for the transfer of data and commands between them - a bus bar structure. The memory (10) system can tolerate a "first-non-zero cumulative error amount" when the following operations are performed: data will be transferred from the controller to write to the memory array until subsequent readback from the memory array in the control The device receives the data. The method includes the controller assigning one of the first non-zero portions of the first error amount to the transfer of data between the control circuit and the memory circuit via the bus structure to 'the first-error amount The remainder is allocated to the writer, store, and read of the material on the memory circuit. The controller circuit sets the transfer characteristics of the operation between the controller circuit and the memory circuit to allow for at most the error of the first portion. In other aspects, the presentation operation includes a method of a memory circuit and a #volatile memory system of the controller circuit. The controller circuit performs a carrier error calibration for each of a plurality of values connecting each of the controller and one of the two or more operational parameters of the bus structure pin of the memory circuit. The processing program includes receiving a data set from the data set of the known data 157533.doc 201225100 through the transmission circuit on the controller, and receiving the data set from the receiving circuit and the receiving circuit on the memory circuit. . The received data set is stored in a buffer memory on the body circuit, and then the data set stored in the buffer memory of the memory circuit is transferred to the memory circuit via the memory circuit The bus structure 'receives the data set from the bus structure via the receiving circuit of the = and performs a comparison of the data set with the known pattern. The error amount associated with the transmission processing program is determined based on one or more operational parameters of the comparison pin. The memory system is then operated to allow a first non-zero error amount in the data transfer between the controller circuit and the memory circuit, wherein the controller circuit is based on the associated error amount determined based on the determination The error calibration handler selects the values of the operational parameters. 1 In accordance with another aspect of the present invention, a non-volatile memory system has: a controller circuit that includes a memory interface and logic circuit and a memory circuit that includes a non-volatile memory cell array , - control benefits interface and logic circuits. The memory system also includes a bus interface structure coupled to the memory interface of the circuit and the controller interface of the memory circuit for transferring data and commands between the controller and the memory circuit. a feedback processing circuit coupled to the controller and the receiver of the memory circuit during reception of the data between the controller and the memory circuit for receiving a result of the transmission as a result of the transmission The error amount information 'and one or both of the memory interface and the controller interface are adjusted in response to the error amount to pass the 157533.doc •10·201225100 delivery characteristics. In another aspect, the presenting method includes a method of non-volatile memory circuitry and a non-volatile memory system of a controller circuit. a logic circuit on the first of the controller circuit and the memory circuit; generating a -th-hash value based on a data set. Transmitting the data set and the first hash value to a bus structure by using one of the controller circuit and the first one of the memory circuits, and the controller circuit and the memory circuit The second of the _ receives the data set and the first hash value from the bus structure. And generating a first hash value according to the received data set in the logic circuit on the first of the controller circuit and the memory circuit, and then in the controller circuit and the memory circuit The first one compares the received first hash value with the second hash value. The system determines whether to change the controller circuit and the memory based on the comparison between the received first hash value and the second hash value by the logic circuit on the controller circuit and the second circuit of the memory circuit The nature of data transfer between body circuits. The various aspects, advantages, features, and embodiments of the invention are described in the following description of the example embodiments of the invention. All of the patents, patent applications, essays, other publications, documents, and the like referred to herein are hereby incorporated by reference in their entirety for all purposes. In the event of any inconsistency or conflict of definition or usage of terms between any of the incorporated publications, documents, or the like, and the application, the definition or usage of this application shall prevail. 157533.doc -11 201225100 [Embodiment] Memory System FIGS. 1 through 7 provide an exemplary memory system in which various aspects of the present invention can be implemented or illustrated. 8 through 10 illustrate preferred memory and block architectures for implementing various aspects of the present invention. 11 through 13 illustrate the use of an adaptive internal interface between the controller and the (or the) memory circuitry. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of the main hardware components suitable for implementing one of the memory systems of the present invention. The memory system 90 typically operates with a host 80 via a host interface. The memory system is typically in the form of a memory card or an embedded memory system. The memory system 9A includes a memory 200, and the operation of the memory 200 is controlled by a controller. The memory 2 includes one or more non-volatile memory cell arrays distributed on one or more integrated circuit wafers. The controller 100 includes an interface 110, a processor 120, an optional coprocessor 121, a ROM 122 (read only memory), a ram 130 (random access memory) and optionally a programmable non-volatile memory. Body 124. The interface 110 has a component that interfaces the controller to a host and interfaces the controller to the other component of the memory. The firmware stored in the non-volatile ROM 122 and/or the optional non-volatile memory 124 provides the processor 120 with a code that implements the functionality of the controller. The processor 12 or optional coprocessor 121 can process the error correction code. In an alternate embodiment, controller 100 is implemented by a state machine (not shown). In yet another embodiment, the controller 100 is implemented within a host. 157533.doc •12· 201225100 Physical Memory Structure Figure 2 schematically illustrates a non-volatile memory cell. The memory cell 10 can be implemented by a field effect transistor having a charge storage unit 2 (e.g., a floating gate or a dielectric layer). The memory cell also includes a source 14, a dipole 16 and a control gate 30. There are many commercially successful non-volatile solid state memory devices in use today. These memory devices may employ different types of memory cells, each of which has one or more charge storage elements. Typical non-volatile memory cells include EEPROM and flash EEPROM. An example of an EEPROM memory cell and a method of fabricating the same is given in U.S. Patent No. 5,595,924. U.S. Patent Nos. 5, 〇 7〇, 〇 32, 5, 095, 344, 5, 315, 541, 5, 343, 063, 5, 661, 053, 5, 313, 421, and 6, 222, 762. 1101^ Examples of the use of memory cells, EEPROM memory cells in a memory system, and methods of fabricating the same. Having a NAND memory cell structure is described in U.S. Patent Nos. 5,570,315, 5,903,495, and 6,046,935.

An example of a memory device "In addition, an example of a memory device using a dielectric storage element has been described by Eitan et al.: "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cellj (IEEE

Electron Device Letters', Vol. 21, No. 11, November 2000, pp. 543-545, and is described in U.S. Patent Nos. 5,768,192 and 6,011,725. In fact, 'the memory of the memory cell is read by sensing the conduction current across the source electrode and the drain electrode of a memory cell when a reference voltage is applied to the control gate. status. Therefore, for each given charge on the floating closed pole of the memory cell, a corresponding conductive current relative to a fixed reference control gate voltage can be detected. Similarly, the range of charge that can be programmed onto the floating gate defines a corresponding threshold voltage window or a corresponding conductive current window. Another-selection system, instead of the pain measurement, the conduction current in a divided current window can be set at the control gate—the threshold voltage is set for the given memory state in the test and the conduction m is still higher than—the threshold (4) . In one embodiment, the conduction current system is measured relative to the current limit (4) by verifying that the conduction current is flowing through the capacitance of the bit line. Figure 3 illustrates the relationship between source and drain currents 1 四个 and control gate voltage vCG for four different charges ^ to 94 that can be selectively stored at any one time for the floating gate. The four entities 1 〇 to 1 curve represent four possible charge levels that can be stylized on the - floating gate of the memory cell, which correspond to the four possible memory states, respectively. As an example, a threshold voltage window for a memory cell population can range from 05 V to 3.5 V. The seven possible regions of an erased state and six stylized states can be demarcated by dividing the threshold window into five regions at intervals of 〇5 ν for each region, respectively. "1", "2", "3", "4", "5", 6". For example, if one of the reference currents IREF' is used as shown, the memory cell programmed with φ can be regarded as being in a memory state "1" because the curve and Iref are at VcG = 〇5. 1. 〇 分 分 的 的 的 的 的 相 相 相 相 相Similarly, the system is in the "memory state" "5". 157533.doc •14· 201225100 As can be seen from the above description, the more states a memory cell is stored, the finer the threshold window is. For example, a memory device can have a plurality of memory cells. The memory cells have a threshold window ranging from -1.5 V to 5 V. This provides a maximum width of 6.5 V. If the memory cell wants to store 16 states, then each state can occupy from 2 〇〇 mV to 300 mV in the threshold window. This will require higher stylization and read operation accuracy to achieve the desired resolution. Figure 4A schematically illustrates a memory cell string organized into a NAND string. A NAND string 50 comprises a series of s-resonant transistors M1, M2, ..., Mn (e.g., n = 4, 8, 16 or higher) connected by their source and daisy chains. The pair of selection transistors SI, S2 control the connection of the memory transistor chain to the outside via the source terminal 54 and the gate terminal 56 of the NAND string, respectively. In a memory array, when the source select transistor S1 is turned on, the source terminal is coupled to a source line (see FIG. 4B). Similarly, when the drain select transistor S2 is turned on, the NAND A string of terminals is coupled to a bit line of the memory array. Each of the memory transistors 10 in the chain acts as a memory cell. It has a charge storage element 20 for storing a given amount of charge to indicate a predetermined memory state. One of the control transistors of each of the memory transistors allows control of the read and write operations. As will be seen in Figure 4B, the control gates 3 of the corresponding memory transistors in one of the NAND strings are all connected to the same word line. Similarly, a control gate 32 of each of the selected transistors s, S2 provides controlled access to the NAND string via its source terminal 54 and NMOS terminal 56, respectively. Similarly, the control gates 32 of the corresponding select transistors of one of the NAND strings are all connected to the same select line. 157533.doc •15· 201225100 When one of the addressed NAND transistors in a NAND string is read or verified during stylization, its control gate 30 is supplied with an appropriate voltage. At the same time, the unaddressed memory transistors are fully turned on by applying sufficient voltage across the control gates of the remaining unaddressed memory transistors in NAND string 50. In this manner, a conductive path is effectively formed from the source of the individual memory transistor to the source terminal 54 of the NAND string, and likewise from the drain of the individual memory transistor to the drain terminal 56 of the memory cell. A conductive path is formed. A memory device having such NAND string structures is described in U.S. Patent Nos. 5,570,3, 5, 5, 903, 495, 6, 046, 935. Figure 4B illustrates an example of a NAND memory cell array 2 10 constructed from a NAND string 50 such as that shown in Figure 4A. Along each row of the NAND string, a bit line (such as bit line 36) is tapped to the no terminal 56 of each NAND string. Along each bank of NAND strings, a source line, such as source line 34, is coupled to source terminal 54 of each NAND string. In addition, the control gates along one of the banks of the NAND string are connected to a word line (such as the control gate line 42 of the selected transistor column). Connecting one of the banks of one of the NAND strings to a select line (such as select line 44) β can address one of the banks of the NANDf by the word line of one of the NAND strings and the appropriate voltage on the select line. Memory cell column. When reading one memory in a NAND string

The level of charge stored in the memory cell being read.

~, also network ι (for example) a NAND configuration of a memory cell page. Figure 5 basically shows a library of NAND strings 50 in the memory array 210 of Figure IB. 157533.doc • 16 - 201225100, wherein the details of each NAND string are as shown in Figure 4A. A "page" (such as page 6) enables parallel sensing or stylization of one of the memory cell groups. This is achieved by a corresponding page of sense amplifiers 212. The sensed results are latched in a corresponding set of latches 214. "Each sense amplifier can be coupled to a NAND_ via a bit line. The page is enabled by the control gates of the memory cells of the page that are commonly connected to a word line 42 and each memory cell is accessible by a sense amplifier accessible via a bit line 36. As an example, when the memory cell page 60 is sensed or programmed separately, a sense voltage or a stylized voltage is applied to the common word line WL3, respectively, along with applying an appropriate voltage to the bit line. 'The physical organization of memory An important difference between flash memory and other types of memory is that memory cells must be stylized from the erased state. That is, the floating gate must first discharge the charge. The stylization then adds a desired amount of charge back to the floating gate. It does not support the self-floating removal of a portion of the charge to change from a more stylized state to a less programmed state. This means that the update data cannot overwrite the existing data and must be written to a location that was not previously written. In addition, erasing the vacant charge from the floating gate typically takes a considerable amount of time. For some reason, the memory-by-memory or even page-by-page erasure will be used to divide the cell array into a large number of memory cells. As is common for flash EEPROM systems, the block is erased. That is, each block contains the smallest number of memories I57533.doc -17· 201225100. Although the integration of a large number of memory cells to be erased in parallel will improve the erase performance, a large number of blocks also need to process a larger number of updated and obsolete data. Just before the block is erased, it is necessary to collect the waste project to save non-obsolete data in the block. Each block is usually divided into a number of m stylized or read soaps 70. In the item embodiment t, the individual pages can be divided into segments, and the segments can contain as the most basic purpose of the - basic stylized operation. ItM or multiple data pages are usually stored in one memory cell. - The page can store one or more sections. A section includes user data and additional items. Multiple blocks and pages distributed across multiple arrays can also operate as metablocks and metapages. If it is distributed over multiple wafers, it can operate as a metablock and a metapage. Example of multi-level memory cell ("MLC") memory segmentation A non-volatile memory in which memory cells each store a plurality of data bits is described in conjunction with FIG. A particular example is a memory formed by a field effect transistor array, each field effect transistor having a charge storage layer between its channel region and its control gate. The charge storage layer or cell can store a range of charges to produce a threshold voltage range for each field effect transistor. It is possible that the threshold voltage range spans a threshold window. When the threshold window is divided into a plurality of threshold voltage sub-ranges or regions, each analyzable region is used to represent a different memory state of a memory cell. The plurality of memory states can be written by one or more binary bits. For example, a memory cell divided into four regions can support four states that can be coded as 2-bit data. Similarly, a memory cell divided into eight regions can support 157533.doc -18- 201225100 can be written as three-bit data in eight memory states and so on. All Bits, Full Sequence MLC Stylization Figure 6(0) through Figure 6(2) illustrate an example of a stylized four state memory cell population. Figure 6(0) illustrates a memory cell population that can be programmed to represent four different threshold voltage distributions of memory states "0", "1", "2", and "3", respectively. Figure 6(1) illustrates the initial "erased" threshold voltage distribution of an erased memory. Fig. 6(2) illustrates an example of a memory after a plurality of memory cells in the memory cells have been programmed. Essentially, a memory cell initially has an "erased" threshold voltage and the stylization will move it to a higher value into one of the two regions demarcated by the verification levels vVi, vV2, and vV3. . In this way, each memory cell can be programmed into one of the three stylized states "1", "2", and "3" or remain "erased" in the unstamped state. . As the degree of stylization of the memory is increased, the initial distribution of the "erased" state as shown in Fig. 6(1) will become narrower and the erased state will be represented by the "〇" state. A 2-bit code having a lower portion element and an upper portion element can be used to represent each of the four memory states. For example, the "〇", "1", "2" and "3" states are represented by "11", "01", "00" and "10" respectively. The 2-bit data can be read from the memory by sensing in the "full sequence" mode, in the "full sequence" mode, by using the three sub-passes with respect to the read boundary thresholds rVi, rVz And rV3 senses and senses two bits together. Bitwise MLC Stylization and Reading 157533.doc -19- 201225100 Figures 7A through 7E illustrate the stylization and reading of a 4-shaped bear memory encoded with a given 2-bit code. Figure 7A illustrates the threshold voltage distribution of a 4-state memory array when each of the cells is stored using a 2-bit code to store two data bits. This 2-bit code is disclosed in U.S. Patent No. 7,057,939. Figure 7B illustrates the lower page stylization (lower part element) in a 2-pass stylization scheme using a 2-bit code. The fault-tolerant LM new code essentially avoids any upper-page transitions going through any intermediate state. Therefore, the lower page of the first question is programmed to make the logic state (upper part element) by the "unprogrammed" memory state "" to the "intermediate" state specified by (X, 0). Lower part element) = (1, υ transition to an intermediate state (χ, 〇), where a programmed threshold voltage is greater than Da but less than Dc. Figure 7C illustrates a 2-pass stylization scheme using a 2-bit code The upper page is stylized (top part). In the second pass of stylizing the upper page bit to "〇", if the lower page bit is at M, then by "memorizing" the memory state "〇" is programmed to Γι" to indicate the logical state 1, 1) to (〇' υ. If the lower page bit is "〇", it is obtained by staging from "intermediate" state to "3" The logical state (〇, 〇 类似 similarly 'if the upper page wants to remain at "1" and the lower page has been programmed to "〇", it is represented by stylizing the "inter-order" state to "2" It will take a transition from the "intermediate" state to (b 0). Figure 7〇 illustrates the identification with a 2-bit code. The read operation of the part under the code 4 state memory. First perform a read operation to determine whether the LM flag can be sold. If it is readable, the upper page is programmed and the β operation will be read. The lower page data is correctly generated. On the other hand, if the upper page has not been programmed 157533.doc -20-201225100, the lower page data will be read by a read A operation. Fig. 7E illustrates the identification of 2 bits. The coded code 4 is required for the read operation of the upper part of the state memory. As is apparent from the figure, the upper page read will need to be read A and B respectively with respect to the threshold voltage, DB and Dc respectively. Reading 3 times of reading C. In the bitwise scheme for a 2-bit memory, a physical memory cell page will store two logical data pages, that is, corresponding to the lower part of the element - the lower data page and Corresponding to an upper data page of the upper part element. Binary and MLC memory partitioning FIG. 6 and FIG. 7 illustrate an example of a 2-bit (also referred to as "D2") memory. As can be seen, 'a D2 memory Divide the threshold range or window into 4 zones of the specified 4 states. Similarly In 03, each memory cell stores 3 bits (lower, middle, and upper part elements) and there are 8 areas. In 〇4, there are 4 bits, 16 areas, etc. With the memory The limited threshold window is divided into more regions, and the resolution of the stylization and reading will need to be more refined. Two problems arise as the memory cells are configured to store more bits. First, # Must be (4) accurately stylized or (4) a memory cell threshold will be slower to program or read. In fact, in practice +, (storage and read) required sensing time often with the split bit Secondly, the square of the number increases. Secondly, the flash memory has a pair of long-term problems as it ages. When the memory is repeatedly programmed and erased, the charge is shuttled across a dielectric by (4) In and out of the floating gate 2G (see Figure 2, each owed, some charge can be trapped in the dielectric and will modify the threshold of the memory cell 157533.doc 21. 201225100 value. On a continuous basis, as the use, the threshold window will gradually narrow. Therefore, MLC memory is typically designed to have a trade-off between capacity, performance, and reliability. Conversely, it will be seen that for binary memory, the threshold window of memory is divided into only two regions. This will allow a maximum margin of error. Therefore, performing binary splitting while reducing storage capacity will provide maximum efficiency and reliability. The multi-pass bitwise stylization and reading technique illustrated in conjunction with Figure 7 provides a smooth transition between mLc and binary segmentation. In this case, if only the following parts are stylized, the memory is actually a binary segmented memory. Although this method does not fully optimize the range of the threshold window (as is the case in the case of a single-order memory cell ("SLC") memory, it has the use of parts below the MLC memory. The advantage of operating the same demarcation or sensing level. As will be explained later, this method allows "extracting" an MLC memory for use as a binary memory, or vice versa. It should be understood that mlc memory tends to have stricter usage specifications. Binary Memory and Partial Page Stylization A charge that is privately converted into a charge storage element of a cell is an electric field that disturbs the electric field of an adjacent memory cell. This will affect the adjacent memory cells (which essentially have the characteristics of a field effect transistor of a charge storage element. In particular, when sensed, the memory cells will appear to be higher than they are disturbed. One of the low-level thresholds (or more south of the stylized). - Generally speaking, 'If-Remember' It is programmed in the -first scene environment. J57533.doc •22- 201225100 Verification and service After the adjacent memory cells are then re-read with different charges and read in a different field environment, the read accuracy can be affected by the coupling between adjacent floating gates. This is called the "Yupin effect." As the integration of semiconductor memory becomes higher and higher, the disturbance of the electric field due to the stored charge between memory cells (YUpin effect) will become more significant due to the reduction of memory cell spacing. The bitwise MLC stylization technique illustrated in Figure 7 is designed to minimize stylized interference from memory cells along the same word line. As can be seen from Figure 7B, in one of the two stylized passes, the first pass , the threshold of the memory cell moves To the midway along the threshold window, the effect of the first pass is exceeded by the last pass. In the last pass, the threshold only moves one of the four 77s of the whole process. For S, for D2, the phase The difference in charge between adjacent memory cells is limited to a quarter of its maximum. For 〇3, in the case of three passes, the last pass limits the difference in charge to one-eighth of its maximum value. However, bitwise Multi-pass stylization techniques will be staggered by partial page stylization. A page usually remembers a group of cells along one column or word line, which is stylized as early as possible. It is possible to have multiple programs. Individually stylizing the non-overlapping parts of a page. However, they are stylized together in the last pass, and then a large difference is formed in the stylized charge in the memory cell. Since it is not all the memory cells of the page, it can be on the page. Completing the stylized disturbance and stylizing a larger sensing portion of the page will result in more stylized interference and will require accuracy limits.

157533.doc In the case of horse binary memory, the limit of operation In the preferred embodiment, the binary memory is configured to support partial page stylization, and in the partial page stylization one page is not The overlapping portion can be individually programmed in one of a plurality of stylized passes to the page. Programmability and read performance can be improved by operating on a large page size. However, when the page size is much larger than the write unit of the host (usually a 5 12-bit sector), its use will be inefficient. Operating at a finer detail than a page allows for a more efficient use of this page. An example between the binary and the MLC has been given. It should be understood that, in general, the same principle applies between a first memory having one of a first number of steps and a second memory having a second number of steps greater than the first s. Logic and Physical Block Structure Figure 8 illustrates a memory managed by a memory manager that resides in one of the software components of the controller. The memory 200 is organized into a number of blocks, each of which is a minimum erasing unit. Continuing with the embodiment, the memory system can be operated by forming a block aggregate into a "metablock" and also forming a larger erase unit of the "block". For convenience, this description refers to a erase unit as a metablock, although it should be understood that some systems operate with a larger erase unit such as a macroblock formed by a metablock aggregate. The host 80 accesses the memory 200 when an application is run under a file system or operating system. Typically, the host system addresses the data in units of logical segments, where, for example, each segment can contain 512 bytes of data. In addition, the 'generator usually consists of a logical cluster as a unit to read or write H logical clusters—or multiple logical sections. An optional host side memory manager may be present in some host systems at 157533.doc -24· 201225100 to perform lower level memory management at the host. In most cases, during a read or write operation, host 80 essentially issues a command to memory to read or write a segment of the _string data logical segment with consecutive addresses. A memory side manager 300 is implemented in the controller 1 of the memory system 9 to manage the wealth and retrieval of data to the host logical segments in the metablock of the flash memory 200. The memory manager includes a front end system 31 and a back end system 320. The front end system 31A includes a host interface 312. Backend system 320 includes a number of software modules for managing erase, read, and write operations on metablocks. The memory manager also maintains the flash control memory 2 and the system control data and directory data associated with its operation in the controller RAM 130. Figure 9 illustrates a software module of a backend system. The back-end system mainly includes two functional modules: a media management layer 33 and a data stream and sequencing layer. The media management layer 330 is responsible for the organization of logical data storage in a flash memory block structure. More details will be provided later in the chapter on “Media Management”. The data stream and sequencing layer 340 is responsible for the sequencing and transmission of data sectors between a front end system and a flash memory. This layer includes a command sequencer 342, a low order sequencer 344, and a flash control layer 346. More details will be provided later in the chapter on "Lower Order System Specifications". The suffix manager 300 is preferably implemented in the controller 1 。 。. It translates the logical address received by the autonomous I57533.doc •25-201225100 machine into the physical address of the actual stored data in the memory array and then records these address translations. Figures 〇A(i) through i〇A(iii) schematically illustrate the mapping between a logical group and a metablock. The metablock of the physical memory has N physical sections for storing - N data logical sections of the logical group. Figure 1A(i) shows data from a logical group LGi where the logical segments are in consecutive logical order 0, 1, ..., iV-7. Figure 1A(ii) shows the same data stored in the same block in the same logical order. When a metablock is stored in this way it is called "sequential." In general, 'metablocks may have data stored in a different order' in this case the metablocks are referred to as "disordered" or "chaotic". There may be an offset between the lowest location of a logical group and the lowest location of the metablock to which it is mapped. In this case, the logical sector address is surrounded from the bottom backward in the metablock. A loop to the top of the logical group. For example, in Figure 10A(iii) the 'meta block' is stored in its first position with the data of the logical section & When the last logical segment is reached, it wraps around segment 0 and eventually stores data associated with the logical segment moxibustion - in its last physical segment. In the preferred embodiment, a page of tags is used to identify any offset, such as identifying the starting logical sector address of the data stored in the first physical segment of the metablock. When two blocks differ by only one page of labels, the two blocks are considered to store their logical segments in a similar order. Figure 10B schematically illustrates the mapping between logical groups and metablocks. Each logical group 380 is mapped to a unique metablock 37, where the data 157533.doc -26 - 201225100 is excluded from the small number of logical groups being updated. After a logical group has been updated, it can be mapped to a different metablock. The mapping information is maintained in a logical-to-entity directory set, which will be explained in more detail later. Adaptive Controller - Memory Interface This section presents a feedback mechanism and processing unit that monitors the internal controller of the memory system - the memory interface 70 is transmitted and the interface settings can be adjusted accordingly . This allows the system to optimize interface performance. For example, it may be possible to reduce the power of the system or accelerate the bus time of the interface, which (as this can usually be an internal performance bottleneck), as allowed outside the memory system (ie, from the host) allows for an increase. efficacy. In the case of transmission errors, the feedback processing unit may decide whether to adjust the interface settings, perform a transmission retry, or ignore the error with the help of interface integrity feedback and other sensors or parameters (at the end of the embodiment). The following description is also given in the context of a memory card using one of the NAND type memory array architectures shown in FIGS. 4A, 4B, and 5, but is easily extended to similar internal interfaces and other forms of other architectures. Memory and non-card use [such as embedded systems, SSDs, etc. Although the following discussion may be based on various example embodiments to provide specific examples, the techniques and structures herein are generally fully applicable to a memory system having a controller and a plurality of independently operable libraries, wherein the libraries include Flash memory or one of a variety of other types of non-volatile memory that can be used to store system data that the controller can use to manage the memory system. In addition to the above-mentioned (4) reference to the memory system, the 157533.doc • 27-201225100 memory system may also include the following numbers of US patents, patent applications and various memory presented in the application. System: 7,480,766,1^-2005-0154819-A1 ' US-2007-0061581-A1 ' US-2007-0061597-Al ' US-2007-0113030-A1 ' US-2008-0155178-A1 ' US-2008-0155228 -A1, US-2008-0155176-A1, US-2008- 0155177-A1 ' US-2008-0155227-A1 ' US-2008-0155175-A1, 12/348,819, 12/348, 825, 12/348, 891, 12/348, 895 12/348,899, 12/642,584, 12/642,611, US 12/642,649, 12/642,728, 12/642,740 and 61/142,620. Before discussing the example embodiments, this section will begin with further consideration of the issues to be resolved. The controller-memory device interface is used to transfer data between a controller (100 'Fig. 1) and one or more NAND (in the exemplary embodiment) device (200, Fig. 1). (Note that this discussion is about the internal interface between controller 1 快 and flash memory 2 记忆 on memory system 90, and interface 110 is the host interface for communication with the external memory system.) Different NAND interface modes have been developed to increase the speed of compromise, the interface performance of power consumption, and the like. Since this interface is often a performance bottleneck, these interfaces are pushed to the limit of system performance. To avoid data errors, interface settings (such as voltage, frequency, drive strength, and slew rate control) are set for worst-case scenarios (extreme temperatures, extreme load capacitance, extreme voltages, etc.). Therefore, devices are typically designed to have a worst-case safety margin, which translates to the maximum of typical conditions. Here, the 5L conditional towel 1 optimizes the interface setting to a higher interface performance without being guilty of production. Without a mechanism such as that presented below, the 157533.doc 201225100 memory device will continue to operate with a worst case performance setting. For example, a simple comparison between a 16-bit normal mode at 33 MHz nominal bus frequency and 40 MHz for acceleration, 50 MHz for super-acceleration, and 60 MHz for super-acceleration. Significant delay reductions of approximately 17%, 33%, and 45%, respectively, were produced. This is shown in Table 1, where the line frequency, the corresponding period (tcyc), the time at which 2142 bytes are transmitted, and the speed ratio at 33 MHz. Frequency tcvc 2142B xfr time ratio 33 MHz 30.3 ns 32454.5 ns 1.00 40 MHz 25.0 ns 26775.0 ns 0.83 50 MHz 20.0 ns 21420.0 ns 0.66 60 MHz 16.7 ns 17850.0 ns 0.55 Table 1 In the prior art, usually a flash will be flashed for a given product The interface performance is set to a fixed performance. This design is therefore factored into the worst case design. In some products, the flash interface is designed for a "near worst case" design that allows for a certain interface performance to be optimized, but at the risk of a lower device yield or increased data error. This section presents a feedback mechanism and processing unit that monitors the interface transport integrity and adjusts the interface settings accordingly to optimize interface performance. In the case of a transmission error, the feedback processing unit (with the help of interface integrity feedback and possibly other sensors or parameters) may decide whether to adjust the interface settings, perform a transmission retry, or ignore the error. In the absence of a transmission error, the feedback processing unit may decide to leave the interface settings as they are or modify the interface settings to increase interface performance. Therefore, 157533.doc -29-201225100 can be used to make the feedback processing unit obtain different levels of information (such as binary pass/fail indication, pass/fail plus error number or pass/fail plus error number plus error) The interface integrity feedback mechanism is designed in a way. According to this embodiment, the feedback mechanism can be further optimized using existing device infrastructure or by a dedicated mechanism such as a hash value engine. This proprietary mechanism can be implemented in hardware, software, or a combination of these. The hash value engine can also be supplemented by an error correction engine that has the ability to correct transmission errors. This method will allow the interface to cope with a certain level of bit error rate while still achieving optimal performance. Transmission correction capability is valuable because the prior art ECC design for NAND bit failures only considers errors in the memory itself, not when it is possible to transfer data between the controller and the memory device. The interface is wrong. The possibility of transmission errors increases as the performance of an interface increases. Making old ECC processing interface errors degrades old ECC capabilities in terms of the probability of performance and unrecoverable errors. Designing a dedicated interface error correction engine allows for a "division and rule" so that legacy ECCs focus only on NAND generated errors. (Additional background details regarding ECC can be found in U.S. Patent, Patent Publication, and Patent Application Serial No.: 2009/0094482, 7,502,254 ' 2007/0268745, 2007/0283081, 7,310,347, 7,493,457, 7,426,623, 2007/0220197, 2007 /0065119, 2007/0061502, 2007/0091677, 2007/0180346, 2008/0181000, 2007/0260808, 2005/0213393, 6,510,488 ' 7,058,818 ' 2008/0244338 ' 2008/0244367 ' 157533.doc •30- 201225100 2008/0250300 and 2008/0104312.;) Figure 11 is a block diagram showing one of the feedback mechanisms, but based on a typical prior art existing NAND/controller infrastructure. This will help to further illustrate some of the concepts involved and provide an alternative embodiment of an adaptive interface. In Fig. 11, in order to simplify the discussion, only elements related to the present description are explicitly shown to suppress other elements. On the controller 1, an ASIC core 411, an ECC circuit 413, an output buffer 415, an input buffer 425, a transmission circuit 417, and a receiving circuit 427 are provided. Although shown here as separate 'but in actual implementations this may not be the case: the input buffer and the output buffer may be overlapping or identical; the transmitting and receiving circuits share the same or even the same; ECC The circuit can be implemented as software in the ASIC core and the like. The components shown on the memory side 2' are read circuit 431 and transfer circuit 441 (which may also partially or completely overlap), an input data buffer 433 and an output data buffer 443 (which may Similarly a single buffer) and NAND core 43 5 . The controller 1 is then connected to the memory circuit by bus bar structure 401. Once a host data set is received at controller 100, one of the host data sets typically flows from ASIC core 411 to output data buffer 415, through transmission circuit 417, and to bus bar structure 401. On the memory 200, the data is transferred from the bus to the input buffer 433 by the receiving circuit 431 and then written into the NAND core 435. Then, when the host wants to access the data, the data is read from the NAND core 435 to the output data buffer 443, transmitted to the bus bar structure 401 by the transmission circuit 441, and then transmitted from the bus by the receiving circuit 427. The row is read into the input data buffer 425 of the controller 157533.doc -31 - 201225100. Remember more than & 1 a. An implicit system usually uses an error correction code (ECC) to detect and correct errors that can be entered into the data, where the controller generates and transmits with the data and writes to the core and then This information - the corresponding ECCeEcc engine 4 can be used after reading the post and its corresponding ECC, allowing the data to be checked and corrected as needed before being passed to the host. Although ECC can be used to correct data errors, it can only correct a limited number of errors' where the quantity is a design choice. Within these capabilities, the ECC engine 413 can correct for any errors accumulated during the round trip, including transmission errors and errors associated with the NAND core 435 itself (such as write errors, read errors, and Interference and other degradation of data at the time of storage" However, the choice of ECC is usually based solely on considerations related to core-435 errors. In some configurations, such as those disclosed in certain references cited above for ECC. "Strong Ecc", the code is based on the nature of the memory and how the data state is mapped into the memory. The transfer between the controller and the memory is mostly ignored and is considered as an unadded error. The interface needs to be set accordingly, resulting in setting the parameters according to the worst, near worst case, as explained above. A first embodiment set is based on the elements of the figure to supply for optimization Feedback of the interface characteristics. On a round trip, a data set is sent from the controller to the memory along with the corresponding ECC and sent back to the controller, as explained above. A read after quasi-write is quite the same, except that the data (and corresponding ECC) is not actually written into the memory core. After a write transfer is sent from the controller 100 to the memory circuit 200, 157533.doc

-32- 201225100 The controller can use buffer latches 433 and 443 to read back the data. This is indicated by path 437, although if the input buffer is the same buffer as the output buffer, there will be no actual transfer. Since this round trip removes any errors associated with array 435 itself, this isolates the impact of transmission' and allows ECC engine 413 to determine the complete I1 of the memory interface. These interface parameters can then be modified and the process can be reissued. This optimizes both write and read interface parameters. Figure 12 is a block diagram illustrating another embodiment set, but wherein the feedback mechanism uses a hash value engine and an optional data correction engine dedicated to the interface. Figure 12 does not mention controller and memory chips, but rather is presented in terms of circuitry on transmitter side 520 and receiver side 530, as any of these may be controlled as set forth below. The other can be a memory 'depending on whether it is a read handler or a write handler, and there is no need for symmetry on both sides. Transmitter side 520 will also include a write data buffer 521 and a transmission interface circuit 529. It will now also include a hash value generator 525 and a multiplexer 527. In a transfer processing program, the data to be written (523) is transferred from the write buffer 520 to the hash value generator 525 and the MUX 527. The hash value generator 525 correspondingly generates a hash value based on the data and then passes the hash value to the MUX 527. The multiplexer then supplies the data followed by its hash value to the transmission interface circuit 529 and then to the bus bar structure 55A. The receiver side also includes a receiver interface circuit and a read data buffer 535 plus some additional components. After the read interface circuit 532 obtains the data and the corresponding hash value from the bus 157533.doc -33 - 201225100 550, the multiplex circuit 533 separates the hash value from the data, and sends the read data. To buffer 535 and also to the receiver-side hash value generator 539, the receiver-side hash value generator also generates a hash value based on the (four) set. The hash value produced by the receiver side is then compared to the received hash value in the comparison circuit (4). Looking at the result of the implementation of the decision, it is possible to determine only whether the equivalent matches or further determines the amount of error due to the transfer handler. A data correction engine 537 may also be included in some embodiments to correct for interface errors without having to perform a data retransmission. In the exemplary embodiment, the hash value generators (and the optional material correction engine on the receiver side) are separated from the ECC for NAND core errors, although there may be some overlap in the circuit; In fact, both can be implemented on the same logic circuit of the controller but implemented by different firmware codes. (Although this discussion is considered separate 'but the two error detection/correction sections may be interactive in one of the more general embodiments described below.) Typically, it will be based on all of the information being sent ( User data, corresponding ECC, header information, etc.) produces a hash value 'but in alternative embodiments, may be based on, for example, only a portion of the stripping from each additional item and only the user used to generate the hash value The data itself produces a hash value. Figure 12 also includes a feedback processing unit 560 coupled to receive the output of the hash value comparison circuit 541. This feedback is then analyzed at 561, looking at one or more of the embodiment's consideration of temperature, supply voltage level, and processing related quality of the NAND core. At 563, the feedback process can then be used to adjust the transmission process and correspondingly to either or both of the transmission interface circuits 157533.doc • 34· 201225100 529 and the read interface circuit 531. For a write operation (where the controller is on the transmitter side), after the transfer is sent from the controller to the memory device at -^, the response can only be read back to the The comparison of the generated hash values, and the integrity of the write direction memory interface is determined by the operation. Based on this, the parameters can be written to the interface and the process can be reissued if desired. From the symmetry of the coffee shop, the same operation can be performed on the reading direction of the memory system side of the memory system. Figure 13 is a diagram showing an example of the transmission of data and the resulting hash values via the E-streaming interface. As shown in the item, the corresponding hash value is automatically appended to the data so that they will be transmitted together when the device is operating in this mode. In the second option shown at the bottom, the data payload is transmitted, the receiving side requests the corresponding hash value, and then the corresponding hash value is generated and transmitted. The data payload can have a predefined length or have a random length. If the data payload length is predefined, the hash value can be appended to the profile as in the first option or sent on request. If the data payload length is random, the hash value can be sent after issuing a specific command. For the technique and corresponding circuitry described with respect to Figure 12, a certain number of variations are possible with respect to the hash value engine and A hash value, which can be a parity code (cyclic redundancy check, or CRC), ECC, and the like. For example, § ' can use a "binary" embodiment that will pass back/fail. This embodiment can be built based on the error bit count (CRC) and has the benefit of implementing a low gate count. Alternatively, a "soft" embodiment may return an error bit count (EBC) and (as appropriate) the location of the fault bit, 157533.doc • 35· 201225100 and may be based on, for example, BCH or Solomon code. The ECC code is built to provide more information to help the system make the right decision. The hash value engine visual aspect also has one of the complementary features of the correction interface failure. For example, the second correction is from the flipped bit of the memory core, as represented by the data correction engine 537 of FIG. Based on the feedback from the transmission, (4) the transmission can be repeated. Can be based on binary transfer status or based on the software transfer status < Transfer retry. In addition, the retry can be sent based on a combination of the transfer status and the number of nand bit flips; for example, if the interface introduces N errors and the NAND introduces M errors, and the (4) error correction capability The system and Ρ>Ν+Μ, the system can decide not to retransmit. The system can also be configured in a variety of different ways. The configuration can be symmetrical, with the hash value engines at the controller side and the memory side being identical or asymmetrical. In the -asymmetric configuration, different configurations are used for different transmission directions; for example, a more reliable mechanism can be designed for write transmission for the read transfer setting - faster mechanism. Moreover, it should be noted that even though the interface is symmetrically configured 'because the settings can be changed during the interval between initial writing and subsequent reading of the material', it can act asymmetrically with respect to a given data set. The feedback processing unit 530 can be located differently on the controller 1 , on the memory 200, or both, or between the two. It can also be formed on a separate circuit. In many applications, implementing the feedback processing unit on the controller will be most practical, as the controller circuit often includes more advanced processing capabilities and also because the memory system is often formed from multiple memory chips, but here The technology provided is not so limited. In any of these variations - 157533.doc -36 - 201225100 "Check the data transfer status phase is the responsibility of the feedback processing unit. Further considering an instance in which the feedback processing unit is located on the controller side. In the read direction, after the controller reads the data and the hash value, the device will pass through the feedback mechanism and the controller will determine the pass. / Failed status and the interface settings can be adjusted (or not adjusted) accordingly. Since the controller has read the data and the hash value, the decision state no longer requires further information from the flash memory side, as this can be done in the logic of the controller. In the write direction, the data payload and the corresponding hash value are sent to the memory side and the controller can then operate in several different ways: reading the pass/fail state from the memory side; reading back the hash value and The pass/fail is judged, the error bit count (EBC) is read back from the memory; the EBC and the error position are read back from nand; or the pass/fail status and the corrected number of bits are read from the memory side. The feedback processing unit can decide to modify the interface settings. Phase t, you can modify the following interface settings · · drive strength, bus frequency or other timing parameters; interface relocation, interface mode (for example, from - normal / custom mode to a two-state thixotropic mode) and so on. Then, the adaptive back-to-back method can be used to modify the interface settings due to factors such as process variation, supply voltage level, and temperature affecting the interface error. These factors can also be included as feedback analysis on Figure 12. 561 input. The bus frequency and other parameter settings can be based on earlier transmissions, and the nominal parameter settings can also be set in different ways. For example, a lookup table (LUT) lookup table (LUT) with different values for different busbar capacitance/NAND configurations can also be used with different operational handlers 157533.doc •37-201225100 parameters, provisioning Different values of voltage level, temperature, etc. The processing parameters, supply voltage levels, and temperature can be a variable in a function (formula) rather than as predefined in a LUT. The optimization interface can be set up by operating the interface in the background. Special events such as supply voltage or temperature changes can also be used to trigger the interface setup training task. The interface training task can also use a header mode that spans but not writes to the nand core, such as set forth above with respect to Figure u and path 43. The interface «also can be different and based on the reading direction and the writing direction or based on different materials. The previous discussion primarily considers a memory system to have a controller and a single "hidden device circuit. More generally, the system can include a plurality of memory chips that can be connected to the controller (and the feedback processing unit, if a separate circuit) using a variety of bus topologies. For example, all memory chips can be used in a single system bus; or each memory circuit can have its own controller-memory bus; or various hybrid configurations can be used. Different interface settings can then be applied to the plurality of NAND devices (e.g., if several devices are interfaced, this can be done in parallel). Different interface settings can also be used based on the particular NAND device being accessed, since the interface quality can be a function of the load and/or cell/block quality of a particular NAND device. In addition, different interface settings can be applied to blocks within the NAND core within a given memory device, since the interface quality can be a function of the quality of a particular block. Further details of the techniques of the preceding sections can be found in U.S. Patent Application Serial No. 12/835,292, filed on Jan. 13, 2010. 157533.doc -38- 201225100 Dynamic Optimization of the Backend Memory System Interface This section will further consider the controller-memory (or "backend") interface of the memory system and present it for dynamic optimization. Some methods of reading and writing performance at the end of a high-speed memory system (including a memory system with multiple memory data busses). As discussed above, a memory system is typically designed to have a certain amount of fault tolerance; and although this error can occur in both the controller-memory transfer handler and the actual store handler on the memory 'but traditionally The ECC handler only considers the latter in these situations and typically the backend interface is optimized to eliminate or at least minimize the loss of transmission channel errors. However, in many cases, data errors (including read and write errors) generated by the material processing program can be much lower than the system's ECC capabilities. For example, while a large number of looping devices may require fully available data correction, an unused device may have relatively few errors, thereby providing additional error correction capabilities to the system. This section presents a method by which the memory system internally allocates the non-zero portion of the error correction capacity to the transmission channel. This allows the interface to operate at, for example, higher speeds or lower circuitry, even though this would result in a transmission path error. When the memory segmentation requires a higher error correction amount, the allocation is automatically adjusted. In the complementary aspect, the system can calibrate the transmission path to determine the amount of transmission error formed for different operational parameters and then select the parameters based on the allowed amount. The process considers the back-end interface between the controller and the memory portion. A typical memory system consists of a memory controller and a memory device (such as a NAND flash memory module). The back-end interface is the data bus between the memory and its control benefits. This interface is usually established in one of two ways: 157533.doc .39· 201225100. In the first mode, if the controller and the memory device are discrete components, the back-end interface is established by conductive traces on the printed circuit board (PCB) on which the components are mounted. In the second mode, the controller and the memory may be encapsulated in a single package, such as a system-in-package (SIP) or a multi-chip package (MCP). In this second case, the back end is established by the package substrate. interface. As discussed in the previous section, the overall bit error rate (BER) in a memory system can be attributed to two main factors: data retention reliability in memory devices (such as nand flash memory); Defects in the interface, which can cause transmission errors. An error correction code (E C C) can be used in the memory system to resolve the overall leg. Figure! 4 Schematic map illustrating the cause of a bit error in a memory system. As shown in Figure 14t, the overall bit error rate BER 605 is the primary source of the error. The effect of this error due to data degradation of the stored data (due to charge leakage, interference, etc.) and any errors introduced in the read and write processing program is shown as nand (10). Traditionally, Data correction is only used to account for this factor, which is observed when reading data. An error due to a channel defect is displayed at 603 and the error affects both data reading and writing, but will also be observed at the time of reading. Sources of channel impact errors can include intersymbol interference (isi), crosstalk in the same data bus (in busbar), crosstalk between busbars (for multi-data busbar design), printed circuit board (PCB) noise, and broken die Noise, package noise, and more. The other aspect - ECC 607 can correct errors up to a certain degree of error. 157533.doc •40- 201225100 The data transfer rate between the follower control Is and the § memory is increased, and the backend interface becomes 603 (such as the _ disturbance in the signal in the same data bus (memory data sink) Signal integrity related issues due to inter-row crosstalk and inter-symbol interference (ISI) are more sensitive. In addition, the memory topology (where the controller can access multiple memory devices at the same time (the introduction of multi-memory data bus design causes the back-end interface to suffer from crosstalk in the simultaneous switching of noise and data buss) (memory data bus Inter-crosstalk). In addition to bus speed, factors such as the voltage amplitude and temperature of the data bus (the ambient temperature of the PCB trace and the junction temperature of the system-in-package (SIP) or multi-chip package (MCP)) Affects the signal integrity of the back-end interface. Therefore, the inherent defect of the back-end interface becomes a bottleneck in determining the overall system performance of the Southspeed § Remembrance system. The pin capacitance of the memory device varies with the number of memory dies. The high-capacity memory device constructed with multiple memory dies exhibits high capacitance on its data input/output (I/O), which further degrades the edge rate and signal integrity of the data bus structure. Signal integrity related issues with signal traces can be minimized by increasing the separation of signal traces from each other to minimize crosstalk; however, this method is subject to PCB or substrate Use area limitation. This problem can also be reduced by selecting PCB materials with low dielectric constant and low dissipation factor (loss factor); however, these PCB materials are more expensive than typical materials. Therefore, although there is a reduction in busbars Speed or otherwise degrading the operation bus parameters to reduce some of the methods of this error' but these methods have drawbacks. This section presents these signal integrity issues in the backend interface and is also considered in control. One of the processing changes in the device and the memory device I57533.doc •41 · 201225100 Dynamic optimization technology. In addition to processing program changes, the voltage setting and temperature of the memory system operation can be changed. A static solution does not count And the process 'changes in voltage and temperature, and therefore may not be the best method. This is a pseudo-return method to dynamically optimize the memory system (including the one with multiple delta recall data buss) Memory system) post-end performance. These types of mechanisms similar to those described in previous chapters can be used or by using pre- The data pattern is used for this operation. The exemplary embodiment will use a pseudo-random bit pattern (PRBS). Dynamically optimized data bus settings can help maximize data transfer between the controller and the memory device. Reliability. This allows the memory system to distinguish between transmission errors and errors caused by memory devices. These aspects are especially beneficial for products equipped with a high-speed back-end memory interface and multiple memory data busses. The conductive traces on the substrate have a finite bandwidth, which causes intersymbol interference (ISI). The effect of ISI depends on the edge rate (rise time and fall time), data rate, and data type. In digital communications, sometimes used Pseudo-random bit pattern (PRBS) pattern to explore the worst case of a data link 1 SI influence 'is therefore a type rich in frequency components. A PRBS type line is a repeat pattern' which has a random The nature of the sequence and used to measure the jitter and eye mask of the data transmitted in the electronic data link. The PRBs are typically expressed as 2X-1 PRBS or PRBS_X, where the power (χ) indicates the length of the shift register used to form the pattern. Each 2X-1 PRBS contains every possible combination of X number of bits, except one. It is desirable to actually use the longest PRBS pattern' because it exerts maximum pressure on the signal link and provides a better random data representation 〇 157533.doc -42. 201225100 Although this exemplary embodiment uses a pseudo-random bit pattern, Other types can be used as long as the system knows the type of data set used so that it can be compared to the data returned at the end of the loopback handler. This exemplary embodiment uses the PRBS pattern because of its class-like nature to maximize the ISI impact of the signal link. In addition to the pRBS type, other types of data patterns can be utilized in the present invention, and each individual pattern can produce a different result. A PRBS pattern can be applied to each of the signal links in the parallel backend interface. Although it is ideally indefinitely repeated that the pattern is not practical in a memory system, this should not be an important disadvantage as long as the pattern can be repeated a sufficient number of times by using a short pattern. For example, if the page size of a NAND flash memory is 16 kB, then one of the 127b-type length pRBs_7 patterns can be completely repeated 129 times on each signal link of an 8-bit data bus. The remaining bits (16384b-127bxl29 = lb) constitute an incomplete copy of PRBS-7. This incomplete pRBS pattern should not ultimately make a meaningful thing, as most transmission link effects are factored out in 129 full PRB S-type cycles. Figure 15 can be used to illustrate the operation of a pseudo loopback method in the backend interface. In Fig. 15, the left hand side is a flow, and the right hand side is schematically illustrated to correspond to the controller-memory interaction. At 7 〇 1, the controller turns off its data agitation and error correction coding (ECC) capabilities, where on the right hand side, this is indicated by the "X" of these components. Therefore, all information transmitted to and from the controller is in its original format without any enrollment or correction. At 703, the controller sends a command to the memory device, 157533.doc •43·201225100 v. It will store the data to be received and keep it in its data latch register order without transmitting it to s Recall the body unit. That is, the data set is not programmed into the memory cell. At 705, the controller sends a known data pattern (here an independent p-type) to each of the k-links in the data bus structure to the memory device. The memory device holds the data in the data latch register until it is full. At 707, the controller sends a command to the memory device telling it to continuously send back the data stored in its data latch register until the controller instructs it to stop. That is, after the data latch register has dumped all 16 kb of data on each link, it will start transmitting again back to m. Therefore, the PRBS_7 pattern is repeated on each signal link of the data bus. The reason why the exemplary embodiment uses continuous operation of PRBs type transmission is that the bit error introduced by a signal link is a probabilistic event. The greater the amount of data transmitted across a link, the more accurate and representative the transmission bit error rate (BER) as one of the inherent link performance. At 709, the controller receives the repeating PRBS-7 pattern (or other data pattern used) on each of the signal links of the data bus. At 711, the controller compares the received data with the transmitted data type (here standard PRBS-7 type) and reports any errors as transmission BER. The controller then sends a command to stop the transmission of the PRBS_7 pattern (713) and exit the pseudo loopback mode (715) to the memory device. Figure 16 corresponds to block 705 of Figure 15 in which the controller sends the data pattern to the memory device 'where Figure 17 corresponds to block 7 〇 9. In this two figures, a specific example of a bus bar structure 811 is shown, with a number of command and control signal lines being displayed at the top 157533.doc -44 - 201225100 and a certain number of data lines being displayed at the bottom. Here, CLE = command latch enable, ALE = address latch enable, RE = read enable, WE = write enable, DQS = data strobe, and there are eight input/output lines (100-107). Such a block diagram is simplified for the purposes of this discussion, in which only one ECC block 805 and one PRBS generator 803 are shown on the memory controller 801 and only the data register REG 833 is presented on the memory device 831, Other components (including the non-volatile memory array on the 831) are shown on the unillustrated disc. In Fig. 16, when the controller 801 is transmitting a data pattern across the memory device 83 1 , the write enable signal and the data strobe will be asserted and each signal line will carry the data pattern. Here, each IO line carries a separate pattern. Here, these are all individual copies of the PRBS, but may have different timings as indicated by their relative skew in the figure. On the memory 831, the data pattern is then stored in the register 833 as received. In Figure 17, the data is then sent back from the scratchpad 833 across the busbar structure 811 to the controller 8〇1, and it is now determined that the read enable signal and the data strobe are completed... the data pattern completes the round trip ( Not written to the non-volatile memory) and returned to the controller 801, it can be inspected against its original form and see how much damage has occurred. Although the bus bar structure 81 has a parallel bus bar interface of one of a plurality of signal lines, this is only a special example, and other bus bar structures can be used for (4) transmission channels, such as data configuration. The performance of the memory system is characterized by the data transfer rate (bus operation frequency) relative to power consumption (power consumption is directly related to the data bus voltage). By transmitting the voltage amplitude of the data bus (by the drive data sink I57533.doc •45-201225100 W device: [/〇 judgment) and the data transfer rate change Shimutu handsome crane _ a three-dimensional representation, which transmits The rate axis plots the 'data bus bar' and the data transfer rate at the end of the transfer can refer to the write operation (as in Figure 5 of Figure 5, when the poor material is transferred from the controller circuit to the memory) The data transfer rate is added during the circuit or during the read operation (as in 7〇9, when transferring data from the memory to the controller). The data presented in this Shimut figure can be measured at various output drive impedances (drive strength) and temperature to cover the worst case: typical case, and best case scenario. As a result, for the ": allowable transmission error" can be determined in this data bus voltage, output drive impedance, slew rate, line capacitance, transfer rate, temperature and power consumption - given the combination of parameters Operating point. An example of a Shimut is shown in FIG. Figure 18 is an illustration of one example of a Shimut diagram of a data transfer bus voltage and a data transfer rate for a fixed output drive impedance, slew rate, line capacitance, and temperature for a particular instance of system memory. The data bus voltage is Vdd on the vertical axis, and the transfer rate is drawn horizontally. The amount of transmitted BER is represented by the color on the graph, with the answer on the right side of the graph. In this black and white representation, the representations of very low and very high error quantities appear to be the same, but in the main picture, the lower error area is to the left of the lightly divided area and the higher error area is to the right. Based on such information, a combination of operational parameters can be selected for the amount of data that is allowed to be transmitted, which, as usual, often involves a compromise. For example, if the expected allowable BER is 10·5, if the maximum speed is the primary consideration, then Vdd should be approximately 157533.doc • 46· 201225100 3.1-3.2 V, allowing approximately 170-1 to Mb/ One of the transfer rates. If power consumption is a more important consideration, a lower Vdd value can be used, such as 2·8 V, whereby approximately 15 〇 Mb/Si — the transmission rate will be allowed for approximately the same transmission ber. Word) How many times the memory has been cycled or the ecc indicates that the combined cause of the BER is approaching the maximum capacity of the system, then assign a different value to the BER rewrite assigned to the transmission channel, and then the controller can adjust the operation of the bus system based on this data. parameter. Thus, after calibrating the system by capturing data presented in the smut diagram at various output drive impedances, slew rates, line valleys, temperatures, etc., the memory system can operate according to various scenarios. For example, if a desired transmission BER is known, the memory system finds and selects the optimal data bus voltage, data transfer rate, output drive impedance, and slew rate. (This data from the calibration process can be stored in non-volatile memory or in memory space (RAM) in the controller circuit.) For example, it can choose to form the lowest expected transmission BER. Data bus voltage, final data transfer rate, and minimum output drive impedance. In another example, a specific combination of data bus voltage, data transfer rate, output drive impedance, slew rate, line capacitance, and temperature is known, and the memory system knows what it can expect to transmit BER » another selection system, memory The body system can choose to balance all factors—data bus voltage, data transfer rate, output drive strength, and one of the operating conditions of the transmitted BER. Since the design of the I/O buffer in the controller and the memory device can be different, the optimal reading performance and writing efficiency of the memory system can be determined separately. In addition to the differences made by the design of the memory system, the individual instances of the same package will vary due to process variations and operating conditions. The calibration process can also be repeated to account for aging of the device, changes in operating conditions, and the like. For example, an initial calibration can be performed at the time of testing prior to shipping the device, and then the controller can recalibrate the system periodically or in response to events such as device cycling, erroneous results, significant changes in operating conditions, and the like. Thus, in addition to changing the proportion of the total error assigned to the transmission channel, the corresponding operational parameters for a given allocation can be dynamically changed. As mentioned above, performance can be optimized during both the read process and the write process" back to Figure 15, for performance optimization during memory read, at 705, the system slows down The transfer rate of the data pattern being written to the data latch register of the memory device to maximize the integrity of the transfer of the data pattern. For example, at a 丨0 MHz transfer rate, filling the 16 kb data latch register will take U ms. At 7〇9 and 7Π, the system measures the transmission Ber incurred during the read operation, where the I/O system of the memory device is 'and the controller is the receiver. The Shimtu data then shows the relationship between the I/O voltage of the memory device and the read frequency. For performance optimization during memory writes, at 7〇5, the system changes the voltage and transfer rate of the data pattern being written to the data latch register of the δ memory device. At 709, the system will then slow down the transfer rate of data from the memory device to the controller to prevent additional bit errors from being injected by the signal link. The measured transmission BER is thus the BER incurred during the write operation in 705. Therefore, the Shimtu data will represent the relationship between the controller's I/O voltage and the write frequency. 157533.doc • 48· 201225100 The various aspects presented here are presented in the background of one of the single busbars between a controller circuit and a soap circuit. The '-memory system, the system can include multiple devices with various busbar topologies; and when there are multiple busbars, the interaction between such busbars can result in additional sources of error. The techniques herein can provide the ability to skew each of the signal links within one of the data busses in the backend interface to a particular resolution, for example, 1 〇〇 pS. This skewing capability can be introduced into the driver or receiver by the controller or S-resonance device. Introducing skew into the data bus allows the system to compensate for the mismatch in the length of the signal traces in the P C B or package substrate. Introducing skew can reduce the effects of near-end and far-end crosstalk in the back-end interface, and thus reduce the transmission BER. There are two types of crosstalk: crosstalk in the memory data bus; and crosstalk between the memory data bus. This _ disturbance causes jitter in the data bus. A typical memory system uses the clock transmitted by the driver to sample each individual signal in a parallel data bus. Therefore, an increase in the jitter of each signal in the data bus will result in an increase in the transmission BER. Crosstalk between memory data busses can be reduced by skewing data across multiple memory data busses so that they are not aligned with one another. Figure 19 is a block diagram illustrating one of the crosstalk in a memory system in which the bus bar structure uses a plurality of memory data sinks. The memory system includes a controller 901 and a plurality of (here four) memory devices 931-1 connected to the controller by individual bus bars 91-1, 911-2, 911-3, 911-4 , 931-2, 932-3, 934-4. For each of the bus bars 911, it will have one or more 10 lines ' as shown in detail from ιοί to IOX. As with the previous 157533.doc -49-201225100, these individual busbars can vary the number of 10 lines used to transmit data in parallel, in tandem, or in combination with one of them. Such a multi-bus arrangement is often implemented in an SSD-type device (see, for example, U.S. Patent No. 7,376,034, U.S. Patent No. 7,765,339, or issued to et al., entitled "Eight Performance Controller for NAND Flash-based Solid State Disk (NSSD) (Samsung, 2006 Non-Volatile Semiconductor Symposium, IEEE, NVSMW 2006, Volume 21, pages 17 to 20, February 12-16, 2006)) to improve performance, but can also be found in Some memory cards and other memory systems are designed. In addition to the crosstalk in this type of memory data bus between the 1 line of a given bus, there will now be crosstalk signals between the memory data bus rows on different bus bars. When combined with the use of the PRBS pattern and the pseudo loopback mode described above, a specific combination of data bus voltage, transmission rate, temperature, output drive impedance, slew rate, line capacitance, and power consumption is given. The least skew is generated and thus the best skew of the lowest transmission BER is produced. The various aspects presented herein provide a low cost solution to optimize back end interface performance in the presence of various signal integrity issues. By dynamically assigning "unused" ECC capabilities to the transfer handler, performance can be improved as explained. As mentioned above, some memory systems use a type of "strong" Ecc that explores the nature of a multi-state memory device, in which case the error correction capability transmitted for the transmission channel may not be transmitted as uti. . It should also be noted that although the memory system incorporates Ecc to compensate for data errors, there is usually no such requirement for commands, and memory devices will often not accept corrupted commands, and therefore compete in data transmission 157533.doc • 50·201225100: Error 'But the order will not be a mechanism such as the system can be used to wash the data iie ^, though, 'by this: allows a higher transfer rate for the asset, but can be incorporated into a comparison <Transfer rate (or other parameter) setting so as not to cause an error for the control k. The foregoing description of the present invention has been presented for purposes of illustration and description, and the embodiments of the invention And variations of the centroids (10) are selected to best explain the principles of the invention and its practical application, thereby enabling those skilled in the art to make various modifications in various embodiments and suitable for the particular use contemplated. The invention is best utilized, and the scope of the invention is intended to be defined by the scope of the appended claims. FIG. 1 is a schematic illustration of a main memory system suitable for implementing one of the present inventions. Hardware components. Figure 2 schematically illustrates a non-volatile memory cell. Figure 3 illustrates source-drainage of four different charges Q1 to Q4 that can be selectively stored at any one time for a floating gate. The relationship between the current iD and the control gate voltage VCG. Figure 4A schematically illustrates a memory cell sequence organized into a NAND string. Figure 4B illustrates the The NAND string 50 shown in Figure 4A constitutes one example of a NAND memory cell array 210. I57533.doc -51· 201225100 Figure 5 illustrates the parallel sensing or stylization of the organization as (for example) NAND configuration One memory cell page. Figures 6(0) through 6(2) illustrate an example of a stylized 4-state memory cell population. Figures 7A-7E illustrate encoding with a given 2-bit code. 4 Stylization and reading of state memory Figure 8 illustrates a memory managed by a memory manager that resides in one of the software components of the controller. Figure 9 illustrates the back end The software module of the system. Figure 10A(i) to Figure 10A(iii) schematically illustrate the mapping between a logical group and a metablock. Figure 10B schematically illustrates the logical group and the metablock. Figure 11 is a block diagram showing one of the feedback mechanisms for determining interface integrity based on an existing infrastructure. Figure 12 is a diagram illustrating the implementation of the feedback mechanism using a hash value engine to determine interface integrity. One of the block diagrams of the example. An illustration of one of the examples of the interface transfer data and the resulting hash value. Figure 14 is a schematic illustration of the cause of a bit error in a memory system. Figure 15 can be used to illustrate one of the back-end interfaces. Figure 16 and Figure 17 respectively correspond to blocks 7〇5 and 7〇9 of Figure 15. Figure 18 shows one of the transmission BER vs. data bus voltage and data transfer rate 157533.doc -52· 201225100 An example of a smut diagram. Figure 19 is a block diagram illustrating one of the crosstalks in a bus memory system using a plurality of memory data busses. [Main component symbol description] 10 Memory cell 14 source Pole 16 Pole 20 Charge Storage Unit 30 Control Gate 32 Control Gate 34 Source Line 36 Bit Line 42 Word Line 44 Select Line 50 NAND String 54 汲 Extreme 5 Source Terminal 60 Page 80 Host 90 Memory System 100 Controller 110 Interface 120 Processor 121 Optional Coprocessor 157533.doc -53- Read Only Memory Programmable Nonvolatile Memory Random Access Memory Memory Memory Array Sensing Bulk latch memory manager front-end system host interface back-end system media management layer data stream and sequencing layer command sequencer low-order sequencer flash control layer element block logic group bus line structure special integrated body Circuit Core Error Correction Code Circuit Output Buffer Transmission Circuit Input Buffer -54 - 201225100 427 Receive Circuit 431 Receive Circuit 433 Input Data Buffer 435 NAND Core 441 Transfer Circuit 443 Output Data Buffer 520 Transmitter Side 521 Write Data Buffer 525 scatter value generator 527 multiplexer 529 transmission interface circuit 530 receiver side 531 read interface circuit 533 multiplexer circuit 539 receiver side hash value generator 541 comparison circuit 550 bus bar structure 560 feedback processing unit 561 Feedback Analysis 801 Memory Controller 803 Pseudo Random Bit Pattern Generator 805 Error Correction Code 811 Bus Bar Structure 831 Memory Device 833 Register 157533.doc -55- 201225100 901 Controller 911-1 Bus 911-2 Busbar 913-1 Busbar 911-4 Busbar 931-1 Memory Device 931-2 Memory device 931-3 Memory device 931-4 Memory device ALE Address latch enable BL bit line CLE Command latch Enable DQS data strobe 10 Input/output LG Logical group Ml Memory M2 Memory MB Block Mn Memory RE Read Enable SI Select Transistor S2 Select Transistor WE Write Enable WL Word Line 157533.doc -56-

Claims (1)

201225100 VII. Patent Application Range: 1. A method for operating a non-volatile memory system, the non-volatile memory system comprising a controller circuit having a memory interface, having a non-volatile memory cell array and a a memory circuit of the controller interface and the memory interface connected to the 4 control n circuit and the controller interface of the memory circuit for the transfer of data and commands therebetween - a bus bar structure The memory system can tolerate the 帛-non-zero cumulative error amount when performing the 'down operation: transferring data from the controller to write to the § memory array until after reading back from the memory array The method of receiving, by the controller, the method includes: using the controller circuit, the first non-zero portion of the first error amount is configured by the bus bar structure in the controller circuit and the memory The transmission of the data between the circuits, the remainder of the first error amount is assigned to the writer, storage, and storage of the data on the memory circuit; The first error portion of the memory circuit is configured by the controller circuit to set the transfer characteristics of the controller circuit and the gate to operate to allow for maximum division. 2. The method of claim 1, i - station oil ^ ^ wherein the transmission characteristics include the voltage amplitude of the bus structure. 3. In the case of the request item, 1 ^ ^ ', A, the transmission characteristics include the data transfer rate on the bus structure. 4. As in the case of claim 1, the transmission characteristics include a signal driven strong 157533.doc 201225100 degrees. The method of item 1 wherein the transmission characteristics include a signal conversion rate. 6. The method of claim 1, wherein the memory system comprises an error correction code (ECC) circuit and the first error amount is based on the capabilities of the ECC circuit. 7. The method of claim 6, wherein the ECC circuit is on the controller circuit. 8. The method of claim 6, the method further comprising: receiving the data from a host at the controller circuit; generating a corresponding ECC code for the data; based on the transfer characteristics, the bus structure The data and corresponding horses are transferred from the controller circuit to the memory circuit; and/or will be there. The data and corresponding code received by the memory circuit are written into the memory cell array. 9. The method of claim 1, further comprising: subsequently, by the controller circuit, the second portion of the first error amount = the new knife is assigned to the red by the bus structure in the controller circuit and the memory The transmission of the data between the circuits; and the special transfer characteristic between the control controller circuit and the memory circuit by the controller circuit is set to μ 忭 to allow up to the second error section. 10. The method of claim 9, wherein the circuit is programmed to re-allocate the error portion from the 157533.doc 201225100 to the first number in response to the memory. Two quantities. 11. The method of claim 9, wherein the controller circuit reassigns the error portion from the first amount to the second in response to an error amount detected in the data read back from the memory array the amount. 12. The method of claim 1, wherein the memory system maintains a value of one or more operational parameters of the busbar structure and the 'between the controller circuit and the memory circuit via the busbar structure Correspondence between the resulting error amounts of the transmission of the data, wherein setting the transmission characteristics comprises: selecting, by the controller circuit, the value of the one or more operational parameters based on the correspondence. The method of month length item 12, whose correspondence is for a plurality of operations &gt; number ' and selecting the value of the plurality of operation parameters includes allowing up to the first error portion according to one or more == A selection is made between a plurality of combinations of the plurality of parameters. 14. 15. The method of claim 13 wherein the voltage amplitude and the method of claim 13 are used. The operational parameters in the ', include the data transfer rate on the busbar bus structure. Wherein the operational parameters include a signal driving strength. 16. The method of claim 13 wherein the towel operating parameter comprises a signal conversion speed. 17. The method of claim 12, wherein the step comprises the value of The correspondence is established by selecting the one or more operating parameter controller circuits by the control. 18. The method of claim 17, wherein the establishing the correspondence comprises: 157533.doc 201225100 for each of the values of the operational parameters, a known data pattern is self-contained via the bus structure The controller circuit transmits to the memory circuit and transmits the data back without writing the data into the non-volatile memory cell array, and compares the data received at the controller circuit with The type of material sent. 19. The method of claim 17, wherein the memory system comprises a plurality of memory circuits, and the bus bar structure comprises a plurality of bus bars, whereby each of the memory circuits is individually connected to the a controller circuit, and wherein establishing the correspondence by the controller circuit comprises determining a crosstalk error between the bus bars. 20. - Operation - Non-volatile memory system method, (4) Volatile memory system with a controller circuit and sentence _ non-broadcast TL 命 峪 峪 峪 峪 峪 之一 之一 § § § § The memory circuit, the method comprising: by the controller circuit by using a plurality of values for each of one or more operational parameters connecting the controller to one of the bus circuits of the memory circuit Each execution-processing program-executing-transmission error calibration, the processing program comprising: one of the known data patterns via the transmission circuit on the controller - the data set is transferred from the controller to the bus structure; The bus bar structure receives the data set via a receiving circuit on the circuit, and stores the received data set in a buffer memory on the memory circuit; via the memory circuit The value of 钤帝朴, the transmission circuit will be stored in the buffer memory of the memory 157533.doc 201225100 on the road and the collection not written to the array is transferred to the bus structure 〆 Receiving a circuit from the busbar structure to receive the data set via the controller; the data set received by the stub is compared with one of the known patterns; and - based on the comparison, the operating parameters for the use Determining an amount of error associated with the transfer handler; and subsequently #serving the memory system to allow a first non-zero error amount in data transfer between the controller circuit and the memory circuit, wherein the controller circuit The values of the operational parameters are selected in accordance with the transmission error calibration process based on the determined associated error amount. The method of claim 20, wherein the operational parameters comprise voltage amplitudes of the busbar structure. 22. The method of claim 20, wherein the operational parameters include a data transfer rate on the bus structure. 23. The method of claim 20, wherein the operational parameters include signal driving strengths. 0. 24. The method of claim 20, wherein the operational parameters comprise signal conversion rates. 25. The method of claim 20, further comprising: subsequently operating the memory system to allow a second error amount in the data transfer between the controller circuit and the memory circuit, wherein the controller circuit is based The determined error amount determined by the decision is based on the transmission error calibration process to select values of the operational parameters. 157533.doc 201225100 26. The method of claim 20, further comprising subsequently re-executing the transmission error calibration process. 27. If the method of claim 20 is ^', where _ line the transmission error calibration process :::... the memory system stores the transmission error calibration process... in non-volatile memory. An α 28. :=Γ method, wherein the transmission error is performed for a plurality of operational parameters and the controller circuit is capable of allowing the plurality of operational parameters up to the first-error amount according to a plurality of job performance criteria Pick between the combinations. 29. The method of claim 2, wherein the memory system comprises a plurality of memory circuits ' and the bus bar structure comprises a plurality of bus bars, whereby the same. Each of the circuits is connected to the controller circuit individually, and the data set in which a known data pattern is transmitted includes information for determining a crosstalk error between the bus lines. 30. A non-volatile memory system, comprising: a controller circuit including a memory interface and logic circuit; a memory circuit including a non-volatile memory cell array, a controller interface, and logic a bus structure </ RTI> connected to the memory interface of the controller circuit and the controller interface of the memory circuit for transmission of data and commands therebetween; and a feedback processing circuit Connecting to the controller and the receiver of the memory circuit during a data transfer between the controller and the memory circuit to receive an error regarding the transfer 157533.doc 201225100 Information, and connected to one or both of the memory interface and the controller interface to adjust the characteristics of the transfer between them in response to the amount of error. 3. The non-volatile memory system of claim 30, wherein the data transfer is from the controller circuit to the memory circuit. 32. The non-volatile memory system of claim 30, wherein the data transfer is from a remote circuit to the controller circuit. 33. The non-volatile memory system of claim 30, wherein the logic circuit of each of the controller and the memory circuit comprises a hash value generator, wherein the memory circuit and the control In the transmission processing program of the first one of the devices to the second one of the devices, the first one transmits a data set via the bus structure and the first one generated from the data set by the logic circuit of the first one a hash value, and the second one receives the data set and the first hash value from the bus structure and generates, by the logic circuit of the second one, the one of the data sets from the received data set a second hash value, and wherein the logic circuit of the memory circuit and the second one of the controllers further comprises a comparison circuit 'the comparison circuit is coupled to receive the received first hash value and the The second hash value and one of its comparisons is made 'this error amount is based on the result of the comparison. 34. The non-volatile memory system of claim 33, wherein the memory circuit is equivalent to the circuitry used to generate the respective hash values on the control ||. 157533.doc 201225100 35. 36. 37. 38. 39. 40. 41. 42. 43. The non-volatile memory (four) system of claim 33, wherein the memory circuit is used with the controller for generating the Such circuits, such as individual hash values, are not equivalent. Wherein the comparison determines the 'and in response to determining the non-volatile memory system as claimed in claim 30, whether the first hash value is equal to the second hash value, the first value is not equal to the second value' The logic circuit of the second circuit of the body circuit and the controller further quantizes the amount of error. The non-volatile memory system of claim 30, wherein the feedback processing circuit is formed on the same integrated circuit as the controller. The non-volatile memory system of claim 30, wherein the feedback processing circuit is formed on the same integrated circuit as the memory circuit. The non-volatile memory system of claim 30, wherein the feedback processing circuit is formed on an integrated circuit separate from both the controller and the memory circuit. The non-volatile memory system of claim 30, wherein the memory circuit is formed by a plurality of integrated circuits, each integrated circuit comprising a non-volatile memory cell array, a controller interface, and a logic circuit. The non-volatile memory system of claim 40, wherein each integrated circuit of the memory circuit is coupled to the controller by a different bus bar. A non-volatile memory system as claimed in claim 40, wherein one or more of the integrated circuits of the memory circuit are coupled to the controller by a common bus. The transmission of the non-volatile memory system of claim 40, wherein the controller and the plurality of integrated circuits of the memory circuit are 157533.doc 201225100, can be independently adjusted. 44. A method of operating a non-volatile memory system, the non-volatile memory system comprising a controller circuit and a non-volatile memory circuit, the method comprising: the controller circuit and the memory circuit - ^ ^ τ ^ the logic circuit on the first one causes a first hash value to be generated from a data set; the data set and the one via the controller circuit and one of the first ones in the memory circuit Transmitting, by the controller circuit and one of the second one of the memory circuits, the data set and the first hash value from the bus line structure; Generating a second hash value from the received data set in the logic circuit on the second of the controller circuit and the memory circuit; the first in the controller circuit and the memory circuit Comparing the received first hash value with the second hash value; and receiving the first based on the controller circuit and the logic circuit pair on the second one of the memory circuits Comparing the hash value with the X of the second hash value determines whether the characteristics of the data transfer between the controller circuit and the memory circuit are changed. The method of claim 44, wherein the controller circuit and the first one of the memory circuits are the controller circuit. 46. The method of claim 44 wherein the controller circuit and the first one of the memory circuits are the memory circuits. The method of claim 44 is equivalent to the logic circuitry on the memory circuit for generating the respective hash values on the controller 157533.doc 201225100. 48. The method of claim 44, wherein the logic circuits on the memory circuit are not equivalent to the logic circuits on the controller for generating the respective hash values. 49. The method of claim 44, wherein the characteristics of the data transfer between the controller circuit and the memory circuit comprise transmitting a frequency of the data. 50. The method of claim 44, wherein the characteristic of the data transfer between the controller circuit and the memory circuit comprises a clock frequency of the bus structure. The method of claim 44, wherein the characteristics of the data transfer between the controller circuit and the memory circuit comprise a slew rate used in the transfer. 52. The method of claim 44, wherein the characteristic of the data transfer between the controller circuit and the memory circuit comprises transmitting a data interface. The method of claim 44, wherein the controller circuit The characteristics of the data transfer with the memory circuit include the drive strength of the transfer material. Cyclic Redundancy Error Correction 54. The method of claim 44, wherein the hash values are based on an inspection. 55. The method of claim 44, wherein the hash values are based on a code. And the memory data set and the method of claim 44, wherein before the 157533.doc •10·201225100 hash value is transmitted via the interface on the first one of the control body circuits The material characteristics of the data transfer are set to determine one of the initial value sets from a lookup table based on the bus structure of the memory system and the characteristics of the memory circuit. 57. The method of claim 44, wherein the data is transmitted before the data set and the first hash value are transmitted via the controller circuit and the interface on the first one of the memory circuits The characteristics are set to determine one of the initial value sets from a lookup table based on one or more parameters. 58. The method of claim 44, wherein the data set is transmitted by transmitting the data set and the first hash value via the interface of the controller circuit and the first one of the memory circuits The characteristics are set to determine an initial set of values from the quality of a prior data transfer between the controller circuit and the memory port circuit. 59. The method of claim 58, wherein the one or more parameters comprise a supply voltage level. 60. The method of claim 58, wherein the one or more parameters comprise a temperature. 61. The method of claim 58, wherein the one or more parameters comprise processing values of one or both of the controller circuit and the memory circuit. 62. The method of claim 44, wherein the generating and transmitting of the first hash value is returned to the request from the controller circuit and the memory circuit. 63. The method of claim 44, further comprising: changing the characteristics of the data transfer between the controller circuit and the memory circuit at 4, wherein the change is related to the controller Circuit JL transfers the memory circuit and the transfer from the memory circuit to the 157533.doc 201225100 controller circuit symmetrically. 64. The method of claim 44, further comprising: responsive to the determining, changing the characteristics of the data transfer between the controller circuit and the memory circuit, wherein the change is from the controller circuit to The transfer of the memory circuit and the transfer from the memory circuit to the controller circuit are performed asymmetrically. 65. A method of operating a non-volatile memory system, the non-volatile memory system having a controller circuit and a circuit comprising a non-volatile memory cell array, the method comprising: The transmission circuit on the controller transmits a data set from the buffer memory on the controller to the bus bar structure connecting the controller to the memory circuit; the receiving circuit on the memory circuit is from the bus bar The structure receives the data set; stores the received data set in a buffer memory on the memory circuit; and stores the data stored in the memory circuit on the memory circuit through the transfer circuit on the memory circuit; The data set written to the array is transferred to the bus structure; the data set is received from the bus structure via a receiving circuit on the controller; and the received data set is then stored on the controller In the buffer memory; then based on the data set received and stored on the controller in the buffer memory 157533.doc ^ 201225100 Error characteristics of the transmission of the adjustment amount of data between the control circuit and the memory circuit. 66. The method of claim 65, wherein the error amount is determined by an ECC circuit on the controller. 157533.doc •13-