TWI498893B - MLC memory write method in multiple environments - Google Patents

Description

Writing method of MLC memory in multiple environments

The invention relates to a method for writing MLC memory, which refers to a method for seamlessly writing MLC memory in multiple environments to improve writing speed.

The flash memory can be roughly divided into a single-stage storage unit (SLC), a multi-level storage unit (MLC), and a third-order storage unit (TLC), wherein the single-stage storage unit (SLC) has low power consumption and fast transmission speed. Long life, etc., while multi-level memory cells (MLC) can store more than 2 data bits in each storage unit, so the capacity is large and the cost is low, but the transmission speed is slower than the single-stage storage unit (SLC). Higher power consumption and shorter life of the storage unit. The third-order storage unit (TLC) has a slower transmission speed than the single-stage storage unit (SLC) and multi-level storage unit (MLC), and its lifetime is relatively short.

According to the above characteristics, the flash memory of the multi-level memory cell (MLC) (hereinafter referred to as MLC memory) has the advantage of the above three, and if the basic characteristics are improved, the application of the MLC memory can be effectively improved. value.

Regarding the application of MLC memory, the emphasis is mainly on the increase of the amount of stored data, so it is very common to have a plurality of MLC memories in a storage device. Please refer to FIG. 3, which is a schematic structural diagram of a storage device, which includes a controller 80 and a plurality of MLC memories 81-84. Take the MLC memory 81~84 as an example. Due to the structural particularity of the MLC memory, the controller 80 transmits and writes the data in two stages, that is, it is divided into the front segment transmission, the front segment write and the back segment transmission, and the latter segment write, because each MLC memory Since the writing of the volume is performed in accordance with the above mode, the writing of each of the MLC memories 81 to 84 is performed in an interleaved manner in the environment of a plurality of MLC memories.

For the above-mentioned interleaved write, please refer to FIG. 4, which discloses the data transmission and write timing of each MLC memory 81-84. First, the first MLC memory 81 performs the pre-transmission and the pre-segment write, which is sufficient. By using the channel, the first MLC memory 81 is not subsequently subjected to the subsequent segment transmission and the subsequent segment writing, but the other MLC memories 82-84 are sequentially transmitted in the previous segment and the previous segment is written, and the last MLC is waited for. After the transmission of the front portion of the memory 84 is completed, the first MLC memory 81 is then subjected to the subsequent segment transmission and the subsequent segment writing, and the second segment of the MLC memory 82 is transmitted to the subsequent segment and the subsequent segment is written in the first MLC memory. After the subsequent segment transmission of 81, the latter segment transmission and the subsequent segment writing of the third MLC memory 83 are connected to the latter segment of the second MLC memory 82, and the subsequent segment transmission and the subsequent segment writing of the fourth MLC memory 84 are This is followed by the subsequent transmission of the third MLC memory 83.

Although the foregoing method can interleave the data into the MLC memories 81-84 one by one, it can be clearly seen from FIG. 4 that each MLC memory 81-84 is transmitted in the front segment, the previous segment is written, and the subsequent segment is transmitted. There is an idle time T _idle between the subsequent writes. When the amount of data written is larger, the idle idle time is longer. In other words, the overall write efficiency is still not fully utilized.

It can be seen from the above that in the MLC memory, the writing time of each MLC memory still has idle time in multiple environments. When the amount of data written is larger, the idle idle time is longer, so that the overall writing speed is still not As expected, it is subject to further review and seeking a viable solution.

Therefore, the main object of the present invention is to provide a method for writing MLC memory in multiple environments, which can perform seamless writing on each MLC memory in multiple environments to further improve the overall writing speed.

The main technical means adopted to achieve the above objectives is that the above method mainly divides a plurality of MLC memories into two or more memory groups, and each memory group is composed of two MLC memories, and when writing is performed, The following steps are performed in groups: first, the first MLC memory of a memory module is successively subjected to the previous segment transmission, the previous segment write and the subsequent segment transmission, and the subsequent segment write; the transmission is completed in the front segment of the first MLC memory. When the second MLC memory of the memory group is successively subjected to the previous segment transmission, the previous segment write and the subsequent segment transmission, and the subsequent segment write; when the second MLC memory of the memory group completes the latter segment transmission, then The first step and the second MLC memory of the other memory group repeat the above steps; since the foregoing method groups the plurality of MLC memories, and groups the units, and writes a memory module first. The first MLC memory is continuously transmitted and written, and when the first MLC memory is successfully transmitted, the second MLC memory of the memory group is continuously transmitted and written; when the memory Group's second MLC Recalling completed body section In the transmission, the above steps are repeated for the first and second MLC memories of another memory group; by using the above method, the front segment transmission, the front segment writing and the back segment of each MLC memory of each memory group can be effectively eliminated. The idle time between transmission and post-write is realized without seams. Even if the amount of data written is large, the overall write speed will not be affected because the idle time is too long.

10‧‧‧First memory group

11, 21‧‧‧ First MLC memory

20‧‧‧Second memory group

12,22‧‧‧Second MLC memory

30‧‧‧ Controller

80‧‧‧ controller

81~84‧‧‧MLC memory

Figure 1 is a schematic view showing the structure of a storage device of the present invention.

2 is a schematic diagram of a write flow of the present invention.

Figure 3 is a schematic view of the structure of an existing storage device.

Figure 4 is a schematic diagram of the writing process of the existing storage device.

In a preferred embodiment of the present invention, a plurality of MLC memories are mainly divided into two or more memory groups, and each memory group is composed of two MLC memories, as shown in FIG. For convenience of description, in the present embodiment, four MLC memories 11, 12, 21, and 22 are divided into two memory groups as an example. Hereinafter, the two memory groups are referred to as the first. The memory group 10 and the second memory module 20, the MLC memories 11, 12, 21, 22 of the first and second memory groups 10, 20 are electrically connected to a controller 30, respectively, by a controller 30 performs transfer writing to each of the MLC memories 11, 12, 21, and 22, respectively. It should be noted that the number of the foregoing memory groups is only an example, and is not intended to limit the number of memory groups.

When the controller 30 transmits and writes the first memory group 10 and the second memory module 20, the following steps are performed in units of groups. Step (refer to FIG. 2): performing a front segment transmission and a front segment writing on the first MLC memory 11 in the first memory group 10; when the front segment transmission of the first MLC memory 11 is completed, The second MLC memory 12 in the first memory group 10 performs front-end transmission and front-end writing; since each storage unit of the MLC memory can store two data bits, the writing is divided into two segments. Because it is difficult to judge when writing the second data bit, the writing of the second data bit takes a long time. When the first data bit is written, the previous segment is transmitted for about 0.2 ms, and the previous segment is written. The input is about 0.4ms (total is 0.6ms), and when the second data bit is written, the latter segment is about 0.2ms, but the latter segment is written for 2ms (total 2.2ms). As can be seen from FIG. 2, in a single channel, after the first MLC memory 11 of the first memory group 10 completes the previous segment transmission, the second MLC memory 12 performs the previous segment transmission, and the first MLC memory at this time. 11 is also about to complete the previous segment write, the second MLC memory 12 is also in the front segment transmission when the subsequent segment transfer and the subsequent segment write are performed, and the second MLC memory 12 is also just after the first MLC memory 11 is completed. At the same time, the previous segment is written, and the subsequent segment transmission and the subsequent segment writing are successively performed.

Under the foregoing arrangement, the first and second MLC memories 11, 12 of the first memory group 10 perform the front-end transmission/write and the back-end transmission/write without seams without idle time therebetween.

When the second MLC memory 12 of the first memory group 10 completes the subsequent transmission, the first and second MLC memories 21 and 22 of the second memory group 20 can be transferred and written. As above The manner in which the first memory group 10 is written.

Performing pre-transmission and pre-segment writing on the first MLC memory 21 of the second memory group 20; performing pre-transmission and pre-decoding on the second MLC memory 22 when the pre-transmission of the first MLC memory 21 is completed. Similarly, after the front segment transmission of the second MLC memory 22 is followed by the previous segment transmission of the first MLC memory 21, the previous segment write of the second MLC memory 22 is completed simultaneously with the subsequent segment transmission of the first MLC memory 21.

In the foregoing process, the first and second MLC memories 21, 22 of the second memory group 20 still perform front-end transmission/write and back-end transmission/writing without seams.

It must be noted that the foregoing method also has some waiting time before the second memory group 20 starts to transmit writes, but only exists before the start of the transfer write, once the transfer write is started, due to the front part of each MLC memory. Transmission/writing and post-transmission/writing are seamless connections. The longer the amount of data, the longer the idle time saved, and the shorter the write time, the overall write speed can be effectively improved.

It will be understood by those having ordinary skill in the art that the number of the aforementioned memory modules can be expanded as needed, and the above method can still be applied to improve the overall writing speed. For example, if there are four memory groups, the writing process of the first and second memory groups is as described above, and the writing process for the third and fourth memory groups is as follows. : Mainly after the second memory group completes the post-transmission, the first MLC memory of the third memory module is successively subjected to the pre-transmission, the pre-description and the subsequent transmission, and the subsequent-segment writing; in the first MLC memory When the front segment transmission is completed, the second MLC memory is successively subjected to the front segment Transmission, pre-write and post-transmission, post-segment write; when the second MLC memory of the third memory group completes the post-transmission, then repeats the above for the first and second MLC memories of the fourth memory group step. That is, each memory group has the same transmission and writing manner to the first and second MLC memories, and the latter memory module is transmitted after the second MLC memory of the previous memory module is completed. After the transfer/write is started.

It can be seen from the above that the method of the present invention can effectively eliminate the idle time between the front segment transmission, the front segment write and the back segment transmission, and the subsequent segment write of each MLC memory of each memory group, thereby achieving seamless writing. The larger the amount of data bits written, the longer the idle time saved, and the higher the overall write speed.

11, 21‧‧‧ First MLC memory

12,22‧‧‧Second MLC memory

Claims (5)

A method for writing MLC memory in multiple environments, mainly dividing a plurality of MLC memories into two or more memory groups, each memory group being composed of two MLC memories, performing writing When the group is the unit, the following steps are performed: first, the first MLC memory of the memory module is successively subjected to the previous segment transmission, the previous segment write and the subsequent segment transmission, and the subsequent segment write; and the first MLC memory is transmitted in the front segment. Upon completion, the second MLC memory of the memory group is successively subjected to pre-transmission, pre-description and post-transmission, and subsequent-stage writing; when the second MLC memory of the memory group completes the subsequent transmission, then The above steps are repeated for the first and second MLC memories of another memory group. The method for writing an MLC memory in a plurality of environments according to claim 1, comprising a first memory group and a second memory group, wherein the writing is performed by performing the following steps: for the first memory The first MLC memory in the group performs a front segment transmission and a previous segment write; when the first segment transmission of the first MLC memory is completed, the front segment transmission and the previous segment write are performed on the second MLC memory in the first memory group. After the writing of the first segment of the first MLC memory is completed, a subsequent segment transmission and a subsequent segment writing are performed on the first MLC memory; when the subsequent segment transmission of the first MLC memory is completed, the second MLC memory is performed. After transmission and subsequent write; after the second segment of the second MLC memory is completed, the second memory The first and second MLC memories in the group perform the above steps. As described in claim 2, the MLC memory is written in a plurality of environments. When the first MLC memory of the first memory group completes the subsequent segment transmission, the second MLC memory simultaneously completes the previous segment write. The method for writing the MLC memory in multiple environments as described in claim 2 or 3, further comprising a third memory group and a fourth memory group, and performing the latter transmission in the second memory group After the following steps are performed: the first MLC memory of the third memory module is successively subjected to the front segment transmission, the front segment write and the back segment transmission, and the subsequent segment write; when the first MLC memory is transmitted in the front segment, the third memory is The second MLC memory of the body group successively performs front segment transmission, front segment write and back segment transmission, and subsequent segment write; when the second MLC memory of the third memory group completes the latter segment transmission, then the fourth memory is performed The above steps are repeated for the first and second MLC memories of the group. The writing method of the MLC memory in the multiple environment as described in claim 4, when writing the third and fourth memory groups, performs the following steps: the first MLC memory in the third memory group Performing a front-end transmission and a front-end writing; performing the front-end transmission and the front-end writing on the second MLC memory in the third memory group when the first-stage transmission of the first MLC memory is completed; in the first MLC memory After the writing of the preceding segment is completed, a subsequent segment transfer and a subsequent segment write are performed on the first MLC memory; when the subsequent segment transfer of the first MLC memory is completed, the second MLC memory is subjected to the subsequent segment transfer and the subsequent segment write; After the subsequent transmission of the second MLC memory is completed, the above steps are performed on the first and second MLC memories in the fourth memory group.