KR20150037517A - Rram cell structure with laterally offset beva/teva - Google Patents

Abstract

The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the formation voltage and improve data retention.

Description

[0001] RRAM CELL STRUCTURE WITH LATERALLY OFFSET BEVA / TEVA [0002] BACKGROUND OF THE INVENTION [0003]

The present disclosure relates to a resistive random access memory (RRAM) device and a method of manufacturing the same.

Non-volatile memories are used in a wide variety of commercial and military electronic devices and devices. Embedded flash memory devices are used to store data and executable programs on integrated chips. As the function of the integrated chip increases, the demand for more memory also increases, so that integrated chip designers and manufacturers have to increase the amount of available memory while reducing the size and power consumption of the integrated chip. As process technology migrates to smaller cell sizes, the integration of floating gates with high-k metal gates for embedded flash memory becomes complicated and expensive. RRAM is a promising candidate for next generation nonvolatile memory technology due to its simple structure and the accompanying CMOS logic compatible process technology.

The RRAM cell is a metal oxide material interposed between the upper electrode and the lower electrode. However, conventional RRAM cells can cause high contact resistance variations in the upper electrode vias. The present disclosure aims at lowering contact resistance variation, lowering formation voltage and improving data retention.

The present disclosure relates to a resistive random access memory (RRAM) cell architecture with an off-axis or laterally offset upper electrode via (TEVA) and a lower electrode override (BEVA). Conventional RRAM cells with on-axis TEVA and BEVA can cause high contact resistance variations. The de-enrichment TEVA and BEVA of the present disclosure push the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variation. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area, which can lower the forming voltage and improve data retention.

Figure 1A illustrates a top plan view of some embodiments of an RRAM device in accordance with the present disclosure;
Figure IB illustrates a cross-sectional view of one of the RRAM cells of the RRAM device of Figure 1 in accordance with some embodiments of the present disclosure.
Figure 2 illustrates a flow diagram of some embodiments of a method of forming an RRAM device in accordance with the present disclosure.
Figure 3 illustrates a flow diagram of some embodiments of a method of forming an upper electrode via on an RRAM cell in accordance with the present disclosure;
Figure 4 illustrates a cross-sectional view of some embodiments of upper electrode vias TEVA and lower electrode vias BEVA offset laterally on a memory cell in accordance with the present disclosure.
Figures 5A-5D illustrate some embodiments of structures offset laterally offset and not laterally offset in accordance with the present disclosure.
6 illustrates a cross-sectional view of some embodiments of an RRAM device having TEVA and BEVA offset laterally offset in accordance with the present disclosure;
Figures 7A-7F illustrate an embodiment of a cross-sectional image of a method of forming a TEVA according to the present disclosure.
Figure 8 illustrates a cross-sectional view of some embodiments of an RRAM device with lateral offset TEVA and BEVA without insulation material adjacent to the top electrode.

The description in this specification is made with reference to the drawings, wherein like reference numerals are generally used to refer to like elements throughout, and the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate understanding. It will be apparent, however, to one skilled in the art, that one or more aspects described herein may be practiced with a lesser degree of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate understanding.

The RRAM cell includes two electrodes with a resistive switching element disposed between the two electrodes. A resistive switching element or variable resistive dielectric layer utilizes a "forming process" to provide a memory device for use. The forming process is typically applied in a factory, in an assembly, or in an initial system configuration. The resistive switching material is usually insulating, but a sufficient voltage (known as the forming voltage) applied to the resistive switching material will form one or more conductive paths to the resistive switching material. Through proper application of various voltages (e.g., set voltage and reset voltage), the conductive path can be modified to form a high resistance state or a low resistance state. For example, the resistive switching material may be switched from a first resistor to a second resistor upon application of a set voltage, and from a second resistor to a first resistor upon application of a reset voltage.

RRAM cells can be considered to store logic bits, where the RRAM cells can be considered to store a "0" bit if the resistive switching element has an increased resistance, and the resistive switching element has a reduced resistance In this case, the RRAM cell can be regarded as storing a "1" bit, or vice versa. The circuit can be used to read the resistance state of the resistive switching element by applying a read voltage to the two electrodes and measuring the corresponding current through the resistive switching element. If the current through the resistive switching element is greater than some predetermined reference current, the resistive switching element is considered to be in a reduced resistance state, and thus the RRAM cell stores a logic "1 ". On the other hand, when the current through the resistive switching element is lower than some predetermined reference current, the resistive switching element is considered to be in an increased resistance state, and thus the RRAM cell stores a logic "0 ".

The RRAM cell has a conductive interconnect comprising a top electrode via (TEVA) and a bottom electrode via (BEVA) connecting the top and bottom electrodes to the rest of the device. In conventional RRAM cells, they are located along the same vertical axis. In this case, the antireflective layer, which may remain on the top electrode, will cause high contact resistance on the TEVA if TEVA is placed in that position.

Thus, the present disclosure is directed to a new architecture for RRAM cells that can improve the contact resistance variation in the upper electrode vias. In some embodiments, the conductive interconnects comprising TEVA and BEVA are laterally offset so that TEVA is away from the insulating antireflective layer, which can reduce contact resistance variations. In addition, the shape and dimensions of the RRAM cells are selected in such a way as to accommodate the conductive interconnects at both ends within the region of the RRAM cell. Small cell sizes and high density memories can have an adverse effect on the associated logic circuitry, such as stress around the RRAM region, junction leakage and abnormal dopant diffusion, low yield, reliability issues, and the like. This may cause an increase in the forming voltage. A larger area will help reduce the forming voltage and will also improve the data retention of the memory device.

Figure 1A illustrates a top plan view of a memory device 100a in accordance with some embodiments including a plurality of memory cells arranged in a series of columns and rows. The memory array 101 includes a plurality of memory cells configured to store data. For illustrative purposes, the memory cells of FIG. 1A are arranged in two rows and two columns with individual cells labeled C _row-column , but the typical embodiment collectively builds a memory array to store digital data Thousands, millions, or other numbers of rows and columns. Memory cell C ₂₂ includes an RRAM cell 102 interposed between an upper electrode via 104 and a lower electrode via 106. The lower electrode via 106 contacts the first metal contact associated with the region 108. The semiconductor substrate on which the memory cells are disposed is illustrated by reference numeral 110. [

Figure 1b illustrates a cross-sectional image of the memory cells C ₂₁ along the length of the RRAM cell of the memory cell C _21. The RRAM cell is over a semiconductor region 108 that includes a conductive region 180a, such as a metal, having an extremely low-k dielectric region 108b on both sides. Above the semiconductor region 108 is a dielectric protection layer 112 having an open area over the metal area 108a and the side walls of the dielectric protection layer 112 end with a rounded end over the metal 108a . The dielectric protection layer 112 protects the semiconductor region 108 from further etching steps. In one embodiment, the bottom electrode via (BEVA) 106 is on a defined area over the dielectric layer and follows the shape of the rounded end of the dielectric protection layer 112 in a dipping manner, 108 and above the open area. The lower electrode (BE) 114 is on the BEVA and is adjacent to the upper surface of the BEVA. The variable resistance dielectric layer or resistive switching element 116 is adjacent to the entire surface of the BE. The top electrode (TE) 118 is above the variable resistive dielectric layer 118 in the defined region. In one embodiment, the top electrode 118 includes a first TE layer 118a and a second TE layer 118b on top of the first TE 118a. Two spacers 120a and 120b are disposed on both sides of the TE 118. [ The spacers 120a and 120b are also on two end positions of the variable resistive dielectric layer 116. An upper electrode via TEVA is located on one side of the second TE layer 118b. This position causes the TEVA to be laterally offset from the conductive interconnect or BEVA / metal interface connecting the bottom of the RRAM cell to the rest of the device. The antireflective layer 122 is disposed on the second TE layer 118b at a location different from the TEVA location. The antireflective layer 122 is positioned above the metal region 108a perpendicular to the indentation on the TE layer 118b and as will be further described later in this disclosure, .

FIG. 2 illustrates a flow diagram of some embodiments of a method 200 of forming an RRAM device with BEVA and TEVA offset laterally offset in accordance with the present disclosure.

Although the disclosed method 200 is illustrated and described below as a series of operations or events, it should be understood that the illustrated sequence of events or events should not be construed in a limiting sense. For example, some operations may occur concurrently with and / or in another sequence of operations or events as illustrated and / or described herein. Furthermore, not all illustrated acts may be required to implement one or more aspects or embodiments of the disclosure herein. Moreover, one or more of the operations illustrated herein may be performed with one or more separate operations and / or steps.

At 202, a first conductive interconnect is formed adjacent the first surface of the RRAM cell at a first location.

At 204, a second conductive interconnect is formed adjacent the second other surface of the RRAM cell at a second location where the first location and the second location are laterally offset from each other. In one embodiment, the first surface is the lower surface of the RRAM cell, while the second surface is the upper surface of the RRAM cell.

Figure 3 illustrates a flow diagram of some embodiments of a method 300 of forming an upper electrode via (TEVA) on a RRAM cell in accordance with the present disclosure.

Although the disclosed method 300 is illustrated and described below as a series of operations or events, it should be understood that the illustrated sequence of events or events should not be construed in a limiting sense. For example, some operations may occur concurrently with and / or in another sequence of operations or events as illustrated and / or described herein. Furthermore, not all illustrated acts may be required to implement one or more aspects or embodiments of the disclosure herein. Moreover, one or more of the operations illustrated herein may be performed with one or more separate operations and / or steps.

At 302, an antireflective / insulating layer is deposited over the top electrode of the RRAM cell. This antireflective layer protects the RRAM surface from further photo patterning and etching steps that may occur for RRAM cells. In some embodiments, the antireflective layer deposited over the TE comprises silicon oxynitride (SiON).

At 304, a photolithography step involving an anisotropic etch is performed to pattern and etch the top electrode, leaving the variable resistive dielectric layer open at two end positions or left exposed. In some embodiments, the photolithography step does not completely remove the antireflective layer in a position to cover the top electrode, and a portion of it is left in a centered position vertically above the metal area forming the bottom contact associated with the BEVA. In some embodiments, the antireflective layer is completely removed in the etching step.

At 306, the spacer material is deposited over the entire semiconductor body to form a monolayer over the entire RRAM cell. In some embodiments, the spacer material comprises silicon nitride (SiN).

At 308, the spacer material is etched to form spacers on both ends of the top electrode. The spacers are on open and exposed end positions of the variable resistive dielectric layer.

At 310, another photolithography step is performed that leaves the protective dielectric layer open at its two end positions and etches the bottom electrode in the defined area.

At 312, an upper electrode via (TEVA) is formed adjacent the upper electrode at a position laterally spaced from the center position. This will ensure that TEVA does not come into contact with the insulating antireflective layer, and therefore, there is no increase in contact resistance unlike the conventional configuration. TEVA is also laterally offset from the conductive interconnect that connects the bottom of the RRAM cell to the rest of the device.

4 illustrates a cross-sectional view of some embodiments of an RRAM device 400 having overlying conductive interconnects and underlying conductive interconnects that are laterally offset from one another in accordance with the present disclosure. The RRAM cell 402 is interposed between two conductive interconnects offset laterally. Reference numeral 404 denotes the upper conductive interconnect adjacent to the upper surface 402a of the RRAM cell 402 and reference numeral 406 denotes the conductive interconnections adjacent to the lower surface 402b of the RRAM cell 402, Connection. The highlighted dotted area on top surface 402a represents a first location 403a over which the conductive interconnects are disposed and the highlighted dotted area 403b on the bottom surface 402b represents a second Position 403b. The first position 403a and the second position 403b are laterally offset from each other. The concept of lateral offset is described in detail in the following figures.

Figures 5A-5D illustrate some embodiments of laterally offset and laterally offset objects. To illustrate the lateral offset of two objects, two axes perpendicular to the horizontal plane and passing through the center of the two objects are introduced. If the axes are spaced apart by a non-zero distance, the two objects are offset laterally or are said to be off-axis.

FIG. 5A illustrates an arrangement 500a of two laterally offset objects 504 and 506 along a horizontal or lateral axis 502. FIG. 508 is a first axis passing through the center of the object 504, and 510 is a second axis passing through the center of the object 506. The non-zero spacing observed between the two axes is indicated by reference numeral 512. Here, the spacing between the axes 512 shows that the objects 504 and 508 are laterally offset or unscrewed relative to each other, while the objects are shown overlapping a predetermined distance along the horizontal axis 502.

Figure 5b shows an arrangement 500b of another embodiment of laterally offset objects. In this case, the corners of the objects 504 and 506 meet at a point along the lateral axis 502. However, there is a non-zero spacing 512 between the vertical axes 508 and 510 so that the objects 504 and 506 are laterally offset or deviated relative to each other.

Figure 5c shows yet another embodiment of objects offset laterally in array 500c. Here, objects 504 and 506 do not have regions that extend along horizontal axis 502. Thus, there is a very pronounced non-zero spacing between the axes 508 and 510, and the objects are offset or deviated laterally with respect to each other.

Figure 5d shows an arrangement 500d illustrating an embodiment in which two objects are not offset in a lateral direction or are on-axis. No gaps are observed between the two axes 508 and 510 or the two axes coincide and the two objects 504 and 506 are not laterally offset or coaxial with respect to each other.

6 illustrates a cross-sectional view of some embodiments of RRAM device 600 having TEVA and BEVA offset laterally offset in accordance with the present disclosure. A plurality of such RRAM devices form a memory array configured to store data. In one embodiment, a selection transistor is associated with each RRAM device. The select transistor is configured to suppress sneak-path leakage (i. E., Prevent intended current from passing through adjacent memory cells for a particular memory cell) while providing sufficient drive current for memory cell operation. FIG. 6 includes a conventional planar MOSFET selection transistor 601. The select transistor 601 includes a source 604 and a drain 606 included in the semiconductor body 602 which are horizontally separated by a channel region 605. The source 604 and the drain 606, The gate electrode 608 is positioned on the semiconductor body 602 at a location above the channel region 605. In some embodiments, the gate electrode comprises polysilicon. The gate electrode 608 extends laterally over the surface of the semiconductor body 602 and is separated from the source 604 and the drain 606 by a gate oxide layer or gate dielectric layer 607. The drain 606 is connected to the data storage element or RRAM cell 620 by a first metal contact 612a. The source 604 is connected by a second metal contact 612b. The gate electrode is connected to the word line 614a and the source is connected to the select line 614b via the second metal contact 612b and the RRAM cell 620 is connected to the upper metalization 612g by an additional metal contact 612g, Lt; RTI ID = 0.0 > 614c < / RTI > Can be selectively accessed using word lines and bit lines in a desired RRAM device for read, write and erase operations. Metal contact vias including 612a, 612b, 610c, 610d, 610e, 610f, etc., and one or more metal contacts including 612c, 612d, 612e, 612f that help to connect the RRAM memory device to external circuitry, And between the source and the second metal contact. In some embodiments, the metal contact comprises copper (Cu).

The RRAM cell 620 includes a resistive switching element / variable resistive dielectric layer 621 interposed between the upper electrode 622 and the lower electrode 623. In some embodiments, the top electrode comprises titanium (Ti) and tantalum nitride (TaN), the bottom electrode comprises titanium nitride (TiN), and the resistive switching device comprises hafnium dioxide (HfO ₂ ). The upper electrode via (TEVA) 624 connects the upper electrode 622 of the memory cell 620 to the upper metallization layer 612g and the lower electrode via (BEVA) 625 connects the lower portion of the RRAM cell 620 Electrode 623 is connected to first metal contact / lower metallization layer 612a. The TEVA 624 and the BEVA 625 are positioned relative to each other to reduce the contact resistance that may build up between the underlying insulator layer (not shown) at the center of the upper electrode 622 and the TEVA 624 Lt; RTI ID = 0.0 > direction. ≪ / RTI > RRAM cell 620 also has an enlarged overall rectangular or long area to accommodate laterally offset TEVA and BEVA. Larger long regions can lower the formation voltage and can also improve the data retention of RRAM cells.

7A-7F illustrate cross-sectional images of various embodiments of a corresponding method 300 in which upper electrode vias TEVA are formed in accordance with the present disclosure.

7A shows a cross-sectional image of an embodiment of a semiconductor body 700a including an RRAM cell, a BEVA, and a metal interconnect below. Semiconductor body 700a includes a semiconductor region 702 that includes a conductive metal region 703 disposed in an insulating layer such as a dielectric layer 704 of a very low dielectric constant. In some embodiments, the metal region comprises copper (Cu) and the dielectric layer of extra-low dielectric constant comprises porous silicon dioxide, fluorinated silica glass, polyimide, polynorbomene, benzocyclobutene or PTFE. A dielectric passivation layer 706 having an open area over the metal is disposed over the semiconductor area 702 and the side walls of the dielectric passivation layer end up with an edge rounded over the metal due to etching. In some embodiments, the dielectric protective layer comprises silicon carbide (SiC). The bottom electrode vias (BEVA) 708 are conformally over the defined area over the dielectric protection layer 706. It follows the shape of the rounded end of the dielectric protection layer in a dipping manner and also contacts the metal 703 of the semiconductor region 702 and is above the open region. In some embodiments, the BEVA comprises tantalum nitride (TaN). The lower electrode (BE) 710 is over the entire BEVA and the variable resistive dielectric layer 712 is over the BE. The variable resistive dielectric layer is usually insulative, but sufficient voltage applied to the variable resistive dielectric material will form one or more conductive paths to the variable resistive dielectric. Through proper application of various voltages (e.g., set voltage and reset voltage), the conductive path can be modified to form a high resistance state or a low resistance state. In some embodiments, the BE 710 comprises titanium nitride (TiN) and comprises a variable resistive dielectric layer hafnium dioxide (HfO ₂ ). On top of the variable resistive dielectric layer 712 is a first top electrode layer 714 and a second top electrode layer 716 is disposed adjacent to that layer. In some embodiments, the first upper electrode layer comprises titanium (Ti) and the second upper electrode layer comprises TaN. Adjacent the entire second upper electrode layer 716, an insulating antireflective layer 718 is deposited. This layer serves to improve the patterning by protecting the underlying layers from further etching steps and reducing the light reflection that causes standing waves. In some embodiments, the antireflective layer comprises SiON.

FIG. 7B shows an embodiment of the semiconductor body 700b after photo-patterning and etching the upper electrode TE. In some embodiments, an anisotropic etch step is performed to create an open exposed end 713 for the variable resistive dielectric layer at two end locations. In one embodiment, the photolithography step does not completely remove the antireflective layer 718 from the second upper electrode layer 716, but a portion thereof remains vertically centered on the metal area. In another embodiment, the antireflective layer is completely removed in the etching step.

Figure 7C illustrates an embodiment of a semiconductor body 700c after a spacer material has been deposited over all of the semiconductor body to form a spacer layer 720 overall over the semiconductor body. In some embodiments, the spacer material comprises silicon nitride (SiN).

Figure 7d shows an embodiment of semiconductor body 700d after the spacer layer 720 has been etched to form spacers 720a and 720b on both ends of the top electrode. The spacers 720a and 720b are on the open end position of the variable resistive dielectric layer.

7E illustrates an embodiment of semiconductor body 700e after another photolithography step is performed that etches lower electrode 710 and variable resistive dielectric layer 712 in the defined region. This etching step will leave the protective dielectric layer open at its two end positions.

Figure 7f illustrates an embodiment of a semiconductor body 700f after formation of an upper electrode via (TEVA) 722 at a location away from the dipping region. This will ensure that TEVA is not in contact with the insulating antireflective layer 718, and thus this configuration significantly improves the contact resistance variation as compared to conventional designs. Thus, TEVA is laterally offset from the conductive interconnect that connects the bottom of the RRAM cell to the rest of the device.

FIG. 8 illustrates an embodiment of an RRAM device 800 having TEVA and BEVA offset laterally offset in accordance with the present disclosure, as well as an upper electrode surface without an insulating antireflective layer. In this case, the antireflective layer is completely removed during step 304 of the method 300.

Although an exemplary structure is referred to throughout this specification to describe aspects of the methods described herein, it will be appreciated that these methods should not be limited by the corresponding structure presented. Rather, the methods (and structures) should be regarded as being independent of each other, alone, and may be practiced without regard to any particular aspect shown in the drawings. Additionally, the layers described herein may be formed in any suitable manner, such as spin-on, sputtering, growth and / or deposition techniques, and the like.

In addition, equivalents and / or modifications may occur to those skilled in the art based on the reading and / or understanding of the present specification and the accompanying drawings. The disclosure herein is intended to include all such modifications and alternatives, and is not generally intended to be limited thereby. For example, although the drawings provided herein are illustrated and described as having a particular doping type, alternative doping types may be used, as would be understood by one of ordinary skill in the art.

Also, although a particular feature or aspect may have been disclosed with respect to only one of several embodiments, such feature or aspect may be combined with one or more other features and / or aspects of other features as desired. Also, when the terms "comprise "," having ", " having ", "comprising ", and / or variations thereof are used herein, such terms are intended to be & . It is also to be understood that the features, layers and / or elements shown herein may be used with reference to one another for the sake of simplicity and ease of understanding, And / or orientation, and that the actual dimensions and / or orientation may be substantially different from those illustrated herein.

The present disclosure relates to a resistive random access memory (RRAM) cell having a first surface and a second surface, a first conductive interconnect adjacent a first surface at a first location, and a second conductive interconnect adjacent a second surface at a second location, (RRAM) device, wherein the first location and the second location are offset laterally from each other.

In some embodiments, the disclosure provides a semiconductor device having a semiconductor body having a source region and a drain region horizontally separated by a channel region, a gate structure coupled to the channel region, a first contact extending upwardly from the drain region and the source region, A first conductive interconnect formed over the first contact and electrically connected to the first contact; a resistive random access memory (RRAM) cell formed over the first conductive interconnect and having a first surface and a second surface, Wherein the surface is connected to the first conductive interconnect at a first location and a second conductive interconnect formed over the RRAM cell and adjacent the second surface at a second location, (RRAM) device that is offset laterally with respect to a memory cell.

In another embodiment, the disclosure provides a method of fabricating a semiconductor device, comprising: forming an ovelying conductive interconnect adjacent a first surface of a RRAM cell in a first location; (RRAM) device, wherein the first and second locations are laterally offset relative to each other. < RTI ID = 0.0 > [0002] < / RTI >

Claims (10)

1. A resistive random access memory (RRAM) device,
A resistive random access memory (RRAM) cell having a first surface and a second surface;
A first conductive interconnect adjacent the first surface at a first location; And
And a second conductive interconnect adjacent the second surface at a second location,
Wherein the first location and the second location are laterally offset from each other. The RRAM cell of claim 1,
A variable resistive dielectric layer having an upper surface and a lower surface;
An upper electrode adjacent the upper surface and disposed over the variable resistive dielectric layer;
A lower electrode adjacent the lower surface and disposed below the variable resistive dielectric layer;
An upper electrode via (TEVA) adjacent to the upper electrode; And
And a bottom electrode via (BEVA) adjacent the bottom electrode. 3. The device of claim 2, wherein the TEVA corresponds to the first conductive interconnect and is located at the first location, the BEVA corresponding to the second conductive interconnect and offset laterally from the first location, Lt; / RTI > device. The method of claim 2,
A semiconductor region comprising a metal disposed in a (extremely low-k) dielectric layer formed over the substrate;
A dielectric protective layer having an open area over the metal, the side walls of the dielectric protective layer ending with rounded ends;
An insulating layer adjacent to the upper electrode on the open area; And
The spacers on both surfaces of the upper electrode
Lt; / RTI > The method of claim 3,
Wherein the bottom electrode via (BEVA) is over a defined area over the dielectric protection layer and follows the shape of the rounded end of the dielectric protection layer in a dipping manner, contacting the metal of the semiconductor area, Above;
The lower electrode being disposed over the entire BEVA;
The variable resistive dielectric layer is disposed over the BE;
The top electrode is above a defined region above the variable resistive dielectric layer;
Wherein the TEVA is in a position offset laterally from the open region and the insulating layer. The RRAM device of claim 1, wherein the RRAM cell comprises a length dimension and a width dimension that constitute an area, and wherein the overlying conductive interconnect and the underlying interconnect interconnect are disposed in the area. The RRAM device of claim 1, wherein the RRAM cell is rectangular in shape. A resistive random access memory (RRAM) device,
A semiconductor body having a source region and a drain region horizontally separated by a channel region;
A gate structure coupled to the channel region;
A first contact and a second contact extending upwardly from the drain region and the source region, respectively;
A first conductive interconnect formed over the first contact and electrically connected to the first contact;
A resistive random access memory (RRAM) cell formed over the first conductive interconnect and having a first surface and a second surface, the first surface coupled to the first conductive interconnect at a first location, Cell; And
And a second conductive interconnect formed over the RRAM cell and adjacent the second surface at a second location,
Wherein the first location and the second location are laterally offset relative to each other. 9. The memory device of claim 8, wherein at least one metal contact and at least one metal contact via are present between the source region and the second contact and between the drain region and the first contact. A method of forming a resistive random access memory (RRAM) device,
Forming an overlying conductive interconnect adjacent the first surface of the RRAM cell in a first location; And
Forming an underlying conductive interconnect adjacent a second surface of the RRAM cell in a second location,
Wherein the first location and the second location are laterally offset relative to each other.

Images