JP6746868B2 - Stacked 3D memory and memory manufacturing method - Google Patents

Description

The present invention relates to high density memory technology, including technology for three-dimensional arrays of memory cells.

High density flash memory is used for non-volatile storage in many systems. One widely used architecture is NAND flash, which is typically implemented with a two-dimensional array of memory cells. It is widely believed that two-dimensional NAND flash is approaching its physical limits as manufacturing technology advances to smaller node technologies. Therefore, various other technologies are being sought.

In one stream of high-density memory implementations for flash memory and other types of memory, designers have implemented multiple levels of memory cells to increase storage capacity and reduce cost per bit. We are looking for a technology for stacking. For example, Lai, et al. , "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory," IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006 and Jung et al. , "Three Dimensionally Stacked NAND Flash Flash Technology Technology Stacking Stacking Single Crystals, Layers, Electrified, EDM, ILD, END, TANOStructured, ND. In 2006, thin film transistor technology is applied to charge trap memory technology. See also U.S. Patent No. 8,482,052 by Lue et al., entitled "Silicon on Insulator and Thin Film Transistor Bandgap Engineered Split Gate Memory."

In the second approach, flash memory is implemented using a vertical gate structure shared between multiple levels of memory cells. An example of a 3D vertical gate (3DVG) architecture was patented on August 6, 2013 (filed on April 1, 2011), and the title of the invention is “Memory Architecture Of 3D Array Alternating Memory Orientation And Structuring Stretching String Stretch”. , Shih-Hung Chen and Hang-Ting Lue, U.S. Pat. No. 8,503,213. The patent is incorporated herein by reference in its entirety.

In the third approach, flash memory is implemented using a vertical channel structure shared between multiple levels of memory cells. For example, the patent was filed on January 29, 2013 (filed on January 19, 2011), and the title of the invention is “Memory Device, Manufacturing Method and Operating Operating Method of The Same Same”, Hang-Ting Lu Heun and Shi-Hu. See commonly-owned U.S. Pat. No. 8,363,476. See also U.S. Patent Application No. 13/772,058 by Hang-Ting Lue, filed February 20, 2013, entitled "3D NAND Flash Memory". This patent application is incorporated herein by reference in its entirety.

Other structures that implement vertical channel structures for NAND cells in charge trapping memory technology are described by Tanaka et al. , "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory", 2007 Symposium on VLSI Technology. 2007, pages: 14-15.

In all of these 3D technologies, there is a practical limit on the number of layers of memory cells that can be implemented while maintaining reliable operation. Since each layer of the stack structure must be patterned separately, the simple stacking approach is expensive. Vertical gate and vertical channel structures, or other structures that include vertical conductors that extend across multiple layers of memory cells, can be more cost effective. This is because one mask and etching process can be used to pattern many layers. However, a structure having a high aspect ratio has a limitation because it is difficult to perform etching and an intermediate structure may be damaged in a process step.

Therefore, it is desirable to provide a technique that supports the stacking of 3D blocks of memory cells in order to overcome some of the limitations on the number of layers that can be reliably implemented.

A technique for stacking 3D blocks of memory cells is provided.

A stack structure that may fit into different structures within a 3D block is described, including structures within a memory kernel and structures of decoding elements coupled to the memory kernel. The memory kernel is at the center of the structure of the memory block and the decoding element is connected to the memory kernel. The conductors in the memory kernel can be classified into (1) a conductor such as a bit line that transmits a signal representing data and (2) a conductor such as a word line that transmits a control signal. Decoding elements in the memory kernel are connected to both types of conductors, string or block select transistors, ground select transistors, and horizontal conductors in the memory kernel, external to the memory kernel for connection to peripheral circuits, etc. A stepped structure linked to the vertical conductor.

The memory may include a plurality of memory blocks including a first block and a second block arranged above the first block. In this structure, an insulating layer is arranged between the first block and the second block to insulate the memory kernels of the first block and the second block from each other. A connection conductor is provided outside the memory kernel adjacent to the memory block or over a plurality of regions of the memory block that include only decoding elements. The connecting conductors are coupled to the decoding elements of the first block and the second block and allow a connection from the memory cells to the peripheral circuits.

By isolating the connector of one memory kernel from the connector of the stack structure above it, a stack structure with less interblock connections can be manufactured. In addition, by providing the connection conductor that is connected only to the decoding element, the connection size used for the connection conductor can be made larger than the size that can be used for the memory kernel.

Other aspects and advantages of the present technology will be understood with reference to the drawings, detailed description, and claims that follow.

FIG. 7 is a simplified diagram of a stacked 3D memory block that includes an insulating layer with interconnects for decoding elements. FIG. 6 is a perspective view of a 3D block of a memory cell having a 3D vertical gate configuration with kernel and decode element regions suitable for stacking as described herein. FIG. 6 is a perspective view of a 3D block of memory cells in a 3D vertical channel configuration with kernel and decode element regions suitable for stacking as described herein. 3 illustrates steps in a manufacturing process for stacking 3D memory blocks described herein. 3 illustrates steps in a manufacturing process for stacking 3D memory blocks described herein. 3 illustrates steps in a manufacturing process for stacking 3D memory blocks described herein. 3 illustrates steps in a manufacturing process for stacking 3D memory blocks described herein. 3 illustrates steps in a manufacturing process for stacking 3D memory blocks described herein. 3 illustrates steps in a manufacturing process for stacking 3D memory blocks described herein. 3 illustrates a set of conductors connected to each decoding element, such as a stair landing area, in a first block and a second block of a stacked memory structure. 3 illustrates a set of conductors coupled to decoding elements at each layer of a stack structure of a 3D memory block. FIG. 7 is an end view of a set of conductors, such as source line conductors, coupled to decoding elements at all layers of a stack structure for a 3D memory block. FIG. 6 is a side view of a set of conductors, such as source line conductors, coupled to decoding elements at all layers of a stack structure for a 3D memory block. Shows a conductor coupled to a decoding element of a 3D memory block, but not connected to a corresponding conductor of another block in the stack structure. 3 is a simplified flowchart illustrating a manufacturing process for forming a stack structure of 3D memory blocks described herein. 1 is a simplified block diagram illustrating an integrated circuit including a 3D memory with a stacked block of memory cells having an isolated memory kernel.

Embodiments of the present invention will be described in detail with reference to FIGS.

FIG. 1 is a simplified diagram of a stacked 3D memory with multiple memory blocks. The structure shown includes a first block comprising a memory kernel 104 and a decoding element area 114. The second block arranged above the first block includes the memory kernel 103 and the decoding element area 113. The third block arranged above the second block includes the memory kernel 102 and the decoding element area 112. The fourth block of the illustrated stack structure includes a memory kernel 101 and a decoding element area 111. An insulating layer (for example, 123) is arranged between the blocks. Connection conductors are formed in the decoding element regions 111 to 114. A plurality of segments of the connecting conductor are arranged on the insulating layers 121 to 123. In this figure, the segments 151 to 153 of the connecting conductor are arranged in the insulating layer 123 between the second block and the first block. The segments 141 to 143 of the connecting conductor are arranged in the insulating layer 122 between the third block and the second block. The segments 131 to 133 of the connecting conductor are arranged in the insulating layer between the fourth block and the third block.

In this figure, the decode element area (eg 111) is shown on only one side of the memory kernel (eg 101). In other embodiments, the decoding element regions may be distributed in other configurations, including regions on two sides of the memory kernel, regions on all sides of the memory kernel, and so on.

This technique produces a memory kernel based on a first design rule that includes the shape of the vertical conductors across the memory kernels, which are selected to achieve a very dense memory cell structure. Advantageously, it applies when the decoding elements of the memory block are manufactured according to a larger second design rule characterized by a larger shape than the shape of the vertical conductors running through.

The insulation layer separates the vertical conductors that are manufactured in the memory kernel using very tight design rules, thus affecting the behavior of damaged memory cells in a particular block on the operation of other blocks in the same stack structure. Can be limited. Also, by preventing connections between the memory kernels of multiple blocks, shared conductors across multiple memory kernels do not spread damage within a block. In addition, the insulating layer can limit the range of influence of misalignment that occurs during manufacturing.

As mentioned above, the memory block may have a vertical channel or vertical gate 3D structure. 2 and 3 show 3DVG and 3DVC blocks that can be stacked using the techniques described herein. Also, these drawings are within a decode element within a decode element region of a block that may be manufactured using smaller design rules and that may be coupled to the memory kernel and manufactured using larger design rules. The structure is shown.

FIG. 2 was published on January 12, 2012, and was filed on January 31, 2011. The title of the invention is “3D Memory Array With Improved SSL and BL Contact Layout”, which is US Patent Application Publication No. 2012/0007167. 3 illustrates a memory block having a 3D vertical gate (3DVG) architecture described in FIG. The U.S. Patent Application Publication is incorporated herein by reference in its entirety.

Insulating material has been removed from the drawing so that other structures are shown. For example, in the ridge stack structure, the insulating layer between the semiconductor strips is removed, and the insulating layer between the ridge stack structures of the semiconductor strip is removed. Decode element regions are indicated by boxes 198,199. The memory kernel is indicated by box 197.

A multi-layer array is formed on the insulating layer. Kernel 197 includes a plurality of word lines 225-1,..., 225-n-1, 225-n that include vertical extensions to accommodate a plurality of ridge-shaped stack structures. The multiple ridge stack structure includes horizontal semiconductor strips 212, 213, 214, 215 configured as channels for corresponding NAND strings in each layer of the block.

The decoding elements in the block include stair structures 212A, 213A, 214A, 215A in decoding element region 198 and stair structures 202B, 203B, 204B, 205B in decoding element region 199. The stepped structures 212A, 213A, 214A, 215A terminate horizontal semiconductor strips such as semiconductor strips 212, 213, 214, 215. As shown, these stepped structures 212A, 213A, 214A, 215A are placed above the block by vertical conductors for connection to page buffers and other decoding circuits that select planes in the array. To the different data lines being provided, in this example metal layer ML3. These stair-like structures 212A, 213A, 214A, 215A may be patterned at the same time as multiple ridge stack structures are defined using design rules larger than those used in the memory kernel.

Stepped structures 202B, 203B, 204B, 205B in the decode element region 199 terminate semiconductor strips such as semiconductor strips 202, 203, 204, 205. As shown, these step structures 202B, 203B, 204B, 205B are electrically connected to different data lines for connection to a page buffer and other decoding circuits that select the planes in the array. Has been done. These staircase structures 202B, 203B, 204B, 205B can be patterned at the same time as the multiple ridge stack structures are defined using design rules larger than those used in the memory kernel.

Any stack structure of semiconductor strips in memory kernel 197 is coupled to one of stair structures 212A, 213A, 214A, 215A, or one of stair structures 202B, 203B, 204B, 205B, but not both. The stack structure of the semiconductor strips has one of the opposite directions, that is, the direction from the end of the bit line to the end of the source line and the direction from the end of the source line to the end of the bit line. For example, the stack structure of the semiconductor strips 212, 213, 214, 215 has a direction from the end of the bit line to the end of the source line, and the stack structure of the semiconductor strips 202, 203, 204, 205 has the end structure of the source line. To the end of the bit line.

The stack structure of semiconductor strips 212, 213, 214, 215 is terminated at one end by a stepped structure 212A, 213A, 214A, 215A and passes through a decode element in region 198 including SSL gate structure 219 and ground select line GSL 226. .. Also, the stack structure of semiconductor strips 212, 213, 214, 215 passes through the decode element in region 199, which includes ground select line GSL 227 and source line 228 terminating the strip. The stack structure of the semiconductor strips 212, 213, 214, 215 does not reach the step structure 202B, 203B, 204B, 205B.

The stack structure of semiconductor strips 202, 203, 204, 205 is terminated at one end by a stepped structure 202B, 203B, 204B, 205B and has a decoding element in region 199 including SSL gate structure 209 and ground select line GSL227. Pass through. Also, the stack structure of semiconductor strips 202, 203, 204, 205 passes through the decode element in region 198, which includes ground select line GSL 226 and source line (hidden by other parts of the drawing). The stack structure of the semiconductor strips 202, 203, 204, 205 does not reach the stepped structures 212A, 213A, 214A, 215A.

A layer of memory material separates word lines 225-1 through 225-n from semiconductor strips 212 through 215, 202 through 205.

The ground selection lines GSL226 and GSL227 include horizontal lines and vertical extensions that are also aligned with the word lines to accommodate a plurality of ridge stack structures.

Each stack structure of semiconductor strips is terminated at one end by a stepped structure and at the other end by a source line. For example, the stack structure of semiconductor strips 212, 213, 214, 215 is terminated at one end by stepped structures 212A, 213A, 214A, 215A and at the other end by source line 228. On the right side of the drawing, every other stack of semiconductor strips is terminated by a step structure 202B, 203B, 204B, 205B, and every other stack of semiconductor strips is terminated by a separate source line. On the left side of the figure, every other stack of semiconductor strips is terminated by a stepped structure 212A, 213A, 214A, 215A and every other stack of semiconductor strips is terminated by a separate source line.

Transistors are formed between the stepped structures 212A, 213A, 214A and the word line 225-1. In the transistor, the semiconductor strip (eg, 213) acts as the channel region of the device. The SSL gate structure (e.g. 219, 209) is patterned in the same step where the word lines 225-1 to 225-n are defined. A layer of silicide (shown in slashes) may be formed along the top surfaces of the word lines and ground select lines, as well as on the SSL gate structure. The layer of memory material 215 can act as the gate dielectric of the transistor. These transistors act as string select gates that are coupled to decoding circuitry to select a particular ridge stack structure in the array.

Data lines and string select lines are formed in the metal layers ML1, ML2, ML3 located above the memory blocks. In a stacked structure, the metal layers include conductors that connect the connecting lines from the blocks to the peripheral circuits and can be shared by the stacked blocks, without having to duplicate each block.

In this example, the first metal layer ML1 includes a conductor having a length direction parallel to the strip of semiconductor material and connecting to the string select line. These ML1 string select lines are connected to mutually different SSL gate structures (for example, 209 and 219) by short vias.

The second metal layer ML2 includes a conductor having a width direction parallel to the word line and connected to the string selection line. These ML2 string selection lines are connected to different ML1 string selection lines by short vias.

When combined, these ML1 and ML2 string select lines allow the string select line signal to select a particular stack structure of semiconductor strips.

The first metal layer ML1 also includes a conductor having a width direction parallel to the word line and connected to the two source lines.

Finally, the third metal layer ML3 comprises a conductor which has a length direction parallel to the strip of semiconductor material and which connects to the bit line. Different data lines are electrically connected to different stages of the staircase structures 212A, 213A, 214A, 215A, 202B, 203B, 204B, 205B, respectively. These ML3 data lines allow the bit line signal to select a particular horizontal plane of the semiconductor strip.

The particular word line allows the word line to select a particular side of the memory cell, so to select a particular memory cell from a 3D array of memory cells, a word line signal and a bit line signal must be selected. And the combination of the three signals with the string select line signal is sufficient.

FIG. 3 is an exemplary vertical channel three-dimensional (as described in US patent application Ser. No. 13/772,058, filed Feb. 20, 2013, entitled “3D NAND Flash Memory”, of the invention. 3D) is a schematic diagram of a memory block. FIG. This patent application is incorporated herein by reference in its entirety. The memory blocks shown in FIG. 3 may be stacked as described herein. The memory block includes high density memory cells in memory kernel 299 and decode elements in decode element region 298.

A 3DVC memory block includes an array of NAND strings of memory cells and can be a dual gate vertical channel memory array (DGVC). The memory blocks include conductive strips separated by an insulating material that include at least a bottom surface (GSL) of the conductive strip, a plurality of intermediate surfaces (WL) of the conductive strip, and a top surface (SSL) of the conductive strip. Including multiple stack structures of. In the example shown in FIG. 3, the stack structure in the stack structure 310 includes a bottom surface (GSL) of the conductive strip, a plurality of intermediate surfaces (WL) of the conductive strips WL0 to WLN−1, and a top surface of the conductive strip. (SSL). Here, N may be 8, 16, 32, 64 and so on.

The plurality of bit line structures include a vertical stack-to-stack structure semiconductor element 320 between the stack structures and a stack-structure link element 330 connecting the stack-structure semiconductor elements 320 to each other. The bit line structures are arranged vertically upward and the vertical extension parts are aligned with the stack structures. In this example, the link element 330 comprises a semiconductor, such as polysilicon, having a relatively high doping concentration such that it has a higher conductivity than the inter-stack semiconductor element 320 that provides a channel region for cells in the stack structure.

The storage device includes a charge storage structure in an interface region at an intersection 380 between a side surface of a plurality of intermediate plane (WL) conductive strips in the stack structure and a side surface of a plurality of bit line structure inter-stack semiconductor elements 320. Including. In the illustrated example, the memory cells at intersection 380 are arranged in a vertical dual-gate NAND string. Here, the conductive strips on either side of a single inter-stack semiconductor element act as dual gates and may be operated in concert for read, erase, and program operations.

The storage device includes a string select switch 390 in the interface area with the top surface of the conductive strip and a reference select switch 370 in the interface area with the bottom surface (GSL) of the conductive strip. In some examples, the charge storage structure dielectric layer can act as the gate dielectric layer of the switches 370, 390.

The reference conductor 360 is disposed between the bottom surface (GSL) of the conductive strip and the integrated circuit board (not shown). This conductor may be located at the bottom of the stack of memory blocks and shared by the blocks within the stack. In one embodiment, the storage device may include a bottom gate 301 near the reference conductor 360 to reduce the resistance of the reference conductor 360. During a read operation, the bottom gate 301 is turned on by a suitable voltage applied to the underlying, doped well, or other underlying, patterned conductor structure in the substrate, thereby causing the reference conductor 360. The conductivity of can be increased.

The decoding elements in the decoding element region are arranged above the inter-stack vertical conductor elements 340 between the stack structures that are in electrical communication with the reference conductor 360, and above the stack structure 310 that connects the inter-stack vertical conductor elements 340. And a link element 350, and a reference line structure disposed vertically above the plurality of stack structures. The inter-stack vertical conductor element 340 may have a higher conductivity than the inter-stack semiconductor element 320.

A stack structure of memory blocks, such as that shown in FIG. 3, is arranged on top of and patterned above a plurality of bit line structures including a plurality of global bit lines coupled to a page buffer and other decoding circuits. 1 conductive layer (not shown). The storage device may also be patterned and may also include a second conductive layer (not shown) disposed above, which may be above or below the patterned first conductive layer. The upper second conductive layer is connected to at least one reference line structure, such as by contacting a link element 350 in the block's decode element region. The patterned second conductive layer may connect the at least one reference line structure to a reference voltage source or a circuit for providing a reference voltage.

In the example shown in FIG. 3, the bit line structure link element 330 comprises an N+ doped semiconductor material. The bit line structure inter-stack semiconductor element 320 comprises a lightly doped semiconductor material. In the example shown in FIG. 3, the reference conductor 360 comprises N+-doped semiconductor material and the link element 350 of the at least one reference line structure comprises N+-doped semiconductor material. The inter-stack vertical conductor elements 340 of the at least one baseline structure also include N+ doped semiconductor material. In an alternative embodiment, the inter-stack vertical conductor elements 340 may use metals or metal compounds instead of doped semiconductors.

Decode elements in the decode element region 298 provide a staircase that provides a pad area of conductive strips for a structure of horizontal word lines and GSL lines for stepwise contact with an overlying decode circuit. Including a structure. The string select lines on the top surface of the conductive strips are independently coupled to and controlled by the string select line decode circuits. The staircase structures 361, 362 connect the set of intermediate plane (WL) word lines to interlayer connectors such as interlayer connectors 371, 372 coupled to the landing area of the link element comprising the staircase structures 361, 362. Provides pad area. Here, the link element includes an opening through which an interlevel connector coupled to the landing area of the lower intermediate surface extends. The landing area is in the interface area between the bottom surface of the interlayer connector and the top surface of the link element.

As illustrated in FIG. 3, the interlevel connectors for the set of word lines in the multiple layers of the intermediate planes are arranged to form a stepped structure. Therefore, the interlayer connectors 371 and 372 are connected to the respective landing areas of different layers of the plurality of intermediate surfaces. The staircase structure can be formed in the decode element region near the boundary between the region of the NAND string block of the memory cell and the region of the peripheral circuit.

In the example shown in FIG. 3, the storage device connects a set of ground select lines on the bottom surface (GSL) of the conductive strip to an interlevel connector, such as interlevel connector 373, coupled to the landing area of the bottom link element. , Link elements such as link element 363 in the decode element area 298. Here, the interlevel connector extends through the opening of the link element in the intermediate plane (WL). The landing area is in the interface area between the bottom surface of an interlayer connector such as interlayer connector 373 and the top surface of a link element such as link element 363.

4-9 show the steps of a manufacturing process for stacking 3D memory blocks, showing the formation of interlevel connectors in a stepped structure within the decode element area of the block. The sequence of steps is the same for the other conductors used to connect the decode elements in the decode element regions of the stacked blocks.

FIG. 4 illustrates the structure after forming a first memory block including a memory kernel 401 having memory cells of multiple layers (eg, four layers) and a decode element region 411 including decode elements coupled to the memory kernel. Indicates. Vertical segments 412-1, 413-1, 414-1, 415-1, which connect to landing areas (not shown) on the staircase structure as shown in FIG. 2 as an example, are formed in the decoding element region 411. Has been done. The memory block shown in FIG. 4 may be manufactured using a process such as that described in numerous patent applications incorporated herein by reference. A block having four vertical segments 412-1, 413-1, 414-1, 415-1 manufactured as shown in connection with FIG. 2 and connected to a staircase structure in the decoding element region 411 is a memory block. It may have four sides of memory cells in the kernel 401. In the stack structure, the width of the blocks may be larger than the width required for the space of the vertical segments 412-1, 413-1, 414-1, 415-1, so that they can be combined with each vertical segment. The number of columns of memory cells in each layer can be increased.

FIG. 5 shows the structure after forming the insulating layer 421 on the first memory block. The insulating layer 421 can be manufactured using silicon dioxide or other insulating material compatible with the manufacture of integrated circuits.

FIG. 6 shows, above the decoding element region 411, second vertical conductor segments 412-1-2, 413-2, which contact first vertical conductor segments 412-1, 413-1, 414-1, 415-1. 41 shows the structure after forming 414-2, 415-2. The second segments 412-2, 413-2, 414-2, 415-2 may be manufactured using relatively large design rules compared to the design rules used for the interior of the memory kernel 401, which Alignment becomes easier, and more reliable manufacturing becomes possible.

FIG. 7 shows a structure after forming a second memory block including a memory kernel 501 having a plurality of layers of memory cells and a decoding element in the decoding element region 511 coupled to the memory kernel 501 on the insulating layer 421. Indicates. Vertical segments 512, 513, 514, 515, which connect to landing areas (not shown) on the staircase structure as shown by way of example in FIG. As described with reference to FIG. 2, using four vertical segments 512, 513, 514, and 515, as in the first block, results in the formation of four sided memory cells when the memory kernel is manufactured. It will be possible.

FIG. 8 shows that in the insulating layer 421 above the decoding element region 411, the second block decoding element region 511 is aligned with and in contact with the second segments 412-2, 413-2, 414-2, 415-2 of the vertical conductors. The structure after forming the 3rd segment 412-3, 413-3, 414-3, 415-3 in is shown. The first segment 412-1, 413-1, 414-1, 415-1 of the vertical conductor in the decoding element region 411, together with the second segment and the third segment, extends from the step structure of the first block to the second block. A vertical connection is established through the decode element area 511.

FIG. 9 schematically represents the structure after a back-end process has been performed to form an overlying conductor structure that contacts the vertical conductors in the decoding element region 511 of the top block. These overlying conductor structures in the illustrated example include bit lines BL1-BL8 coupled to page buffers and other decode circuits.

FIG. 10 is an end view of a stepped interlevel conductor within a stacked block as shown in FIG. FIG. 10 shows active layers 601 to 604 of a first block and active layers 605 to 608 of a second block separated by an insulating layer 621. Insulating layers 651 to 654 and insulating layers 655 to 658 separate the respective active layers in the block. Within the decoding element area of the block, the stepped structure as described above provides a landing area for the interlevel conductors. In this example, the inter-layer conductors are implemented within the block's decode element area, without the strict design rules of the conductors formed in the block's memory kernel. The interlayer conductors for the lower block active layers 601-604 may each include three segments. Therefore, the interlayer conductor is formed by the segment 615-1 of the lower block which is in contact with the active layer 601, the segment 615-2 of the insulating layer 621, and the segment 615-3 which passes through the upper block. An insulating layer (eg 620) surrounds the inter-layer conductor through the active layer located thereabove. In addition, the interlayer conductor for the active layer 602 includes a lower block segment 614-1, an insulating layer 621 segment 614-2, and an upper block segment 614-3. The interlayer conductor for the active layer 603 includes a lower block segment 613-1, a second segment 613-2 of the insulating layer 621, and an upper block segment 613-3. The interlayer conductor for active layer 604 does not include a segment through the bottom block. This is because the active layer 604 is the top layer in the block in this example. However, the interlayer conductor for active layer 604 includes segment 612-2 of insulating layer 621 and segment 612-3 of the upper block.

In this example, the inter-layer conductors for the top block active layers 605-608 include one segment of conductors (unsigned).

As described above, a back end process is used to mount the patterned conductive layers disposed above the bit lines BL1 to BL8 after forming the interlayer conductors in the block's decode element regions.

The multiple segment interlayer conductors shown in FIG. 10 that contact the lower block active layer are not in electrical contact with the upper block decoding elements or memory cells, but only in the lower block data lines, or in some embodiments. Provides a control line.

11-14 illustrate another type of connector for the decoding elements of a memory block. FIG. 11 shows one structure of a string select line SSL structure such as SSL gate structure 219 in decode element region 198 of FIG. 12 and 13 illustrate one structure for a source line, such as source line 228 in decode element region 199 of FIG. FIG. 14 illustrates one structure for a gate select line GSL such as gate select line 227 in decode element region 199 of FIG.

FIG. 11 shows two SSL structures respectively connected to conductor SSL1 and conductor SSL2 for connection to the peripheral circuits used for controlling the memory. In the SSL structure, the active layer comprises active strips within each stack structure. Thus, in this example, in the SSL structure coupled to SSL1, the strips for the active layers 601-604 of the first block are separated by the insulating layers 651-654, with the insulating layer 664 located above. .. Also, in this example, the strips for the active layers 605-608 of the second block are separated by insulating layers 655-658, with insulating layer 668 located above. The dielectric layer (804-1, 804-2, 804-3, 804-4), which may be a multi-layer stack structure that is also used in a memory kernel as a dielectric charge storage structure, has gate insulation between the SSL structure and the strip. Placed as a body. The SSL gate structure coupled to SSL1 includes a first segment 801-1 covering the stack structure of the lower block, a second segment 801-2 extending through the insulating layer 621, and a first segment 801-2 covering the stack structure of the upper block. 3 segments 801-3. The metal structure arranged above forms the conductor SSL1. Similarly, the SSL structure coupled to SSL2 is located above the strips for the active layers of the first and second blocks. The SSL structure includes a first segment 802-1 covering the lower block stack structure and a second segment 802-2 extending through the insulating layer 621. In this example, the insulating layer 621 has two portions connecting to two opposite sides of the SSL structure in the decoding element area of the block. The third segment 802-3 covering the stack structure of the upper block is connected to the second segment 802-2. The first segment 802-1 may be manufactured during the manufacture of the first block in a similar manner to the formation of word lines, with larger design rules to include the decoding elements. Similarly, the third segment 802-3 may be manufactured during the manufacture of the second block using larger design rules.

The SSL structure illustrated in FIG. 11 does not carry data for the upper memory part, but is an example of a connection for a decoding element of a lower block that can control the upper memory part. The SSL structure is also an example of a connecting portion extending from the lower block through the decode element region of the upper block.

FIG. 12 illustrates a source line structure that terminates a strip of active layer that connects to a reference voltage source, such as a ground voltage or other reference voltage depending on the device's operation or implementation mode. In some embodiments, the source line structure conducts current through the memory cell. FIG. 12 shows two source line structures connected to the overlying source line conductors 860, 861 in the patterned conductive layer. Source line conductors 860, 861 provide the decoding circuitry and connections to other peripheral circuitry for device operation. A dielectric layer (eg, 854), which may be a multi-layer stack structure also used in the memory kernel as a dielectric charge storage structure, may be present on the sidewall of the source line structure.

FIG. 13 shows that the strips of semiconductor material of the active layers 601-608 terminate at the source line structure segments 851-1, 851-3 in the decode element regions of the first and second blocks. The source line structure connected to conductor 860 includes a first segment 851-1 connected to a strip of active layers 601-604 in the decode element region of the lower block. In addition, the second segment 851-2 passes through the insulating layer 621. The third segment 851-3 terminates the strip of active layers 605-608 in the decode element region of the upper block. In a similar manner, the source line structure connected to the conductor 861 has a first segment 852-1 in the decoding element region of the lower block, a second segment 852-2 through the insulating layer 621, and a decoding element of the upper block. And a third segment 852-3 in the area.

The source line structures shown in FIGS. 12 and 13 provide electrical connections for conducting current in memory cells of the upper and lower memory blocks, such as common source lines. However, the structure exists in the decoding element area outside the memory kernel of the memory cell.

FIG. 14 illustrates yet another conductor disposed within the decode element regions of the first block and the second block. In this example, a ground select line GSL structure is shown, such as GSL structure 226 in decode element region 198 of the structure of FIG. The lower block includes GSL line 871. The upper block includes GSL line 872. The GSL line 871 and the GSL line 872 are not connected via the insulating layer 621. This allows independent control of the GSL lines 871 and 872 if desired. In yet another embodiment, GSL lines 871, 872 are electrically coupled to neighboring horizontally arranged blocks or to other interconnect structures outside the memory block.

Thus, the GSL structure shown in FIG. 14 may be used to control the operation of a memory block, illustrating a connector for a decoding element that is not coupled to blocks located above or below in the stack structure.

Thus, there is provided a first set of conductors (eg, staircase data lines) that are connected to the decode elements of the first and second blocks and that are located in the decode element regions outside the memory kernels of the first and second blocks. To be The first set of conductors includes conductors arranged vertically within the decode element regions that connect to the decode elements in each layer of the first block and the second block.

Also provided is a second set of conductors (eg, SSL gates or source lines) connected to the decoding elements of the first and second blocks and located within the first and second blocks outside the memory kernel. Each conductor included in the second set of conductors includes a vertical extension through all layers of the first block and the second block.

FIG. 15 shows a basic manufacturing process for stacking blocks of memory cells. The flow chart begins at step 1000, where an integrated circuit substrate on which a stacked three-dimensional memory device is formed is prepared. In this process, a first memory block including a memory kernel and a decoding element area is formed (1001) as described above. As a matter of course, many memory blocks may be formed in the block of the first layer to realize a high capacity and high density memory. An insulating layer is formed on the first memory block (1002). The insulating layer serves as a means of separating the memory kernel of the first block from the memory kernel of the second block. In the operation of the device, the memory blocks, which are based on the small design rule and are dense, of the stacked blocks are isolated by the insulating layer. Next, a second memory block (or a layer of the second memory block) is formed on the insulating layer (1003). The second memory block includes a kernel and decoding element area aligned above the corresponding area of the first memory block.

In the process, connecting conductors are provided which are coupled to the decoding elements of the first block and the second block. In the illustrated embodiment, the connecting conductors are connected to the decoding elements of the first block and the second block and are arranged vertically in the decoding element region of the block in a first set of conductors, such as staircase data lines. (1004). This first set of conductors allows a connection to the decoding elements in each layer of the first block and the second block such that the conductors of the first set do not come into contact with elements of other blocks or of other blocks. Do not control the element.

The connecting conductors implemented in this illustrated process are connected to the decoding elements of the first block and the second block, and have an SSL gate including a vertical extension through all layers of the first block and the second block, or A second set of conductors, such as source lines, is also included (1005). This second set of conductors allows a connection to the decoding elements of each layer of the first and second blocks, which second set of conductors can be used to control the decoding elements of both blocks.

In this process, other conductors may be formed as described above.

In addition, according to the process shown, peripheral circuitry is provided (1006) that uses the first and second sets of conductors to access the selected memory cells via the decode elements of the selected memory block.

The back end of line BEOL process is performed to complete device fabrication and the flowchart ends at step 1007.

The flow chart shows the basic manufacturing process. The order of steps may be modified to suit a particular embodiment. Similarly, the types of conductors implemented in the first set of conductors and the second set of conductors are selected depending on the particular implementation of the memory block and decoding element being accessed.

FIG. 16 illustrates an integrated circuit including a 3D memory array having stacked blocks with isolated memory kernels, as described herein, for accessing the memory cells of a block, and for other purposes. 3 is a block diagram showing a peripheral circuit used in FIG. A row decoder 901 is coupled to the string select lines, ground select lines, and word line drivers of block 912 that drive SSL, GSL, and word lines 902 arranged along a row of memory array 900 for electrical communication. ..

The page buffer 906 is coupled to a plurality of bit lines 904 arranged along the columns of the memory array 900 to read data from and write data to the memory cells of the memory array 900, and to perform telecommunication. To do. Addresses are given to the row decoder 901 and the page buffer 906 on the bus 905. Data is supplied from the input/output port on the integrated circuit 950 to the page buffer 906 via the data input line 911. Data is supplied from the page buffer 906 to an input/output port on the integrated circuit 950, or to another data destination inside or outside the integrated circuit 950 via a data output line 915. State machines, clock circuits, and other control logic reside in circuit 909. The bias configuration supply voltage is generated at block 908 using a charge pump and other voltage sources and provided to the word line driver at block 912 and other circuits on the integrated circuit. Integrated circuit 950 includes terminals used to connect supply voltages VDD and VSS to a power supply that supplies the chip.

Integrated circuit 950 may include other peripheral circuits not shown, such as processors, gate arrays, logic circuits, and the like.

A 3D memory structure suitable for vertical gate and vertical channel 3D blocks has been described. The structure includes a stack structure of 3D blocks each including a memory kernel and a decoding element area. The connections that extend through more than one block in the stack structure are located outside the memory kernel only in the decoding element area where large design rules may apply. The connection portion includes a connection portion that connects only to the decode element of one block and the block arranged above in the decode element region passes through. In addition, the connection portion may include a connection portion that connects to the decode elements in the decode element regions of all the blocks of the stack structure.

While the present invention has been described with reference to the preferred embodiments and examples detailed above, it should be understood that these examples are for purposes of illustration and not limitation. It is anticipated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations are included in the spirit of the invention and the embodiments of the following claims.

Claims (13)

Multiple memory blocks,
An insulating layer,
With multiple connecting conductors,
Each of the plurality of memory blocks has a memory kernel including a plurality of layers of memory cells and a plurality of vertical conductors across the plurality of layers, and a plurality of decoding elements coupled to the memory kernel,
The plurality of memory blocks include a first block and a second block arranged above the first block,
The insulating layer connects the plurality of vertical conductors of the memory kernel of the first block and the plurality of vertical conductors of the memory kernel of the second block between the first block and the second block. Insulated,
The plurality of connecting conductors are coupled to the plurality of decoding elements of the first block and the plurality of decoding elements of the second block,
The plurality of connection conductors,
It is connected to a plurality of decoding elements of the first block and a plurality of decoding elements of the second block, and is arranged in a decoding element region outside the memory kernel of the first block and the memory kernel of the second block. A plurality of conductors of the first set, the plurality of conductors of the first set including a plurality of conductors arranged in a vertical direction in the decoding element region connected to the plurality of decoding elements in each layer of the first block and the second block; Multiple conductors,
A second set of conductors connected to the plurality of decoding elements of the first block and the second block and disposed within the first block and the second block, the memory kernel of the first block And a plurality of conductors of the second set, each conductor including a vertical extension outside the memory kernel of the second block and through all layers of the first block and the second block. Including,
The plurality of conductors of the second set are SSL gates or source lines, and penetrate the insulating layer;
A plurality of conductors of said first set, Ri staircase data lines der,
The plurality of memory kernels include horizontal NAND strings,
The plurality of decode elements include a string select switch coupled to a plurality of connecting conductors that provide vertical string select lines,
The vertical string selection line of the first block is connected to the vertical string selection line of the second block through the insulating layer.
memory. The plurality of connection conductors are connected to the plurality of decoding elements of the first block and the plurality of decoding elements of the second block, and include one conductor arranged in the first block and the second block. ,
The one conductor includes a first segment connected to the decoding element of the first block, and a second segment connected to the decoding element of the second block and substantially aligned with the corresponding first segment. The memory according to claim 1, further comprising: a third segment that passes through the insulating layer and connects the second segment and the first segment. The first set of conductors comprises a corresponding layer of the memory kernels of the first block and the memory kernels of the second block in a stepped structure including a landing pad extending horizontally in the decoding element region. The memory of claim 1 connected to. The memory of claim 1, wherein a conductor included in the second set of conductors is operably coupled to a decode element of the first block and a decode element of the second block. The plurality of memory kernels of the plurality of memory blocks include at least one of a vertical word line, a vertical channel line, and a vertical source line,
The memory according to any one of claims 1 to 4, wherein the vertical source line of the first block is connected to the vertical source line of the second block through the insulating layer. The plurality of vertical conductors of the plurality of memory kernels have dimensions based on a first design rule,
The memory of any one of claims 1 to 5 , wherein the plurality of decoding elements of the plurality of memory kernels have a dimension based on a second design rule that is greater than the first design rule. Forming a first memory block having a memory kernel including a plurality of layers of memory cells and a plurality of decoding elements coupled to the memory kernel;
Forming an insulating layer above the first memory block;
Forming a second memory block on the insulating layer, the second memory block having a memory kernel including a plurality of layers of memory cells and a plurality of decoding elements coupled to the memory kernel;
Decoding outside the memory kernel of the first memory block and the memory kernel of the second memory block connected to the plurality of decode elements of the first memory block and the plurality of decode elements of the second memory block. A plurality of conductors of a first set arranged in the element region, the plurality of conductors being vertically arranged in the decoding element region connected to the plurality of decoding elements in each layer of the first memory block and the second memory block. Providing a plurality of conductors of the first set including conductors;
Is connected to a plurality of decoding elements of the first memory block and a plurality of decoding elements of the second memory block, and the first outside the memory kernel of the first memory block and the memory kernel of the second memory block. A second set of conductors disposed within the memory block and the second memory block, each of which has a vertical extension extending through all layers of the first memory block and the second memory block. Providing a plurality of conductors of the second set that the conductors include,
The second set of conductors are SSL gates or source lines, and penetrate the insulating layer;
A plurality of conductors of said first set, Ri staircase data lines der,
The plurality of memory kernels include horizontal NAND strings,
The plurality of decode elements include a string select switch coupled to a plurality of connecting conductors that provide vertical string select lines,
The vertical string select line of the first memory block is connected to the vertical string select line of the second memory block through the insulating layer.
Memory manufacturing method. The step of providing a plurality of conductors of the second set,
Forming a first segment connected to a plurality of decoding elements of the first memory block formed in the step of forming the first memory block;
Forming an interconnect through the insulating layer and connected to the corresponding first segment;
Is connected to a plurality of decoding elements of the second memory block, via the cross-connection through the insulating layer, and forming a second segment that is connected to a corresponding said first segment, claim 7 A method of manufacturing a memory according to. Further comprising forming a staircase structure including a landing area extending in the horizontal direction in the decoding element region,
9. The memory of claim 7 or 8 , wherein the first set of plurality of conductors connects to corresponding layers of the memory kernel of the first memory block and the memory kernel of the second memory block in the landing area. Production method. Providing the first set of conductors comprises forming a first block of conductors connected to a plurality of decoding elements of the first memory block,
A plurality of conductors of the first block,
A first segment disposed adjacent to the second memory block and isolated from the second memory block;
A second segment disposed substantially adjacent to the first segment and adjacent to the first memory block and in contact with a corresponding plurality of decoding elements of the first memory block;
Wherein through the insulating layer, wherein the first segment includes an interconnect that connects the second segment, memory production method according to any one of claims 7 to 9. The conductor included in the plurality of conductors of the second set, and decoding the elements of the first memory block, said operably coupled to the decoding element of the second memory blocks, any of claims 7 10 1 A method for manufacturing a memory according to item. The memory kernel of the first memory block and the memory kernel of the second memory block include at least one of a vertical word line, a vertical channel line, and a vertical source line,
Wherein said vertical source lines of the first memory block, the are through the insulating layer is connected to the vertical source lines of the second memory block, a memory process according to any one of claims 7 11. The memory kernel of the first memory block and the memory kernel of the second memory block include vertical elements having dimensions according to a first design rule;
The at least some of the plurality of decode elements of the first memory block and the plurality of decode elements of the second memory block have dimensions based on a second design rule that is greater than the first design rule. 13. The memory manufacturing method according to any one of 7 to 12 .

Images