TWI570893B - Memory architecture of 3d array with interleaved control structures - Google Patents

Description

Three-dimensional array memory structure with interleaved control structure

The present invention relates to a high density memory device, and more particularly to a memory device in which a plurality of faces of a memory cell are disposed in a three dimensional array.

Since the critical size miniaturization of devices in integrated circuits has reached the limit of general memory cell technology, designers are constantly seeking to stack several memory cell planes to achieve greater storage capacity and lower per bit. the cost of.

Fig. 1 is a perspective view of a three-dimensional integrated circuit device using a vertical gate structure. The apparatus 100 of Fig. 1 includes a stack of conductive stripes and staggered stripes in the Z direction on the integrated circuit substrate.

In the example shown in FIG. 1, the multilayer array is formed on the insulating layer and includes a structure of a plurality of conductive materials, such as a plurality of word lines 125-1 WL to 125-N WL, orthogonally stacked on the stack, and Stack conformal. Conductive stripes in a stack of conductive stripes in a number of faces (eg, 112, 113, 114, and 115) may include channels of memory elements, and structures in structures (eg, 125-1 WL to 125-N WL) may be configured as words The meta-line and the serial selection line, including the vertical gate of the memory element. Conductive stripes in the same plane Electrically coupled by a stack of connecting elements (eg, 102B, 103B, 104B, and 105B).

The contact structure including the stack of connection elements 112A, 113A, 114A, and 115A terminates conductive stripes, such as conductive stripes 112, 113, 114, and 115 in the stack. These connection elements 112A, 113A, 114A, and 115A are electrically coupled to different bit lines for connection to a decoding circuit to select faces in the array. The connecting elements 112A, 113A, 114A, and 115A can be simultaneously patterned, with a stack defined.

The stack of connecting elements (e.g., 102B, 103B, 104B, and 105B) is separated from one another in the Z direction by an insulating layer (not shown) and terminates conductive stripes, such as conductive strips 102, 103, 104, and 105. The insulating layer may include an insulating material, as described, for use as an insulating stripe disposed between the conductive stripes in the Z direction. A plurality of via connectors (e.g., 172, 173, 174, and 175) in a stack of connecting elements (e.g., 102B, 103B, 104B, and 105B) extend from the surface of the connector to individual connecting elements. The patterned conductive lines on top of the surface of the connector can be connected to respective via connectors. The via connectors 172, 173, 174, 175 are electrically connected to the connection elements 102B, 103B, 104B, and 105B to different bit lines in the patterned conductive lines, such as the metal layer ML3, for connection to the decoding circuit to The array selects the face. The stack of connecting elements 102B, 103B, 104B, and 105B can be simultaneously patterned, with several stacks defined.

The stack of conductive stripes is coupled to a stack of connecting elements 112A, 113A, 114A, and 115A, or connecting elements 102B, 103B, 104B, and 105B Stacking, not both. The stack of conductive stripes 112, 113, 114, and 115 ends at a stack of connecting elements 112A, 113A, 114A, and 115A, passing through SSL gate structure 119, ground select line (GSL) 126, word line 125- 1 WL to 125-N WL, ground select line (GSL) 127, and the other end ends at source line 128. The stack of conductive stripes 112, 113, 114, and 115 does not reach the stack of connecting elements 102B, 103B, 104B, and 105B.

Stacks of conductive strips 102, 103, 104, and 105 end at a stack of connecting elements 102B, 103B, 104B, and 105B, passing through SSL gate structure 109, ground select line (GSL) 127, word line 125- N WL to 125-1 WL, ground select line (GSL) 126, and the other end ends at the source line (in other parts of the figure). The stack of conductive stripes 102, 103, 104, and 105 does not reach the stack of connecting elements 112A, 113A, 114A, and 115A.

The memory layer is disposed in an interface region at an intersection between the surface of the conductive strips 112 to 115 and 102 to 105 and the structure of the conductive material in the conductive stripe stack, such as word lines 125-1 WL to 125-N WL. In particular, the memory layer is formed on the side surface of the conductive stripes in the stack. The memory element is disposed in an interface region at an intersection between the side surface of the stack and the word line. Ground select lines (GSL) 126 and 127 are conformal to the stack, similar to word lines.

One end of each stack of conductive stripes ends at the connecting element and the other end ends at the source line. For example, one end of the stack of conductive stripes 112, 113, 114, and 115 ends at connection elements 112A, 113A, 114A, and 115A, and the other end ends at source line 128. At the end of the adjacent map, His stack of conductive stripes ends at connection elements 102B, 103B, 104B, and 105B, and the stack of each of the other conductive stripes ends at a separate source line. At a distance away from the end of the figure, the stack of each of the other conductive stripes ends at the connecting elements 112A, 113A, 114A, and 115A, and the stack of each of the other conductive stripes ends at a separate source line.

A bit line and a tandem selection gate structure are formed in the metal layers ML1, ML2, and ML3. The bit line is coupled to a surface decoder (not shown). The serial select gate structure is coupled to a tandem select line decoder (not shown).

Ground select lines (GSL) 126 and 127 may be patterned in the same step of defining word lines 125-1 WL through 125-N WL. A ground selection device is formed at the intersection between the surface of the stack and the ground selection lines GSL 126 and 127. The SSL gate structures 119 and 109 can be patterned in the same step of defining the word lines 125-1 WL to 125-N WL. A tandem selection device is formed at the intersection between the surface of the stack and the tandem select (SSL) gate structures 119 and 109. These devices are coupled to decoding circuitry for selecting a string in a particular stack in the array.

In order to increase the number of memory cells, an additional example of the memory array of Fig. 1 can be repeatedly arranged in the Y direction. In order to connect the additional example of the memory array of FIG. 1, the bit lines formed at the metal layer ML3 extend in the Y direction. These are formed on the different faces of the memory cells in the additional example of the memory array of Fig. 1 which is formed along the extended bit line at the metal layer ML3. The connection between the extension bit line and the different faces of the memory cell is not achieved, and additional examples of connection elements 112A, 113A, 114A, and 115A and additional examples of connection elements 102B, 103B, 104B, and 105B are along the memory. Array Additional examples are repeated. Several examples of these connection elements 112A, 113A, 114A, and 115A and connection elements 102B, 103B, 104B, and 105B consume the area of the dense memory array area. As a result, the efficiency of the array is reduced. It is therefore desirable to increase array efficiency by reducing the area occupied by the connecting elements in the dense memory array region.

Other points are the complexity of transmitting the decoded address signal to a particular memory cell or group of memory cells in the three-dimensional array. The SSL gate structures 109 and 119 in Figure 1 select a particular stack from a plurality of conductive stripe stacks. The connecting elements 112A, 113A, 114A, and 115A and the connecting elements 102B, 103B, 104B, and 105B select a particular face from a plurality of conductive stripe stacks. The word lines 125-1 to 125-N select a specific position along the conductive stripe stack. It is therefore desirable to simplify the transfer of the decoded address signal to the memory structure of a particular memory cell or group of memory cells in the three dimensional oscillator.

One of the concepts of the present technology is a memory device, including a three-dimensional vertical gate NAND array, several hierarchical selection gate lines (sometimes referred to as SSL gate lines) in individual levels of the NAND array, and block selection gate lines ( Sometimes called the GSL gate line).

The NAND array includes a plurality of levels, each of the plurality of NAND strings comprising a plurality of NAND strings, the NAND strings having a first switch at one end and a second switch at an opposite end, the first switch The string is connected to a common source structure, and the second switch connects the string to a corresponding bit line. The switch can be a transistor.

Several levels select the gate line for several separate levels of the NAND array The plurality of hierarchical selection gates of the plurality of hierarchical selection gates are connected to the second switches of the plurality of NAND strings of the respective layers of the NAND array. a block selection gate line connected to the first switches of the NAND strings in the hierarchy

In one embodiment, the three-dimensional vertical gate NAND array includes a first stack of stripes of semiconductor material, the hierarchical selection gate lines including a second stack of stripes of gate material, the first stacks being staggered and coplanar Some second stacks.

In one embodiment, the three-dimensional vertical gate NAND array has a plurality of memory cells located in a plurality of intersections of semiconductor stripes and a plurality of word lines in a plurality of stacks.

One of the concepts of the present technology is a memory device that includes a NAND string in a strip of semiconductor material; a plurality of first word lines are disposed on the NAND string, and a pair of gate material stripes. The first word lines extend in a first direction. The gate material stripes are coplanar with the NAND string and extend along both sides of the NAND string in a second direction. The second direction is perpendicular to the first direction. The pair of gate material stripes are configured as a gate for the stripe portion of the semiconductor material.

An embodiment further includes a control circuit that provides a biasing arrangement to the pair of gate material strips to act as the gate for the portion of the strip of semiconductor material.

One of the concepts of the present technology is a memory device that includes a first stack of stripes of semiconductor material, a plurality of first word lines, and a second stack of stripes of gate material that are staggered and coplanar to the first A stack, and control circuit. The The second stacks are configured as a plurality of gates for the first stacks.

An embodiment further includes a control circuit that provides a plurality of bias arrangements to the second stacks to control the plurality of gates to serve as the plurality of gates of the first stack.

The word lines are orthogonal to the first stacks and have a plurality of surfaces conformal to the first stacks such that a three-dimensional array of memory elements is established on a plurality of surfaces of the first stack A number of intersections between the word lines.

In one embodiment, the first stack of strips of semiconductor material includes: a first length, wherein the word lines are orthogonal thereto along the first length; and a second adjacent to the first length length. No word line orthogonal to the second length is disposed on the second length. The second stacks are staggered along the first stack along at least a portion of the second length, and not along the first length.

An embodiment further includes a lateral stack of a plurality of gate material stripes stacked on the substrate. The lateral stack is perpendicular to the second stacks. The second stack extends from the lateral stack of strips of the brake material.

In one embodiment, a plurality of strips of sluice material strips separated from each other by an insulating material are included therein: (i) a second stack of strips of the gate material, and (ii) a lateral direction of the strip of the gate material In the stack. The plurality of sluice material strips located in a plurality of the second stacks are electrically connected to each other by the laterally stacked sluice material strips at the same side.

In one embodiment, the lateral stack of strips of the gate material has an outer portion and an inner portion, the outer portion being adjacent to the second stack, the inner portion The sub-portions are separated from the second stack by the outer portion. The outer portion includes a plurality of strips of sluice material strips separated by an insulating material, and the inner portion is filled with the insulating material.

An embodiment further includes a third stack of stripes of semiconductor material, a plurality of second word lines, and a fourth stack of stripes of thyristors, the fourth stacks being interleaved with the third stacks. The fourth stacking system is configured as a plurality of gates of the fourth stack.

The lateral stack has a first side and a second side opposite each other. The first side of the lateral stack faces the first stack, the second stacks, and the first word lines. The second stack extends from the first side of the lateral stack of stripes of the gate material.

The second side of the lateral stack faces the third stack, the fourth stack, and the second word lines. The fourth stack extends from the second side of the lateral stack of stripes of the gate material.

The second word lines are orthogonal to the third stacks and have a plurality of surfaces conformal to the third stacks, thereby establishing a three-dimensional array of another memory element on the third stacks The intersection of several surfaces and the second word lines.

In one embodiment, the second stacking locations are at a plurality of first locations along a length of the lateral stack. The fourth stacking locations are at the first locations along the length of the lateral stack.

In an embodiment, the second stacked bits are stacked along the horizontal direction A number of first positions of a length. The fourth stacking locations are at a plurality of second locations along the length of the lateral stack. The first positions are interlaced with the second positions.

In one embodiment, the fringe of the plurality of gate material strips separated from each other by the insulating material is included in: (i) a second stack of strips of the gate material, and (ii) a lateral stack of strips of the gate material. The control circuit provides a first one of the biasing arrangements to a particular one of the second stacks, and a second one of the biasing arrangements to the other of the second stacks A plurality of memory cells of the particular face are selected among the faces in the first stack.

In an embodiment, the second stacks interlace the first stacks such that one of the second stacks is located between two adjacent ones of the first stacks.

In an embodiment, adjacent stacks in the first stacks have opposite stack orientations, including a first stack orientation of a bit line contact-to-source line contact, and a The second stack orientation of the source line contact-to-bit line contact.

In an embodiment, the second stacks interlace the first stacks, such that one of the second stacks is located between two adjacent ones of the first stacks having the same stack orientation, and is located at the first stack orientation Beyond this second stack orientation.

In an embodiment, adjacent stacks in the first stacks have an identical stacking orientation, including a first stacking surface in which one bit line contacts the source line contact. Bit, one of the second stack orientations in contact with a source line to the bit line.

In one embodiment, the first stacks of strips of semiconductor material are parallel to each other, and the second stack of strips of thyrist material are parallel to each other.

In one embodiment, the first stack of strips of semiconductor material has a plurality of first ends coupled to a source line voltage and a plurality of second ends coupled to a one-bit line voltage.

Another concept of technology is a method of operating three-dimensional memory, including: A plurality of memory cells are selected in a particular one of the plurality of faces of the three-dimensional memory array by providing a plurality of biases arranged to a second stack of stripes of gate material. The faces are established at intersections between a plurality of first word lines and a first stack of stripes of semiconductor material. The first word lines are orthogonal to the first stack of strips of semiconductor material and have a first stacked strip of surface conformal to the strips of semiconductor material. A second stack of the sluice material strips is staggered on the substrate and coplanar with the first stacks.

Various embodiments are disclosed below.

Yet another concept of technology is a fabrication method comprising: forming a first stack of stripes of semiconductor material; forming a plurality of first word lines orthogonal to the first stack and having surface conformalities The first stacks are such that a plurality of three-dimensional array memory elements are established at intersections between the surfaces of the first stacks and the word lines; and a second stack forming a plurality of gate material stripes, The first stacks are interlaced and coplanar with the first stacks, and the second stacks are configured as the first A stack of several gates.

Other concepts and advantages of the present invention can be seen in the following drawings, detailed description, and claims.

ML1, ML2, ML3‧‧‧ metal layer

172, 173, 174, 175‧‧ ‧ interlayer connectors

102, 103, 104, 105, 102B, 103B, 104B, 105B‧‧‧ connection elements

109‧‧‧ gate structure

112, 113, 114, 115, 112A, 113A, 114A, 115A‧‧‧ connection elements

119‧‧ ‧ gate structure

125-1, 125-N‧‧‧ character line

126‧‧‧ Grounding selection line

127‧‧‧ Grounding selection line

128‧‧‧ source line

202, 402‧‧‧ bit line contact

203, 403‧‧‧ bit line contact

P#204, P#404‧‧‧Second length

P#205, P#405‧‧‧ Length

P#505‧‧‧Optoelectronics

206, 406‧‧‧ character line

207, 407, 507‧‧ ‧ character lines

208, 408‧‧‧ Grounding selection line

209, 409, 509‧‧‧ Grounding selection line

210, 410‧‧‧shared source line contact

211, 411, 511‧‧ ‧ shared source line contact

212, 412‧‧‧Semiconductor material stripe stacking

213, 413, 513‧‧ ‧ semiconductor material stripe stacking

214, 414‧‧‧ brake material stripe stacking

215, 415‧‧ ‧ brake material stripe stacking

220, 420‧‧‧ transverse gate material stripe stacking

225, 425‧‧‧ ladder structure

228‧‧‧ side wall

428‧‧‧ side wall

303‧‧‧ bit line

P#305‧‧‧Optoelectronics

307‧‧‧ character line

309‧‧‧ Grounding selection line

311‧‧‧ Grounding selection line

710, 712, 714‧‧‧ insulation

711, 713‧‧‧ conductive layer

750‧‧‧Stacking of conductive stripes

958‧‧‧ Face Decoder

959‧‧‧Sequence selection line

960‧‧‧Memory array

961‧‧‧ column decoder

962‧‧‧ character line

963‧‧‧ row decoder

964‧‧‧ bit line

965‧‧ ‧ busbar

966‧‧‧

967‧‧‧ data bus

968‧‧‧ squares

969‧‧‧ Controller

971‧‧‧ data input line

972‧‧‧ data output line

974‧‧‧Other circuits

975‧‧‧ integrated circuit

1115‧‧‧ memory material layer

1116‧‧‧ character line

1117‧‧‧ character line

1197‧‧‧Tunnel dielectric layer

1198‧‧‧Charge storage layer

1199‧‧‧Blocking dielectric layer

1120‧‧‧ trench

1230‧‧‧ openings

2130‧‧‧ openings

Figure 1 is a perspective view of a three-dimensional memory structure.

2 is a top view of a three-dimensional memory structure having stripe stacks of semiconductor material, the stripe stack of semiconductor material having memory elements interleaved with strips of gate material, wherein strips of semiconductor material with memory elements are stacked to share bit lines to The orientation of the source line.

Figure 3 is a circuit diagram showing one of the semiconductor material stripe stacks of the three-dimensional memory structure in Figure 2.

Figure 4 is a top view of a three-dimensional memory structure having a stripe stack of semiconductor material having a memory element interleaved with a strip of gate material, wherein the stripe stack of semiconductor material with memory elements has bit lines to The orientation of the source line and the orientation of the source line to the bit line.

Figure 5 is a circuit diagram of one of the semiconductor material stripe stacks of the three-dimensional memory structure of Figure 4.

6 to 14 are manufacturing processes of the three-dimensional memory structure in Fig. 2 in an embodiment.

15 to 23 are manufacturing processes of the three-dimensional memory structure in Fig. 4 in an embodiment.

Figure 24 is a set of dimensions of the three-dimensional memory structure of Figure 4 in an embodiment.

Figure 25 is a schematic diagram of an integrated circuit including a three-dimensional memory array with staggered stripe stacks, and column, row and plane decoding circuits.

The embodiments are described in detail below with reference to the drawings.

2 is a top view of a three-dimensional memory structure having a stripe stack of semiconductor materials, a stripe stack of semiconductor material having a memory element, a stripe stack of staggered gate materials, wherein a strip of semiconductor material with memory elements is stacked to share a bit line to the source The common orientation of the bit line-to-source line.

Figure 2 includes a top array and a bottom array. The top array is explained below. The semiconductor material stripe stack 212 includes a stack of 16 strips of semiconductor material. In each stack, the stripes of semiconductor material are interlaced with the dielectric stripes. The semiconductor material stripe stacks 212 are parallel to each other.

The plurality of word lines 206 include eight word lines orthogonal to the semiconductor material stripe stack 212 and have a surface that is conformal to the semiconductor material stripe stack 212. The word lines 206 are parallel to each other and extend in the same direction. Other embodiments may include other numbers of word lines. The three dimensional array of memory elements is established at the intersection between the stripe stack 212 of semiconductor material and the surface of the word line 206. The method of selecting memory elements at a particular location along the stripe stack 212 of semiconductor material is to provide a set voltage to word line 206 that distinguishes one word line from the other. The word lines can be referred to as vertical gates because of their vertical orientation extending up and down the side of the stripe stack 212 of semiconductor material.

Ground select line 208 is also orthogonal to semiconductor material stripe stack 212 And having a surface conformal to the stripe stack 212 of semiconductor material.

The semiconductor material stripe stack 212 has opposite first and second ends. The first end has a common source line contact 210 for striping all of the semiconductor material in different stacks. The second end has bit line contacts 202 for striping all of the semiconductor material in different stacks. The method of selecting a plurality of memory elements on a particular stack of semiconductor material stripe stacks 212 is to provide a set voltage to bit line contact 202 that distinguishes one stack of semiconductor material stripe stacks 212 from other semiconductor material stripe stacks 212. .

The semiconductor material stripe stack 212 has a first length with the word lines 206 being orthogonal to the first along the first length. This first length of the strip of semiconductor material stripes has a first width. The semiconductor material stripe stack 212 has a second length adjacent to the first length. No word lines are disposed on the second length of the stripe stack 212 of semiconductor material. The second length of the stripe stack 212 of semiconductor material ends at bit line contact 202. The second length has a second width that is narrower than the first width of the first length. The second length of each of the strips of semiconductor material stripes 212 is indicated by a dashed dotted line. The second length of all semiconductor material stripe stacks is labeled P# 204 and is indicated by a rectangular dashed line. Reference numeral P# denotes a plurality of faces, and can be explained with reference to FIG.

The gate material stripe stack 214 and the semiconductor material stripe stack 212 are staggered with each other. The gate material stripe stacks 214 are alternately parallel and extend in a direction perpendicular to the direction in which the word lines extend. In some embodiments, the gate material stripe stack 214 has the same material as the semiconductor material stripe stack 212, which simplifies the process. or, The gate material can be a conductor such as a highly doped semiconductor such as polysilicon or a metal. The gate material stripe stack 214 is perpendicular to the lateral gate material stripe stack 220 and extends from the lateral gate material stripe stack 220. The gate material stripe stacks 214 are staggered along the length of the semiconductor material stripe stack 212, preventing shorting of the word lines 206. The gate material stripe stack 214 is coplanar with the semiconductor material stripe stack 212 such that the stack in the gate material stripe stack 214 has substantially the same vertical position as the stack in the semiconductor material stripe stack 212. In some embodiments, the gate material stripe stack 214 and the lateral gate material stripe stack 220 are formed with stripes of semiconductor material staggered with dielectric stripes, like the semiconductor material stripe stack 212. In this embodiment, the gate material stripe stack 214 on the same side is electrically interconnected by the gate material strips of the lateral gate material stack 220 in the same plane.

Regardless of whether the second length P# 204 of the stripe stack 212 of semiconductor material along a particular face is electrically or non-conductive, it is controlled by the stripe stack 214 of gate material on the same side. The gate material stripe stack 214 produces a field effect that controls the conductivity in the second length P# 204 in the semiconductor material stripe stack 212. Field effects can include accumulation, depletion, or inversion. Thus, a field effect is generated in accordance with the gate material stripe stack 214 to open and close the second length P# 204 along the stripe stack 212 of semiconductor material, along which the second length P# 204 of the stripe stack 212 of semiconductor material can be strengthened (enhancement) or depletion mode doping is n-type or p-type. It is assumed that the second length P# 204 on one side of the stripe stack 212 of semiconductor material is doped to the enhancement mode, when the bias of the gate material stripe stack 214 on the same side is greater than or equal to the second length of the doped n-type P# 204 Pro The second length P# 204 is conducted when the boundary voltage is less than or equal to the threshold voltage of the second length P# 204 doped to the p-type. It is assumed that the second length P# 204 on one side of the stripe stack 212 of semiconductor material is doped to the enhancement mode, when the bias strips provided by the gate material stripe stack 214 on the same side are greater than or equal to the second length doped to the n-type. When the threshold voltage of P# 204 is less than or equal to the threshold voltage of the second length P# 204 doped to the p-type, the second length P# 204 is conducted. Assuming that the second length P# 204 on one side of the stripe stack 212 of semiconductor material is doped to a depletion mode, the second length P# 204 conducts when the bias provided by the gate material stripe stack 214 on the same side is zero volts. When the bias voltage provided by the gate material stripe stack 214 on the same side is less than the threshold voltage of the second length P# 204 doped to the n-type, or greater than the threshold voltage of the second length doped to the p-type, the second Length P# 204 stops conduction.

For any single semiconductor material stripe in any single stack in the semiconductor material stripe stack 212, a pair of gate material strips in the gate material stripe stack 214 are coplanar on either side of a single strip of semiconductor material and along a single semiconductor The sides of the material strip extend in parallel. The pair of gate material stripes are configured as gates of the stripe portion of the semiconductor material.

Each of the gate material stripe stacks 214 need not be staggered along the entire adjacent second length P#204, and the second length P#204 is along the semiconductor material stripe stack 212. Even though the gate material stripe stack 214 extends partially along the entire adjacent second length P#204, rather than extending completely, the gate material stripe stack 214 can still be controlled along the edges due to the electric field fringe and spread. The semiconductor material stripe stack 212 is adjacent to the second length P#204.

The method of selecting memory elements on a particular side of the semiconductor material stripe stack 212 provides a set voltage to the gate material stripe stack 214. As a result, the gate material stripe stack 214 controls the conductivity along the second length P#204 of the semiconductor material stripe stack 212, which causes one face of the semiconductor material stripe stack 212 to be differentiated from other faces of the semiconductor material stripe stack 212. The selection of one side of the semiconductor material stripe stack 212 may be due to the gate material stripe stack 214 providing a field effect to the adjacent second length P#204 on the selected surface, and the field effect does not occur on the other side adjacent the second length P #204, and vice versa.

The ladder structure 225 transmits a serial selection signal, wherein the serial selection signal selects a particular face of the semiconductor material stripe stack 212. In one embodiment, the ladder structure can be similar to the connecting elements 112A, 113A, 114A and 115A of Figure 1, and the connecting elements 102B, 103B, 104B and 105B. Other embodiments may change the order, shape and configuration of the connecting elements.

The serial selection signals are transmitted to different faces of the gate material stripe stack 214. As previously discussed, the different faces of the gate material stripe stack 214 control the conductivity along the second length P#204 of the semiconductor material stripe stack 212, which separates the semiconductor material stripe stack from the memory elements on one side of the stripe stack 212 of semiconductor material. 212 memory components on other faces.

In combination, the word line signal, the bit line signal, and the serial selection line signal are sufficient to identify individual memory cells in the three-dimensional memory array.

In addition to the top array just described, Fig. 2 also shows the bottom array which will be described below. The bottom array includes a plurality of semiconductor material stripe stacks 213 including 16 A strip of semiconductor material staggered with dielectric stripes. The word line 207 includes eight word lines that are orthogonal to the stripe stack 213 of semiconductor material and have a surface that is conformal to the stripe stack 213 of semiconductor material. The memory elements of the three dimensional array are established at the intersection between the surface of the stripe stack 213 of semiconductor material and the surface of the word line 207. Ground select line 209 is also disposed orthogonal to semiconductor material stripe stack 213 and has a conformal surface to semiconductor material stripe stack 213.

The semiconductor material stripe stack 213 has opposite first and second ends. The first end has a common source line contact 211 for all of the semiconductor material stripes in the individual stack. The second end has a bit line contact 203 for all of the semiconductor material stripes in the individual stack.

The gate material stripe stack 215 is interleaved with the semiconductor material stripe stack 213. The gate material stripe stack 215 is perpendicular to the lateral gate material stripe stack 220 and extends from the lateral gate material stripe stack 220.

The bottom array can also be similar to the configuration, operation, and variations of the top array.

Figure 3 is a circuit diagram of a stripe stack of semiconductor materials in the three-dimensional memory structure of Figure 2.

All of the semiconductor material stripe stacks 212 and 213 include a plurality of faces of strips of semiconductor material separated by an insulating material. For simplicity, a single stack of semiconductor material stripes is shown.

In a single stack, the eight faces of the strip of semiconductor material are separated by an insulating material. Other embodiments include a different number of face or strips of semiconductor material. In each of the faces in the stack, a NAND string includes a series of transistor CSLs 311, GSL 309, word line (WL) 307 (which includes WL0, WL1 to WL N-1), P# 305, and bit line (BL) 303. Other embodiments may use switches other than transistors. The transistors P1 to P8 in Fig. 3 are generally designated P# 305, which is a selective memory element on a particular face or strip of semiconductor material. As described with reference to FIG. 2, a stacked memory component that provides a stack of specific semiconductor material stripes to a voltage group is distinguished from a stack of other semiconductor material stripes, and the voltage set provided to WL 307 will be accessed by a particular word line. Memory elements distinguish memory cells accessed by other word lines.

As described with reference to FIG. 2, the gate material stripe stack 214 on the same side is electrically connected to each other by the gate material strips of the lateral gate material stack 220 in the same plane. FIG. 3 shows the specific faces of the transistors in the stripe stack 212 of all semiconductor materials in a single one of the transistors P1 to P8. The gates of the single one of the transistors P1 to P8 of Fig. 3 correspond to all of the gate material stripe stacks 214 on the same side. The body of the single one of the transistors P1 to P8 of FIG. 3 corresponds to all of the second lengths P# 204 on the same face in the stripe stack 212 of semiconductor material.

Other semiconductor stripe stacks have the same circuitry as shown in FIG. All of the gate material stripe stacks 214 use the same CSL 311, GSL 309, WL 307, and P#305. However, since the voltage sets provided to the different BLs 303 distinguish the other stacks of memory cell distinguishing gate material stripe stacks 214 in a particular stack of gate material stripe stacks 214, the BLs 303 are different from the different gate material stripe stacks 214.

Figure 4 is a top view of a three-dimensional memory structure with stripe stacks of semiconductor material. The semiconductor material stripe stack has a memory element that is interleaved with the gate material stripes, wherein the semiconductor material stripe stack with the memory elements has The bit line-to-source line and the source line-to-bit line are interleaved.

The configuration, operation, and variation of Fig. 4 are substantially similar to Fig. 2 except for the difference between the upper half array and the lower half array described below. Figure 2 includes a top array of complete bit line to source line semiconductor material stripe stacks, and a bottom array of complete bit line to source line semiconductor material stripe stacks. Figure 4 includes an upper half array and a lower half array. The complete bit line to source line semiconductor material fringe stack is formed by combining several examples of FIG. 4, for example, the upper half top array in the first example of FIG. 4 merges with the lower half bottom in the second example of FIG. Array.

The semiconductor material stripe stack 412 includes eight strips of semiconductor material stripes that include other possible stacks of semiconductor material stripes. In Figure 2, the memory strings in adjacent stacks share the same bit line end to the end of the source line. In Figure 4, the memory cell strings in adjacent stacks alternate between the orientation of the end of the bit line to the end of the source line and the end of the source line to the end of the bit line. The semiconductor material stripe stack 412 includes a stack having end portions of bit lines that are alternately arranged with the gate material stripe stack 414. The semiconductor material stripe stack 412 does not include a stack having source line ends, wherein the source line ends are not alternately arranged with the gate material stripe stack 414.

The strip of semiconductor material stripes 412 has opposite first and second ends. The first end has a bit line contact 402 for individually striping all of the semiconductor material strips. The second end has a common source line contact for stripping all of the semiconductor material in each stack.

The memory construction examples of Figure 4 are combined in a tile fashion to form a complete stripe stack of semiconductor material with bit line ends and a common source line end. In the first example of FIG. 4, in the upper half top array, the semiconductor material stripe stack 412 includes a stack having bit line contacts 402 but no shared source line contacts. The second example of Fig. 4 is disposed in the form of a tile in the vicinity of the top edge adjacent to the first example of Fig. 4. In the second example of FIG. 4, the lower half bottom array includes a stripe stack of semiconductor material that includes a common source line contact 411 but does not include bit line contacts. The stripe stack 412 of semiconductor material including the bit line contact 402 in the upper half array of the first example of FIG. 4 ends at the top edge of the first example of FIG. 4, and then proceeds to the second example of FIG. The bottom edge is connected to the semiconductor material stripe stack, wherein the semiconductor material stripe stack comprises the common source line contact 411 in the lower half bottom array of the second example of FIG. Thus, a complete strip of semiconductor material stripe having a terminal line end and a common source line end is formed by combining several examples of FIG.

Similarly, the other semiconductor material stripe stacks in the upper half-array array of Figure 4 include a stack having a common source line contact 410 without bit line contact. As described above, the second example of Fig. 4 is reproduced and arranged in the form of a tile in the vicinity of the top side of Fig. 4. In the second example of FIG. 4, the lower half bottom array includes a stripe stack of semiconductor material, and the stripe stack of semiconductor material includes bit line contacts 403, but does not include a common source line contact. The stripe stack of semiconductor material including the common source line contact 410 in the upper half-top array of the first example of FIG. 4 ends at the top edge of the first example of FIG. 4, and then proceeds to the bottom edge of the second example of FIG. To connect semiconductor materials The fringe stack is stacked, wherein the stripe stack of semiconductor material includes the bit line contact 403 in the lower half-bottom array of the second example of FIG. Again, the complete semiconductor material stripe stack at the end of the bit line and the end of the common source line is formed by combining several examples of FIG.

The word line 406 includes a word line of 4 that is orthogonal to the strip of semiconductor material stripes in the top half of the top array and has a surface that is conformal to the stripe stack of semiconductor material in the top half of the top array. The three dimensional array of memory elements is established at the intersection between the surface of the stripe stack of semiconductor material and the word line 406 in the top half of the array.

Word line 407 includes four word lines that are orthogonal to the strip of semiconductor material stripes in the lower half of the bottom array and that have surfaces that are conformal to the stripe stack of semiconductor material in the lower half of the bottom array. The three dimensional array of memory elements establishes the intersection between the surface of the stripe stack of semiconductor material and the word line 407 in the lower half of the array.

By combining the methods of the four fourth example examples as described above, word line 406 and word line 407 form a group of word lines as a whole to access a complete memory array.

The GSL/SSL 408 is orthogonal to the stripe stack of semiconductor material in the top half of the array and has a surface conformal to the stripe stack of semiconductor material in the top half of the array. The GSL/SSL 409 is orthogonal to the strip of semiconductor material stripes in the lower half of the bottom array and has a stripe of semiconductor material that is surface conformal to the lower half of the bottom array. In the example where GSL/SSL 408 or GSL/SSL 409 approximates a common source line contact for a particular stripe stack, GSL/SSL 408 or GSL/SSL 409 acts as a ground select line. In the case of GSL/SSL 408 or GSL/SSL 409 approximating bit line contact of a particular stripe stack, GSL/SSL 408 or GSL/SSL 409 acts as a tandem select line.

The semiconductor material stripe stack 412 has a first length along the word line 206, and the word lines 206 are orthogonally disposed on the semiconductor material stripe stack 412. As described above, because several examples of FIG. 4 are combined to form a complete semiconductor stripe stack having bit line ends, source line ends, and intermediate word lines. The first length of the stripe stack 412 of semiconductor material has a first width. The semiconductor material stripe stack 412 has a second length adjacent the first length. No word lines (without GSL/SSL lines) are disposed on the second length of the stripe stack 412 of semiconductor material. The second length of the strip of semiconductor material stripes terminates at bit line contact 402. The second length has a second width that is narrower than the first width of the first length. The second length of each of the strips 412 of semiconductor material is indicated by an elliptical dashed line. The second length of all semiconductor material stripe stacks is collectively indicated by the reference P#404 and the rectangular dashed line. The P# number indicates a plurality of faces and is described with reference to FIG.

The gate material stripe stack 414 and the semiconductor material stripe stack 412 are staggered with each other. The gate material stripe stack 414 is perpendicular to the lateral gate material stripe stack 420 and is stacked 420 from the lateral gate material stripe. The gate material stripe stack 414 is partially staggered along the length of the semiconductor material stripe stack 412, preventing shorting between the word line 406 (and GSL/SSL 408). As noted above, the operation of FIG. 4 is generally similar to FIG. 2, including controlling the conduction or non-conductivity of the second length P# 404 along the stripe stack 412 of semiconductor material on a particular side, the sluice material stripe stack 414 on the same side.

In Fig. 4, the memory cell strings in the adjacent stack are staggered between the end of the bit line to the end of the source line and the end of the source line to the end of the bit line. A stack having one of the above orientations includes stripes in a semiconductor material Stacks in stack 412 and having other orientations are not included in stripe stack 412 of semiconductor material. The different illustration is that the gate material stripe stack 414 can control the conductivity of other stacks that are interleaved with the gate material stripe stack 414.

The ladder structure 425 carries a serial selection signal that selects a particular face of the stripe stack 412 of semiconductor material.

In addition to the upper half array described in the context of merging a plurality of examples of Fig. 4, Fig. 4 also shows the bottom array explained below. The bottom array includes a stripe stack 413 of semiconductor material that includes eight strips of semiconductor material staggered with dielectric stripes. The word line 407 includes eight word lines orthogonally disposed on the semiconductor material stripe stack 413 and having a surface conformal to the semiconductor material stripe stack 413. The three dimensional array of memory elements is established at the intersection between the stripe stack 413 of semiconductor material and the surface of word line 407.

The gate material stripe stack 415 is staggered across the semiconductor material stripe stack 413. The gate material stripe stack 415 is perpendicular to the lateral gate material stripe stack 420 and extends from the lateral gate material stripe stack 420.

The configuration, operation, and variations of the lower half of the array can be similar to the upper half of the array.

Fig. 5 is a circuit diagram showing one of the stacked semiconductor material stripes of the three-dimensional memory structure in Fig. 4.

The configuration, operation, and variation of Figure 5 are generally similar to Figure 3, with the differences illustrated below.

All semiconductor material stripe stacks 412 and 413 include insulation The faces of the strips of semiconductor material separated by materials. For the sake of simplicity, Figure 5 shows a stack of stripes of a single semiconductor material. The complete stacking of strips of semiconductor material is formed by combining several examples of Figure 4 such that the stack of strips of semiconductor material includes a one-bit end and a common source line end.

In a single stack, the eight faces of the strip of semiconductor material are separated by an insulating material. Among the various faces of the stack, the NAND string includes series transistors CSL 511, GSL 509, WL 507 (including WL0, WL1 to WL N-1), P#505 and BL 503. The transistors P1 to P8 are generally designated P#505, and a memory element on a particular face or strip of semiconductor material is selected.

As described with reference to FIG. 4, the gate material stripe stack 414 on the same side is electrically connected to each other by the strips of material of the lateral gate material stack 420 in the same plane. The single one of the transistors P1 to P8 of Fig. 5 selects a particular face of the transistor in the stripe stack 412 of all semiconductor materials. Figure 5 of the transistors P1 to P8 in which the gates of a single one correspond to all of the gate material stripe stacks 414 on the same side. Figure 5 of the transistors P1 to P8 wherein the bodies of the single one correspond to all of the second lengths P# 404 on the same side of the stripe stack 412 of semiconductor material.

As described above with reference to Figure 4, the memory cell strings in adjacent stacks are interleaved between the end of the bit line end to the end of the source line and the end of the source line end to the end of the bit line. The strip of semiconductor material (which includes the second length controlled by the same one of transistors P1 to P8 in Figure 5) all share the same orientation, the orientation of the end of the bit line to the end of the source line and the end of the source line in place. The orientation of the end of the line is either.

For memory cell arrays having opposite orientations, the additional set of transistors P1 through P8 in the other examples of Figure 5 provide control for distinguishing memory elements on a particular face from other memory elements on other faces. As described with reference to FIG. 4, the complete bit line-to-source line semiconductor material stripe stack is formed by combining several examples of FIG. Additional sets of transistors P1 through P8 in the additional example of Figure 5 are in the additional example of Figure 4.

6 to 14 are manufacturing processes of the three-dimensional memory structure of Fig. 2 in an embodiment.

Figure 6 is a top view of the stack of layers of semiconductor material. The semiconductor layer and the dielectric layer are interdigitated with each other.

The conductive plug and other via connectors form a stack through the layer of semiconductor material. The conductive plug then becomes part of the bit line contact 202, the bit line contact 203, the shared source line contact 210, and the common source line contact 211.

Fig. 6 includes a dotted rectangle having an arrow line A-A indicating a plane portion in the three-dimensional view of Fig. 7.

Figure 7 is a three-dimensional view of the portion of Figure 6, showing the structure formed by alternately depositing insulating layers 710, 712, 714 and conductive layers, 711, 713. The conductive layers, 711, 713 are formed using doped semiconductors, such as Blankly deposited in the array area of the wafer. Although two conductive layers are shown, eight layers may be formed to cause eight faces of the memory element, or other numbers of conductive layers may be used. The arrow line A-A corresponds to the arrow line in Fig. 6.

The semiconductor material layer can be formed by a plurality of doped semiconductors, for example For example, p-type or n-type germanium; a plurality of doped forms such as p-type or n-type single crystal semiconductors; or a plurality of doped forms such as p-type or n-type polycrystalline semiconductors.

A representative embodiment having a doping concentration of n-type semiconductor stripes may be about 1018/cm3, and may be implemented in the range of 1017/cm3 to 1019/cm3. The use of n-type semiconductor stripes is particularly beneficial for junction-free embodiments to enhance conductivity along the NAND string and thereby allow for higher read currents.

The insulating layers 710, 712, and 714 may be selected from polymethylsilsesquioxane (P-MSQ), SiLK, fluorine-doped oxides, carbon-doped oxides, porous oxides, and spin-coated organic One or more substances in the group consisting of polymeric dielectrics, wherein the fluorine-doped oxide comprises fluorinated silicate glass (SiOF), and the carbon-doped oxide comprises tantalum silicate Carbonated silicate glass (SiOC), black diamond, coral, and aurora. These material layers can be formed in a variety of ways, including low pressure chemical vapor deposition (LPCVD) processes that can be used in the art.

Figure 8 is a top view of a stripe stack of semiconductor material. The semiconductor material stripe stack 212 has an opposite orientation to the semiconductor material stripe stack 213. The outer ends of the semiconductor material stripe stack 212 and the semiconductor material stripe stack 213 are individual common source line plugs. The semiconductor material stripe stack 212 and the inner end of the strip of semiconductor material stripe 213 prevent shorting between individual bit line plugs.

Fig. 8 includes a dotted rectangle having an arrow line B-B indicating a plane portion of the three-dimensional view of Fig. 9, and showing a partial view of Fig. 9 taken from Fig. 8.

Figure 9 is a three-dimensional view of the portion of Figure 8, showing the results after the yellow lithography patterning step, the yellow lithography patterning step is used to define a stack 750 of conductive stripes of a plurality of raised shapes, wherein the conductive stripes are made of a conductive layer The materials of 711, 713 are separated from each other by insulating layers 712, 714. A high aspect ratio trench can be formed using a carbon hard mask and a reactive ion etching process to form a high aspect ratio trench in the stack, supporting many material layers. The arrow line B-B corresponds to the arrow line B-B of Fig. 8.

Figure 10 shows a top view of the word lines on the stripe stack of semiconductor materials. The word line 206 covers the intermediate length of the stripe stack of semiconductor material in the upper array. The ground select line 208 covers the portion of the semiconductor material stripe stack that is between the word line 206 and the common source line contact. Word line 207 covers the intermediate length of the stripe stack of semiconductor material in the lower array. The ground select line 209 covers the semiconductor material stripe stack in a portion between the word line 207 and the common source line contact.

Fig. 10 includes a broken line rectangle having an arrow line C-C, which indicates a plane portion of the three-dimensional view of Fig. 11, and shows a partial structure of Fig. 11 taken from Fig. 10.

Figure 11 is a three-dimensional view of the portion of Figure 10 showing the word lines on the memory material stacked with the stripes of semiconductor material.

In this example, the memory material layer 1115, such as a dielectric charge trapping structure, covers a plurality of semiconductor stripe stacks. A plurality of word lines 1116, 1117 are orthogonal to a plurality of semiconductor stripe stacks. The surfaces of the word lines 1116, 1117 are conformal to the semiconductor stripe stack, filled with trenches defined by the stack (eg, trenches 1120), and stacked on the stack The interface region at the intersection between the side surfaces of the semiconductor stripes 711 to 714 and the word lines 1116, 1117 defines a multi-layer array. The word lines 1116, 1117 can be semiconductor materials that are the same or different conductivity types as the semiconductor material stripes. For example, the semiconductor stripes may be formed of a p-type polycrystalline germanium or a p-type epitaxial single crystal germanium, and the word lines 1116, 1117 may be formed of a relatively heavily doped p+ type polycrystalline germanium.

A telluride layer (e.g., tungsten telluride, cobalt telluride, titanium telluride) may then be formed on the top surface of the word lines 1116, 1117.

As a result, a three-dimensional array constructed in a NAND flash array is formed. A source, a drain, and a channel are formed on the germanium semiconductor stripes 711 to 714, the memory material layer 1115 includes a tunneling dielectric layer 1197, which may be formed by yttrium oxide (O), and a charge storage layer 1198, which may be nitrided ( N) forming; blocking dielectric layer 1199, which may be formed of yttrium oxide; and gates, which may include polysilicon (S) of word lines 1116, 1117.

Therefore, a memory cell including a field effect transistor having a charge storage structure is formed in a three-dimensional array of intersections. The size of the semiconductor stripe and the word line is 25 nm, the pitch between the bumps is 25 nm, and the tens of layers (for example, 32 layers) in a single wafer can reach megabit capacity ( 1012).

The memory material layer 1115 can include other charge storage structures. For example, a bandgap engineered SONOS (BE-SONOS) charge storage structure can be used that includes a dielectric tunneling layer 1197 that includes a reverse "U" shape at zero bias. The composite material of the belt. In one embodiment, the composite tunneling dielectric layer includes a first layer called a tunneling layer called a band compensation layer (band) The second layer of the offset layer) and the third layer of the isolation layer. In this embodiment, the tunnel tunneling layer 1115 includes ruthenium dioxide on the side surface of the semiconductor stripe, and the formation method is, for example, an in-situ steam generation (ISSG) method, which can be performed by post-deposited NO annealing or by a deposition process. An additional pass-through environment NO performs an arbitrarily selected nitridation step. The first layer of cerium oxide has a thickness of less than 20 angstroms, preferably 15 angstroms or less. Representative embodiments may have a thickness of 10 angstroms or 12 angstroms.

In this embodiment, the band compensation layer includes tantalum nitride on the tunnel tunnel layer, for example, using dichlorosilane (DCS) and NH3 precursor, 680 ° C low pressure chemical vapor deposition (low-pressure chemical) Vapor deposition; LPCVD) formation. In other processes, the bandgap compensation layer, including bismuth oxynitride, is formed in a similar manner to the N2O precursor. The tantalum nitride band compensation layer has a thickness of less than 30 angstroms, and preferably 25 angstroms or less.

The spacer layer in this embodiment includes ruthenium dioxide on the tantalum nitride band compensation layer, and the formation method is, for example, a LPCVD high temperature oxide (HTO) deposition method. The thickness of the ceria barrier layer is less than 35 angstroms, preferably angstroms or less. The three-layer tunneling layer causes a reverse U-shaped valence band energy level.

The valence band energy level of the first location is an electric field sufficient to cause a hole to tunnel through a thin region between the semiconductor body and the first position interface, which is also sufficient to lift the valence band energy level to a level after the first position, which has The hole tunneling barrier after the composite tunneling dielectric first position is efficiently eliminated. This structure establishes a reverse U-shaped valence band energy level in the three-layer tunneling dielectric layer, and enables high-speed electric field-assisted hole tunneling, while efficiently avoiding the composite tunneling dielectric in the absence of Electric field or for other The purpose of the operation is to cause a leakage charge problem that occurs when a small electric field is generated, such as reading data from a unit cell or stylizing adjacent unit cells.

In the representative device, the memory material layer 1115 includes a band gap engineered composite tunneling dielectric layer comprising a ceria layer having a thickness of less than 2 nm, a tantalum nitride layer having a thickness of less than 3 nm, and a dioxide having a thickness of less than 4 nm.矽 layer. In one embodiment, the composite tunneling dielectric layer is formed from an ultra-thin yttrium oxide layer O1 (eg, <=15 angstroms), an ultra-thin tantalum nitride layer N1 (eg, <=30 angstroms), and an ultra-thin yttrium oxide layer O2. (e.g., <= 35 angstroms), which compensates the interface of the semiconductor body by 15 angstroms or less, resulting in an elevated valence band energy of about 2.6 eV. The O2 layer separates the N1 layer at a second compensation (eg, from about 30 angstroms to 45 angstroms from the interface) by a lower valence band energy level (higher tunnel tunneling barrier) and a higher conduction band energy level region. Self-charge trapping layer. An electric field sufficient to cause tunneling of the hole raises the valence band energy level after the second position to a level, which effectively eliminates the hole tunneling barrier because the second position is located farther from the interface. Therefore, the O2 layer does not significantly interfere with the electric field-assisted hole tunneling, while at the same time improving the ability of the engineered tunneling dielectric to prevent leakage during low electric field.

The charge trapping layer in the memory material layer 1115A in this embodiment comprises tantalum nitride having a thickness greater than 50 angstroms and a thickness of, for example, about 70 angstroms, formed by a method such as LPCVD. Other charge trapping materials and structures can also be used, including, for example, cerium oxynitride (SixOyNz), cerium-rich nitrides, cerium-rich oxides, capture layers including buried nanoparticles, and the like.

In this embodiment, the barrier dielectric layer in the memory material layer 1115 comprises a ruthenium dioxide layer having a thickness greater than 50 angstroms, for example about 90 angstroms, by means of a wet furnace. The tube oxidation process forms a wet conversion of the nitride. Other embodiments may use high temperature oxide (HTO) or LPCVD SiO2. Other barrier dielectrics can include high-k materials such as alumina.

In a representative embodiment, the tunnel tunneling layer may be a cerium oxide having a thickness of 13 angstroms; the energy compensation layer may be a tantalum nitride having a thickness of 20 angstroms; the insulating layer may be a cerium oxide having a thickness of 25 angstroms; and the charge trapping layer may be It is a tantalum nitride having a thickness of 70 angstroms; the barrier dielectric layer may be yttrium oxide having a thickness of 90 angstroms. The gate material can be p+ polysilicon (work function about 5.1 eV) for use in word lines 1116, 1117.

The top view of Figure 12 additionally shows an additional strip of semiconductor material stripes.

The direction of extension of the lateral gate material stripe stack 220 is parallel to the word line. In the top array, the gate material stripe stack 214 extends in a direction perpendicular to the vertical gate material stripe stack 220, contacted by the bit lines, but not shorted to the word lines. A length P# 204 of the stripe stack 212 of semiconductor material is formed. The length P# 204 is narrower than the remaining semiconductor material stripe stack 212. In a subsequent step, a dielectric fill such as an oxide is filled in the gap between the semiconductor material stripe stack 212 and the gate material stripe stack 214.

In the bottom array, the gate material stripe stack 215 extends in a direction perpendicular to the vertical gate material stripe stack 220, which is contacted by the bit lines without shorting the word lines. A length P#205 of the stripe stack of semiconductor material is formed. The length of the length P# 205 is narrower than the remaining semiconductor material stripe stack 213. In a subsequent step, a dielectric filler such as an oxide is formed on the semiconductor material stripe stack 213 and the gate material strip The gap between the stacks 215 is in the gap.

High aspect ratio trenches can be formed in a stack using a carbon hard mask and a reactive ion etched yellow light lithography process to support many materials.

Openings 1230 are formed to the top array and bottom array sides, and intermediate portions of the lateral gate material stripe stack 220. As described with reference to FIG. 3, the transistor gates of the transistors P1 to P8 are formed from all of the gate material stripe stacks 214, all of the gate material stripe stacks 215, and the same side of the lateral gate material stripe stack 220. The brake material in the middle. By forming the opening 1230, the volume of the gate material in any particular layer can be reduced. Reducing the volume of the thyristor material can cause the transistors P1 to P8 to reduce the RC delay and increase the rate of the switch.

Figure 13 is a top view showing the process of a three-dimensional memory array. Forming a ladder structure 225 that transmits a series selection signal that selects a particular face of the semiconductor material stripe stack 212 from the control circuit to the gate material stripe stack 214, the gate material stripe stack 215, and the lateral gate material stripe stack 220 Different faces.

Sidewall 228 is formed in opening 1230. The sidewall deuteration formation may be cobalt silicide (CoSix), titanium silicide (TiSix), or other telluride compound, such as a self-aligned deuteration process on the sidewalls of the word line group (self- Aligned silicide;SAlicide). The formation of a telluride can deposit a thin telluride precursor, such as a transition metal layer, on the sidewalls. The structure is then annealed to cause the telluride precursor to react with the conductive material to form a low resistance sidewall deuterated formation. Remove any excess or excess transition metal.

Figure 14 is a top view showing the process of a three-dimensional memory array. Formed in contact with the plug, including bit line 202, bit line 203, word line 206, word line 207, ground select line 208, ground select line 209, common source line contact 210, and a common source Polar line contact 211.

15 to 23 are views showing a manufacturing process of the three-dimensional memory structure according to FIG. 4 in an embodiment. Figures 15 through 23 generally correspond to the configurations, operations, and variations of Figures 6 through 14.

Figure 15 depicts a top view of a stack of layers of semiconductor material, and is substantially similar to Figure 6. The conductive plug and other via connectors form a stack through the layer of semiconductor material. The conductive plug then becomes part of the bit line contact 402, the bit line contact 403, the common source line contact 410, and the common source line contact 411.

Fig. 15 includes a dotted rectangle having an arrow line D-D indicating the area in which the three-dimensional view of Fig. 16 is located in Fig. 15.

Fig. 16 is a three-dimensional view of a portion of Fig. 15 and is substantially similar to Fig. 7. The arrow line D-D corresponds to the arrow line D-D in Fig. 15.

Figure 17 is a top view of a stripe stack of semiconductor material and is generally similar to Figure 8. The semiconductor material stripe stack 412 has an opposite orientation to the semiconductor material stripe stack 413. The semiconductor material stripe stack 412 and the semiconductor material stripe stack 413 extend through individual common source line plugs. In another embodiment, the stripe stack 412 of semiconductor material and the stripe stack 413 of semiconductor material are not shorted to the common source line plug.

Figure 17 includes a dotted rectangle and an arrow line E-E, which indicates Figure 18 is a plan view of the position of the three-dimensional view in Figure 17.

Figure 18 is a three-dimensional view of a portion of Figure 17, showing the result of defining a raised stack of conductive stripes using a yellow lithography patterning step, and is substantially similar to Figure 9. The arrow line E-E corresponds to the arrow line E-E in Fig. 17.

Figure 19 is a top view of a strip of semiconductor material having word lines and is substantially similar to Figure 10. The word line 406 covers the intermediate length of the stripe stack of semiconductor material in the upper array. GSL/SSL 408 covers the strip of semiconductor material between the word line 406 and the common source line contact. The word line 407 covers the intermediate length of the stripe stack of semiconductor material in the lower array. GSL/SSL 409 covers the stack of semiconductor material stripes between word line 407 and the common source line contact.

Fig. 19 includes a dotted rectangle and an arrow line F-F indicating the plane portion of the position of the three-dimensional view of Fig. 20 in Fig. 19.

Figure 20 is a three-dimensional view of the portion of Figure 19 showing the memory material and semiconductor material stripes stacked, and the word lines above them, and are substantially similar to Figure 11.

Figure 21 is a top view which further shows other semiconductor material stripe stacks and is substantially similar to Figure 12.

The direction of extension of the lateral gate material stripe stack 420 is parallel to the word line. In the upper half of the top array, the strip material stack 414 extends in a direction perpendicular to the lateral gate material stripe stack 420, which is in contact with the bit line but not with the word line (and Short-circuited between GSL/SSL lines). A length P#404 of the stripe stack 412 of semiconductor material is formed. The length P# 404 has the same width as the remaining semiconductor material stripe stack 412, while in another embodiment it may also be wider or narrower than the remaining semiconductor material stripe stack 412. In a subsequent step, a dielectric fill such as an oxide is formed in the gap between the semiconductor material stripe stack 412 and the gate material stripe stack 414.

In the lower half bottom array, the gate material stripe stack 415 extends in a direction perpendicular to the lateral gate material stripe stack 420, through the bit line contacts, without forming a shorting with the word lines (and the GSL/SSL lines). A length P#405 of the semiconductor material stripe stack 413 is formed. The length P#405 is the same width as the remaining semiconductor material stripe stack 413, but in another embodiment it may be wider or narrower than the remaining semiconductor material stripe stack 413. In a subsequent step, a dielectric fill such as an oxide is formed in the gap between the semiconductor material stripe stack 413 and the gate material stripe stack 415.

Yellow light lithography based on carbon hard masking and reactive ion etching can be used to form trenches in the stack, supporting many layers of material.

An opening 2130 is formed to the upper half top array and the lower half bottom array side, and to the intermediate portion of the lateral gate material stripe stack 420. As described with reference to FIG. 5, the transistor gates of the transistors P1 to P8 are formed from all of the gate material stripe stacks 414, all of the gate material stripe stacks 415, and the same side of the lateral gate material stripe stack 420. Brake material.

Figure 22 is a top view showing another form of a three-dimensional memory array One step, and is substantially similar to Figure 13. A ladder structure 425 is formed. A sidewall 428 is formed in the opening 1230.

Figure 23 is a top view showing another step of forming a three-dimensional memory array and is substantially similar to Figure 14. Forming a contact on the plug, including bit line 402, bit line 403, word line 406, word line 407, ground select line 408, ground select line 409, shared source line contact 410, and common Source line contact 411.

Fig. 24 is a view showing the size group of the three-dimensional memory structure of Fig. 4 in an embodiment. The narrowness of the stripe based on the semiconductor material is 56 nm to 20 nm, and the critical dimension in the X-axis direction is 20 nm. The critical dimension in the Y-axis direction is 38 nm, which is wider than 20 nm based on the stripe of the semiconductor material and 18 nm from the stripe to oxide of the semiconductor material. The array efficiency increased from 69.2% to 74.2%.

The area efficiency is equal to: (array cell area) / (array cell area + upper part area), wherein the upper portion includes the tandem selection line area, the ground selection line area, the contact landing area, and other non-array cells. area.

In Fig. 24, the blank region is filled with oxide, and includes a blank region on the contact having a length of 130 nm in the Y direction, and a blank region at the contact of 100 nm in the Y direction. Blank areas are etched away in different steps.

Figure 25 is a simplified circuit block diagram in accordance with an embodiment. Integrated circuit line 975 includes a three dimensional NAND flash memory array 960, as described below, on a semiconductor substrate having a staggered control structure. a short set of gates The material stack provides a field effect to turn on and off a portion of the long set of semiconductor material stacks. Column decoder 961 is coupled to a plurality of word lines 962 and is arranged along a number of columns in memory array 960. The row decoder is coupled to a plurality of bit lines 964 along a plurality of rows of the stack in the corresponding memory array 960 for reading and stylizing data from the memory cells in the array 960. The face decoder 958 is coupled to the plurality of faces in the memory array 960 through the serial select line 959. The address is supplied to the row decoder 963, the column decoder 961, and the area decoder 958 in the bus 965. In this example, the sense amplifier and data input structure in block 966 is coupled to row decoder 963 via data bus 967. The data is passed through data entry line 971, from input/output ports on integrated circuit 975, or other sources of data internal or external to integrated circuit 975, to the data input structure in block 966. In the embodiments described herein, other circuits 974 are included on integrated circuits, such as general purpose processors, or other special purpose application circuits, or program elements of on-chip system functions supported by NAND flash memory cell arrays. combination. Data is provided from the sense amplifiers in block 966 through data sense line 972 to input/output ports on integrated circuit 975, or to other data destinations internal or external to integrated circuit 975.

The controller 969, in this example, uses a bias-arranged state machine to control the biasing arrangement generated or provided by the voltage supply in block 968 to provide voltage applications, such as read, erase, stylize, erase verify, and stylized verification. Voltage. The controller transmits a signal to plane decoder 958 that transmits a set of set voltages to the tandem select line 959 to a short stack of gate material stacks, such as providing field effects to turn on or off portions of the long stack of semiconductor material stacks to act as Long group of semiconductor material stacking parts pole.

For any single semiconductor material stripe in a single semiconductor material stripe stack, a pair of gate material strips in the gate material stripe stack are coplanar with both sides of a single semiconductor material stripe and are striped along a single semiconductor material strip. Extending on both sides. The pair of gate material stripes are configured as gates of the stripe portion of the semiconductor material, and the controller provides a biasing arrangement to the gate material strips to act as gates for the stripe portions of the semiconductor material. The controller can use known special purpose logic circuits. In other embodiments, the controller includes a general purpose processor that can be implemented on the same integrated circuit that executes a computer program to control the operation of the device. In still another embodiment, the controller can incorporate a special purpose logic circuit with a general purpose processor.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

202‧‧‧ bit line contact (BL)

203‧‧‧ bit line contact (BL)

P#204‧‧‧Second length

P#205‧‧‧ Length

206‧‧‧ character line (WL)

207‧‧‧ character line (WL)

208‧‧‧Ground selection line (GSL)

209‧‧‧ Grounding Selection Line (GSL)

210‧‧‧Shared source line contact (CSL)

211‧‧‧Shared source line contact (CSL)

212‧‧‧Semiconductor material stripe stacking

213‧‧‧Semiconductor material stripe stacking

214‧‧‧Semiconductor material stripe stacking

215‧‧‧Semiconductor material stripe stacking

220‧‧‧Horizontal semiconductor material stripe stacking

225‧‧‧ ladder structure

Claims (20)

A memory device comprising: a three-dimensional vertical gate NAND array comprising a plurality of levels, each of the levels comprising a plurality of NAND strings, the NAND strings having a first switch at one end and an opposite end The first switch is connected to the serial switch to a common source structure, the second switch is connected to the serial to a corresponding bit line; the plurality of levels select the gate line, and are separately set separately And in the plurality of different levels of the NAND array, wherein the hierarchical selection gates of the plurality of hierarchical selection gates are connected to the second switches of the NAND strings of the respective layers of the NAND array; A block select gate line is connected to the first switches of the NAND strings in the levels. The memory device of claim 1, wherein the three-dimensional vertical gate NAND array comprises a first stack of stripes of semiconductor material, the hierarchical selection gate lines comprising a second stack of stripes of gate material, The first stacks are staggered and coplanar with the second stacks. The memory device of claim 1, wherein the three-dimensional vertical gate NAND array has a plurality of memory cells located in a plurality of intersections of semiconductor stripes and a plurality of word lines in the plurality of stacks. A memory device comprising: a NAND string in a strip of semiconductor material; a plurality of first word lines disposed on the NAND string, the first word lines extending along a first direction; and a pair of gate material stripes coplanar with the NAND string and along a second The direction extends on both sides of the NAND string, the second direction being perpendicular to the first direction, the pair of gate material strips being configured as a gate for the stripe portion of the semiconductor material of only a single level. The memory device of claim 4, further comprising a control circuit that provides a biasing arrangement to the pair of gate material strips to act as the gate for the portion of the strip of semiconductor material. A memory device includes: a first stack of stripes of a plurality of semiconductor materials; a plurality of first word lines orthogonal to the first stacks and having a plurality of surfaces conformal to the first stacks, Forming a three-dimensional array of memory elements at a plurality of intersections between the plurality of surfaces of the first stack and the first word lines; and a second stack of a plurality of gate material stripes, staggered and coplanar In the first stacks, the second stacks are configured as a plurality of gates for the first stacks. The memory device of claim 6, further comprising: a control circuit, providing a plurality of bias arrangements for controlling the second stacks to serve as the plurality of gates of the first stack. The memory device of claim 6, wherein the first stack of strips of semiconductor material comprises: a first length, wherein the word lines are orthogonal to the first length; and a second length adjacent to the first length, the second length is not disposed orthogonal to the second length a word line; and wherein the second stacks are staggered along the first stack along at least a portion of the second length, and not along the first length. The memory device of claim 6, further comprising: a lateral stack of a plurality of sluice material strips perpendicular to the second stacks, the second stacks extending from the sluice material strips The lateral stacking. The memory device of claim 9, wherein a plurality of planes of strips of thyristor separated by an insulating material are included therein: (i) a second stack of strips of the damper materials, And (ii) the lateral stack of strips of the gate material, and located in different ones of the second stacks, and the plurality of gate material stripes on the same side of the faces are by the lateral stack at the same face The gate material strips are electrically connected to each other. The memory device of claim 9, wherein the lateral stack of strips of the gate material has an outer portion and an inner portion, the outer portion being adjacent to the second stack, the inner portion being The outer portion is separated from the second stack, the outer portion comprising a plurality of slat material strip faces separated by an insulating material, the inner portion being filled with the insulating material. The memory device according to claim 9 of the patent application, further comprising: a third stack of stripes of semiconductor material; a plurality of second word lines orthogonal to the third stack and having a plurality of surfaces conformal to the third stack, thereby causing another memory a three-dimensional array of elements is formed at intersections of the plurality of surfaces of the third stack and the second word lines; a fourth stack of strips of thyristor material interleaved with the third stacks, the The four stacks are configured by the at least one dielectric as the plurality of gates of the fourth stack, wherein the lateral stack has an opposite first side and a second side, wherein the first side of the lateral stack faces a first stack, the second stack, the first word lines, wherein the second stacks extend from the first side of the lateral stack of the gate material strips, wherein the second side of the lateral stack The third stack, the fourth stacks, and the second word lines, wherein the fourth stacks extend from the second side of the lateral stack of the gate material strips. The memory device of claim 12, wherein the second stacking positions are at a plurality of first positions along a length of the lateral stack, and the fourth stacked positions are along the lateral direction The first positions of the length of the stack are stacked. The memory device of claim 12, wherein the second stacked bits are in a plurality of first positions along a length of the lateral stack Positioning, the fourth stacking positions are at a plurality of second positions along the length of the lateral stack, and the first positions are staggered with the second positions. The memory device of claim 6, wherein the surface of the plurality of gate material strips separated from each other by the insulating material is included in: (i) a second stack of strips of the gate material, and (ii) a lateral stack of strips of gate material, and further comprising: a control circuit providing a first one of the biasing arrangements to a particular one of the second stacks, and one of the biasing arrangements The second to the other of the second stacks to select a plurality of memory cells of the particular face in the plurality of faces in the first stack. The memory device of claim 6, wherein the second stacks interlace the first stacks such that one of the second stacks is located between two adjacent ones of the first stacks. The memory device of claim 6, wherein the adjacent stacks in the first stack have opposite stacking orientations, including one bit line contact-to-source line Contact a first stack orientation, and a second stack orientation of a source line contact-to-bit line contact. The memory device of claim 17, wherein the second stacks interlace the first stacks such that the second stacks One of the two adjacent ones of the first stack having the same stacking orientation is located outside the first stacking orientation and the second stacking orientation. The memory device of claim 6, wherein adjacent stacks of the first stacks have a same stack orientation, including a first stack orientation of one-bit line contact to source line contact, and a The source line contacts one of the second stack orientations of the bit line contact. The memory device of claim 6, wherein the first stack of strips of semiconductor material has a plurality of first ends coupled to a source line voltage and coupled to a bit line voltage Several second ends.