TWI566365B - Contact structure and forming method, and the circuit using the same - Google Patents

Description

Contact structure and forming method and circuit using same

The disclosure relates to a high density component. In particular, embodiments of the present invention provide a method for forming a contact structure that is coupled to an active layer in a three-dimensional high density semiconductor device such as a memory device.

The three-dimensional semiconductor component is characterized by a plurality of layers to form a stack of alternating active and insulating layers. In a memory component, each layer can include a planar array of memory cells. For some three-dimensional stacked memory elements, the active layer may comprise active strings, the active series of materials being used by bit lines or word lines for stacking in memory cells of spaced apart ridge structures Composition. The active layer may be composed of a doped (p-type or n-type) or undoped semiconductor material. In such three-dimensional memory, the memory cells can be disposed at the intersection of stacked bit lines or word lines and intersecting word lines or bit lines to form a three-dimensional memory array.

One of the methods of joining the interlayer conductors to the active layers in the stack can be found in the multiple lithographic-etch process disclosed in U.S. Patent No. 8,383,512, entitled "Using a Multilayer Connection. Method for Making Multilayer Connection Structure, the disclosure of which is incorporated herein by reference. Another method of joining the interlayer conductors to the active layers in the stack can be referred to as a trim-etch process, as disclosed in U.S. Application Serial No. 13/735,922, filed on Jan. 7, 2013, entitled " Method for Forming Interlayer Conductors to a Stack of Conductor Layers, the disclosure of which is incorporated herein by reference.

A method of forming a via hole in a layer stack can be performed as described below. A stack of alternating active layers and insulating layers is formed by forming a first stack, a second stack, a first buffer layer, and a second buffer layer. The first stack includes N active layers separated by an insulating layer. The second stack is stacked on the first stack, and the second stack includes M active layers separated by an insulating layer. The first buffer layer is formed between the first stack and the second stack, and the second buffer layer is formed under the first stack. One of the upper layers of the first stack is exposed through a set of through holes by a first etching process and a second etching process. The etching is performed using a first etching process to form a first set of etched vias that are stacked by the second time and stopped in the first buffer layer or stopped in the first buffer layer. The etching is performed using a second etching process, passing through the first buffer layer to stack the upper layer for the first time. The first stacking is performed by etching through the third etching process and the fourth etching process. Etching is performed using a third etch process, through the first set of etch vias, through the first stack and stops at the second buffer layer or stops in the second buffer layer. And then etching is performed using a fourth etching process through the second buffer layer.

The method for forming the vias can include one or more of the steps described below. A stepped structure can be formed by etching through the vias to form a landing zone, the landing zone being over the active layer of the first stack and the second stack, and forming an interlayer conductor extending to the landing zone. The etching used to form the stepped structure may include using a single etching process to form the landing zone on an integer multiple of an N layer having an integer multiple of at least two. The etching time of the first buffer layer is greater than the etching time of one of the insulating layers of the second stack under the second etching process and the first etching process for each of the first buffer layer and the second stack. The first buffer layer may be (1) the first buffer layer may be composed of the same material as the first stacked insulating layer, but the thickness of the first buffer layer is different from the thickness of one of the first stacked insulating layers. The case, or (2) the material composition of the first buffer layer may be different from the case of the first stacked insulating layer, or the case of (3) having both (1) and (2). The thickness of the first buffer layer may be at least 1.5 times greater than the thickness of an active layer in the first stack. The first stack may feature a first spatial period N1, and the second stack may feature a second spatial period N2, where N1 is equal to N2. An etch mask can be formed over the second stack, the etch mask having an etch mask opening, and the step of exposing the upper layer can be performed by etching the mask opening. The forming step of the first stacking and the second stacking may be performed such that the thickness of the upper layer of each of the first stacking and the second stacking is greater than at least one of the active layer and the insulating layer of the corresponding sub-stack.

A stepped contact structure includes a stack of alternating active and insulating layers having a plurality of non-simple spatial periods, a stepped structure of a landing zone on the active layer, and extending to the landing zone and borrowing An interlayer conductor separated from each other by an insulating material. The stack of alternating active layers and insulating layers includes One stack and a second stack, and a first buffer layer between the first stack and the second stack. The first stack has N active layers separated by an insulating layer, and the N active layers include an upper boundary active layer. The second stack is located on the first stack, and the second stack has M active layers separated by an insulating layer, and the M active layers include an upper boundary active layer. Under the etching process performed, the etching time of the first buffer layer is greater than the etching time of one of the insulating layers of the second stack.

The stepped contact structure can include one or more of the following. The first buffer layer may be (1) the first buffer layer may be composed of the same material as one of the first stack of insulating layers, but the thickness of the first buffer layer is different from the thickness of one of the first stack of insulating layers. The case, or (2) the material composition of the first buffer layer may be different from the case of an insulating layer stacked for the first time, or the case of (3) having both (1) and (2). The stack may include a third stack and a second buffer layer between the second stack and the third stack. The etching time of the second buffer layer may be greater than the etching time of one of the insulating layers of the third stack under the etching process performed. The boundary layer of each of the first stack and the second stack may be thicker than at least one of the active layer and the insulating layer of the corresponding sub-stack.

The circuit of the first example includes a substrate and a series of counter-gate connections with transistors on the substrate. The tandem column having the transistor and the gate connection includes a first plurality of non-volatile memory cells and a second plurality of non-volatile memory cells. The first plurality of non-volatile memory cells have a first gate length. The second plurality of non-volatile memory cells have a second gate length, and the second gate length is greater than the first gate length. The series of electrical channels connected by the opposite gates have a direction perpendicular to the substrate. In some examples, the circuitry of the first example may include one or more of the following scenarios.

The loop of the first example may include one or more of the following scenarios. The circuit can control the series of anti-gate connections, and the circuit supplies different path voltages to a plurality of non-volatile memory cells and a plurality of transistors. The circuit can include a series of circuit controlled reverse gate connections, wherein the first gate length is less than 0.1 microns and the second gate length is greater than 0.1 microns. The series of gate connections may include a ground select line transistor (GSL transistor) and a series of select line transistors (SSL transistors).

The circuit of the second example can include a substrate, a plurality of stacks of a plurality of semiconductor strips on the substrate, and a plurality of word lines. The plurality of semiconductor strips in the plurality of stacks includes at least one first semiconductor strip and a second semiconductor strip, the first semiconductor strip has a first height, and the second semiconductor strip has a second height, the first height being different from the first Two heights. A plurality of word lines are orthogonally disposed on the plurality of stacks, and the plurality of word lines have a conformal shape on the plurality of stacked surfaces, such that a three-dimensional array of memory elements is formed on a plurality of stacked surfaces and The intersection between the plurality of word lines, and such that the series of the transistor and the gate connection are formed along the semiconductor strips in the plurality of stacks. The tandem of the transistor and the gate connection includes a first reverse gate connection of the non-volatile memory cells and a second reverse gate connection of the non-volatile memory cells. The series of first anti-gate connections has a first height. The series of second anti-gate connections has a second height.

The loop of the second example may include one or more of the following. The different first heights and second heights may cause a first set of electrical characteristics for the series of reversed gate connections in the first semiconductor strip having the first height, and for the second semiconductor strip having the second height The series of gate connections can result in a second set of electrical characteristics, the first set of electrical characteristics being different from the second set of electrical characteristics. The circuit can include a first sense amplifier and a second sense amplifier, and the circuit controls the first set according to the first set of electrical characteristics A sense amplifier is used for electrical measurement, and the circuit controls the second sense amplifier according to the second set of electrical characteristics for electrical measurement. The circuit can also perform the operation of the memory on the reverse connection of the transistor to store the first data on the series of the first anti-gate connection, and use the series of the second anti-gate connection. To correct at least one error in the first data.

Other aspects and advantages of the present invention will be described hereinafter with reference to the detailed description of the embodiments, the appended claims and the appended claims.

67, 68, 69‧‧‧ connection endpoints

100‧‧‧ device

102, 103, 104, 105‧‧‧ active serial

102B, 103B, 104B, 105B, 112B, 113B, 114B, 115B‧‧‧ semiconductor pads

102C1, 102C2, 102C3, 103C1, 103C2, 104C1, 208, 210, 214, 214.1, 214.2, 222, 280, 282, 286, 288, 292.1, 292.2, 294, 296, 299, 302, 306, 366, 442, 482‧‧‧Opening

119‧‧‧Source line terminal

125-1, 125-N‧‧‧ conductor

126, 127‧‧ ‧ gate selection line

128‧‧‧ source line

152‧‧‧ memory material layer

154‧‧‧

202.1, 202.2, 202.3, 202.4‧‧‧ active layers

204.1, 204.2, 204.3, 256, 258, 260, 268, 270, 360, 480 ‧ ‧ insulation

200, 330‧‧‧ Stacking

216, 308, 368‧‧‧ through holes

206, 220, 278, 284, 290, 298, 304, 332, 336, 346, 354, 356, 364‧‧ ‧ mask

224, 226, 228, 230, 232, 234, 228, 331, 334‧‧‧

252.1, 252.2, 252.3, 252.4‧‧‧ times stacking

254, 262, 264, 266‧ ‧ layer matching

272‧‧‧Interlayer conductor

300‧‧‧ structure

310, 358‧‧‧ landing zone

314‧‧‧Insulator

338, 340, 342, 344, 348, 349, 350, 351, 452 ‧ ‧ surface

362‧‧‧Insulation materials

370‧‧‧Contact structure

380, 382, 384, 386, 388, 390, 392, 394, 396, 398, 400, 402, 404, 410, 412, 414, 416, 418, 460, 462, 464, 466, 468, 470, 472 ‧‧step

440, 490, 492‧‧‧ components

446‧‧‧Substrate

450, 477‧‧‧ buffer layer

471, 496‧‧‧Three-dimensional non-volatile memory array

474‧‧‧Vertical channel reverse gate-connected transistor

475‧‧‧Listing

476‧‧‧Sequence selection line

478‧‧‧ Grounding selection line

484, 507‧‧‧ capture structure

509‧‧‧ contact area

486‧‧‧ channel layer

488‧‧‧Insulation core

498‧‧‧Stacking

500, 502‧‧ ‧ semiconductor strips

503‧‧‧Insulated series

504, 506‧‧‧ tandem transistor connected to the gate

508, 510‧‧‧ reversed gate connection

958‧‧‧ Planar Decoder

959‧‧‧ bit line

960‧‧‧Three-dimensional memory array

961‧‧‧ column decoder

962‧‧‧ character line

963‧‧‧ row decoder

964‧‧‧Source selection line

965‧‧ ‧ busbar

966, 968‧‧‧ squares

967‧‧‧ data bus

969‧‧‧ state machine

971‧‧‧ data input line

972‧‧‧ data output line

974‧‧‧Other circuits

975‧‧‧ integrated circuit

BL‧‧‧ bit line

G‧‧‧ gate

GSL‧‧‧ Grounding selection line

H1, H2‧‧‧ height

L1, L2‧‧‧ thickness

N1‧‧‧First space cycle

N2‧‧‧Second space cycle

WL‧‧‧ character line

1 is a perspective view of a semiconductor component of a semiconductor pad including interlayer conductors.

2A, 2B, 2C, 2D, 2E, and 2F are simplified views of the process steps for performing an example of multiple photolithography processes with simple cycles.

3A, 3B, 3C, 3D, and 3E are simplified views of an example of a multiple photolithography process that creates a problem of etch depth during processing during a non-simple cycle.

4A, 4B, 4C, 4D, 4E, 4F, and 4G are diagrams showing a simplified view of a process step for stacking an example of a trim etch process with a simple cycle.

5A, 5B, 5C, and 5D are simplified views of an example of a trim etch process that creates a etch depth during processing with a non-simple cycle.

Figure 6 illustrates an active layer and an insulating layer including alternating periods without a simple period. Schematic diagram of an example of a stacked contact structure.

7 to 25 are schematic views showing an example of forming a contact structure of Fig. 6 using a multiple photolithography process.

Figure 7 is a schematic view showing the stacking of one of the active layer and the insulating layer.

Figure 8 is a schematic view showing the structure of Figure 7 plus a first etch mask.

Figure 9 is a schematic view showing the structure of Figure 8 after etching.

FIG. 10 is a schematic view showing the first etch mask of the structure of FIG. 9 removed.

Figure 11 is a schematic view showing the structure of Figure 10 plus a second etch mask.

Fig. 12 is a schematic view showing the structure of Fig. 11 after etching.

Figure 13 is a schematic view showing the second etch mask of the structure of Figure 12 removed.

Figure 14 is a schematic view showing the structure of Figure 13 plus a third etch mask.

Figure 15 is a schematic view showing the structure of Figure 14 after etching.

Figure 16 is a schematic view showing the third etch mask of the structure of Figure 15 after removal.

Figure 17 is a schematic view showing the structure of Figure 16 plus a fourth etch mask.

Figure 18 is a schematic view showing the structure after the etching of the structure of Figure 17.

Figure 19 is a schematic view showing the fourth etch mask of the structure of Figure 18 removed.

Figure 20 is a schematic view showing the structure of Figure 19 plus a fifth etch mask. Figure.

Figure 21 is a schematic view showing the structure of Figure 20 after etching.

FIG. 22 is a schematic view showing the fifth etch mask of the structure of FIG. 21 removed and showing the via holes formed in the stack.

Figure 23 is a schematic view showing the structure of Figure 22 after deposition of an insulating layer.

Figure 24 is a schematic view showing the portion of the insulating layer of the structure of Figure 23 removed leaving the sidewall insulator in the via.

Figure 25 is a schematic view showing the structure of Figure 24 plus an interconnect conductor to form the contact structure of Figure 6.

26 to 43 are schematic views showing an example of forming a contact structure using a trim etching process.

Figure 26 is a schematic diagram showing the stacking of alternating active and insulating layers with a first etch mask.

Figure 27 is a schematic view showing the structure of Figure 26 after etching.

Figure 28 is a schematic view showing the replacement of the first etch mask of the structure of Figure 27 with the second etch mask.

Figure 29 is a schematic view showing the structure of Figure 28 after etching.

Figure 30 is a schematic view showing the second etch mask of the structure of Figure 29 removed.

Figure 31 is a schematic view showing the structure of Figure 30 plus a third etch mask.

Figure 32 is a schematic view showing the structure after the etching of the structure of Figure 31.

Figure 33 is a schematic view showing the third trim mask of the structure of Figure 32 after the first trimming.

Figure 34 is a schematic view showing the structure of Figure 33 after etching.

Figure 35 is a schematic view showing a second trimming of the third etch mask of the structure of Figure 34.

Figure 36 is a schematic view showing the structure of Figure 35 after etching.

Figure 37 is a schematic view showing the third etch mask of the structure of Figure 36 removed.

Figure 38 is a schematic view showing the deposition of the insulation/stop layer of the structure of Figure 37.

Figure 39 is a schematic view showing the deposition of the insulating material for the structure of Figure 38.

Figure 40 is a schematic view showing the structure of Figure 39 plus a fourth etch mask.

Figure 41 is a schematic view showing the structure after the etching of the structure of Figure 40.

Figure 42 is a schematic view showing the through hole formed in the structure after the fourth etch mask of the structure of Fig. 41 is removed.

Fig. 43 is a view showing the formation of the interlayer conductor in the through hole in the structure of Fig. 42.

Figure 44 is a simplified flow diagram showing the schematic steps of a method for forming the contact structure described below with respect to Figures 7 through 25.

Figure 45 is a simplified flow diagram showing the schematic steps of a method for forming the contact structure described below with respect to Figures 26 through 43.

Figure 46 is a simplified flow diagram showing the schematic steps of a method for forming the contact structures described below with respect to Figures 7 through 25 and Figures 26 through 43.

Figure 47 shows a simplified block diagram of the integrated circuit.

48 to 63 are schematic views showing further examples of forming a contact structure.

Figure 48 is a schematic illustration of how etching through the opening in the etch mask can result in etched openings having different depths.

Figure 49 is a schematic illustration of the result of an overetch process for the structure of Figure 48 such that the etched openings completely traverse the underlying insulating layer through portions of the active layer but still at different depths.

Figure 50 illustrates that the lack of uniformity of the layer and/or etch process results in the etched openings extending to different layers rather than the same layer.

Figure 51 is a schematic view showing a stack of an active layer and an insulating layer having an etch mask over the upper insulating layer, similar to the structure of Figure 8.

Figure 52 is a schematic view showing the structure of Figure 51 after etching through the first stack of the uppermost layer and into the uppermost first buffer layer of the portion.

Figure 53 is a schematic view showing the structure of Figure 52 after etching through the first buffer layer.

Figure 54 is a schematic view showing the structure of Figure 53 after etching through the second stack and into a portion of the second buffer layer.

Figure 55 is a schematic view showing the structure of Figure 54 after etching through the second buffer layer.

Figure 56 is a schematic view showing the structure of Figure 55 after being etched through the third stack and into a portion of the third buffer layer.

Figure 57 is a schematic view showing the passage of the third buffer layer after etching the structure of Figure 56.

Figure 58 is a schematic view showing the structure of Fig. 57 after etching through the fourth stack of the lowermost layer and into the fourth buffer layer of the lowermost layer of the portion.

Figure 59 is a diagram showing the structure of Fig. 58 after etching through the lowermost layer. Schematic diagram in the four buffer layers.

Figure 60 is a view showing an etched opening of an active layer which has been formed by stacking to the uppermost layer of each sub-stack, similar to the structure of Figure 16, to prepare an active layer for processing each sub-stack to form, for example, Schematic diagram of the stepped structure of the landing zone on the sub-stacked active layer described in Figures 17-25.

Fig. 61 is a schematic view showing a structure similar to that of Fig. 52 but having an upper boundary layer adjacent to the covered buffer layer thicker than the example of Fig. 52 to enlarge the process window.

Figure 62 illustrates the etching of the structure of Fig. 61 through the covered buffer layer, the etched opening system is completely traversed through the buffer layer, and the thickness is increased to accommodate the over-etched upper boundary layer to expand Schematic diagram of the process window.

Figure 63 is a flow chart showing an example of a method for forming a stepped contact structure.

Figure 64 is a cross-sectional view of a three-dimensional non-volatile memory array including a vertical channel and a gate connected transistor.

Fig. 65 is a top view showing the structure of Fig. 64.

Figure 66 is a schematic diagram showing the representative of the reverse gate train shown in Figure 64.

Figure 67 is a diagram showing a three-dimensional array of anti-gate memory elements formed on the intersection between the surface of the stack and the word line along the line 67-67 of Fig. 68 and having alternating semiconductors on the substrate. A cross-sectional view of a three-dimensional non-volatile memory array of strips and insulators.

Figure 68 is a top plan view showing the stack of alternating conductors and insulated strings in the direction of the word lines shown in the structure of Figure 67.

Figure 69 is a cross-sectional view similar to line 69-69 of Figure 68 taken along line 68.

Figure 70 is a schematic diagram showing a representation of a non-volatile memory cell and a gate connection of a lower first height formed by a structure perpendicular to the plane of Figure 69 and having the structure of Figures 67-69.

Figure 71 is a schematic diagram showing a representation of a non-volatile memory cell and a gate connection of a non-volatile memory cell having a higher second height by the structure of Figures 69 to 69, which is perpendicular to the plane of Figure 69.

For a detailed description of various embodiments of the invention, please refer to the drawings. Most of the disclosures below need to be accompanied by reference to specific embodiments of the embodiments and methods. It is understood that the invention is not limited to the specific disclosed embodiments and methods, and the invention may be practiced with other features, elements, methods and embodiments. The disclosure of the present invention may be made by way of examples, but the embodiments are not intended to limit the scope of the present invention. Other possible equivalent embodiments will be apparent to those of ordinary skill in the art in view of this disclosure. Unless specifically stated otherwise, the specific relational terms used in the present invention, such as "parallel," "aligned," "having consistent characteristics," or "in the same plane", represent a particular relationship that is limited in process and transformation manufacturing. Unless specifically described, when the components are described by "coupling", "linking", "contacting" or "contacting each other", these constituent objects do not require physical direct contact with each other. The same elements in different embodiments are generally denoted by the same element symbols.

FIG. 1 illustrates a three-dimensional semiconductor device (such as a memory device) 100. A perspective view of an example, as described in the application of US Publication No. 2012/0182806, filed on April 1, 2011, entitled "Three-Dimensional Array with Alternating Memory String Direction and String Selection Structure" Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures. In order to more clearly illustrate the active layer, the various insulating materials formed are not shown, and the active layer includes semiconductor stripes, semiconductor pads for bonding the interlayer conductors, and other components. The three-dimensional semiconductor device 100 is formed to cover a substrate (not shown) having an insulating layer (not shown) formed thereon. The substrate can include one or more integrated circuits as well as other structures. The figure shows that the active layer stack has four semiconductor pads 102B, 103B, 104B and 105B at the proximal end and four semiconductor pads 112B, 113B, 114B and 115B at the far end of the stack, but the active layer and corresponding The number of semiconductor pads can extend to N layers of any number, where N is an integer greater than one. As shown, the three-dimensional semiconductor device 100 includes a stack of active strings (e.g., 102, 103, 104, 105) that are separated by an insulating material. The semiconductor pads (eg, 102B, 103B, 104B, 105B) terminate the series in the corresponding active layer. As shown, the semiconductor pads 102B, 103B, 104B, and 105B are electrically coupled to the active layer for bonding to a decoding circuit to select layers in the array. The semiconductor pads 102B, 103B, 104B, and 105B may be patterned together while the active layer is patterned, with the exception of the vias of the interlayer conductors. In the illustrated embodiment, each active string comprises a semiconductor material suitable for use as a channel region. The tandem system is ridge-shaped and extends over the Y-axis in the figure such that the active series 102, 103, 104, 105 can constitute a body, and the body includes a flash The channel region of the memory cell string, such as a horizontal reverse gate (NAND) string configuration. As shown, in this example a memory material layer 152 is applied to a plurality of active serial stacks. In other examples, the memory material layer 152 is applied to at least the sidewalls of the active series. In other embodiments, the active string can be configured to vertically reverse the word lines in the gate. For example, please refer to the application of U.S. Patent No. 8,363,476, filed on January 19, 2011, entitled "Memory Device, Manufacturing Method and Operating Method of The Same" (Memory Device, Manufacturing Method and Operating Method of The Same) "."

One end of each active tandem stack terminates in a semiconductor pad while the other end terminates in a source line. Thus, the active series 102, 103, 104, 105 terminate at the near end by the semiconductor pads 102B, 103B, 104B, and 105B, and terminate at the source line terminal on the far end of the active string through the gate select line 127. 119. The active series 112, 113, 114, 115 terminate at the far end by the semiconductor pads 112B, 113B, 114B, and 115B, and the source line terminals (such as the source line 128) traverse at the near end of the active string. Pass gate selection line 126.

In the embodiment of Figure 1, a plurality of conductors 125-1 through 125-N are arranged orthogonally over a plurality of active serial stacks. In a trench defined in a plurality of stacks, the conductors 125-1 through 125-N have surfaces that are conformal with the plurality of active tandem stacks, and active strings 102, 103 on the stack The intersections between the sides 104, 105 and conductors 125-1 through 125-N (e.g., word line or source select line) define a multi-layer array of interface regions. As shown, a layer 154 of a telluride (eg, tungsten telluride, cobalt antimonide, titanium telluride, or nickel telluride) may be formed on the conductor (eg, The upper surface of the word line or source selection line).

Depending on the implementation, the memory material layer 152 can include a multilayer dielectric charge storage structure. For example, a multilayer dielectric charge storage structure includes a tunneling layer containing hafnium oxide, a trapping layer containing tantalum nitride, and a blocking layer containing hafnium oxide. In some embodiments, the tunneling layer in the dielectric charge storage layer can include a first tantalum oxide layer having a thickness of less than about 2 nanometers, a tantalum nitride layer having a thickness of less than about 3 nanometers, and a thickness of less than about 3 nanometers. The second layer of ruthenium oxide. In other embodiments, the memory material layer 152 can include only a charge trapping layer without a tunneling layer or isolation layer.

In another embodiment, for example, an anti-fuse material having a thickness of 1 to 5 nanometers, such as cerium oxide, cerium oxynitride or other cerium oxide, may be used. Other anti-fuse materials such as tantalum nitride can also be used. In an embodiment for an antifuse, the active series 102, 103, 104, 105 may be a first conductivity type (e.g., p-type) semiconductor material. The conductor (e.g., word line or source select line) 125-N may be a second conductivity type (e.g., n-type) semiconductor material. For example, active strings 102, 103, 104, 105 can be fabricated using p-type polysilicon, while conductors 125-N can be fabricated using relatively heavily doped n+ type polysilicon. In embodiments for antifuse, the width of the active string should provide sufficient space for the depletion region to support diode operation. Thus, a memory cell comprising a rectifier is formed in a three-dimensional array of intersections between the polysilicon series and the wires, and the rectifier is connected between the anode and the cathode by a pn junction of the writable antifuse layer. Formed.

In other embodiments, different writable resistive memory materials can be used as memory materials, including metal oxides such as tungsten oxide or doped metal oxides on tungsten. Certain such materials may form devices to be written and erased under a variety of voltages or currents, and may perform multi-bit storage of each memory cell.

As shown in FIG. 1, one side of the semiconductor pads 102B, 103B, 104B, and 105B is coupled to the active series in a corresponding layer of the device, such as by continuous patterning of the semiconductor layers. In some embodiments, both sides of the pad may be coupled to a active string in the corresponding layer. In other embodiments, the pads may be coupled to the active string using other materials and structures that allow electronic communication of the voltage and current required for operation of the device. Moreover, in the present embodiment, a covered insulating layer (not shown) and a semiconductor pad other than the lowest pad among the semiconductor pads 102B, 103B, 104B and 105B include openings 102C1, 102C2, 102C3, 103C1, 103C2, 104C1, these openings expose a landing zone on the underlying liner to form a stepped structure.

One of the methods of joining the interlayer conductors to the active layers in the stack can be found in the multiple lithographic-etch process disclosed in U.S. Patent No. 8,383,512, entitled "Method for Making Multilayer Connection Structures" (Method for Making Multilayer Connection Structure), the disclosure of which is incorporated herein by reference. Another method of joining the interlayer conductors to the active layers in the stack can be referred to as a trim-etch process, as disclosed in U.S. Application Serial No. 13/735,922, filed on Jan. 7, 2013, entitled " Method for forming intermediate connectors for conductive layers of stacked structures (Method For Forming Interlayer Conductors to a Stack of Conductor Layers), the disclosure of which is incorporated herein by reference.

2A through 2F are simplified diagrams showing an example of a multiple photolithography process for fabricating a contact structure. FIG. 2A illustrates a stack 200 of alternating active layers 202 and insulating layers 204, and a first etch mask 206 is formed on the uppermost active layer 202.1. The first etch mask 206 has a first etch mask opening 208. The active layer 202 can be formed of different kinds of conductive materials, such as doped semiconductors, metals, and combinations thereof. Fig. 2B shows the structure after etching through a layer of an active layer 202 and an insulating layer 204 in Fig. 2A. This first etch begins at the first etch mask opening 208 to form a first etch opening 210. After stripping the first etch mask 206, see FIG. 2C, a second etch mask 212 is formed over the stack 200, see FIG. 2D. The second etch mask 212 has a second etch mask opening 214, wherein one second etch mask opening 214 is aligned with the first etch mask opening 208 and the other second etch mask opening 214 Not aligned with the first etch mask opening 208. Next, as shown in FIG. 2E, the second etching is started and passed through two levels. As a result, vias 216 are formed and extend to the second, third, and fourth active layers 202.2, 202.3, and 202.4, and the first active layer 202.1 is exposed by removing the second etch mask 212, as shown in FIG. Shown.

The stack 200 is formed of an active layer 202 having a common etch characteristic and an insulating layer 204 having a common etch characteristic. In this example, active layer 202 is formed from the same conductive material and has the same nominal thickness. Similarly, insulating layer 204 is formed from the same insulating material having the same nominal thickness. Therefore, each pair of insulating layer and active layer will have a uniform etching time for the etching process performed. This configuration in which the insulating layer is paired with the active layer It can mean a stacked layer having a simple period.

3A to 3D are diagrams showing an example of a stacked layer having no simple period similar to the 2A to 2F drawings. In this example, the third insulating layer 204.3 is thicker than the insulating layer 204.1 or 204.2 thereon. Therefore, it is desired to etch the first active layer 202.1, the first insulating layer 204.1, the second active layer 202.2, and the second insulating layer 204.2 passing through the uppermost boundary at the second etch mask opening 214.1 to form the via 216.1. The time required for the second etch mask opening 214.2 is only sufficient to etch through the portion of the third insulating layer 204.3 to form the via 216.2.

As described herein, a structure having a non-simple period in which the active layer and/or the insulating layer have different etching times is provided, typically because the active layer and/or the insulating layer are composed of different etching characteristics. Or a material of different thickness, or the active layer and / or insulating layer is composed of a combination of different materials and different thicknesses.

4A to 4G illustrate a simplified example of a trim etching process. An etch mask 220 is formed over the uppermost active layer 202.1 and has an etch mask opening 222 to expose a portion 224 of the uppermost active layer. The first etch step is etched through the active layer 202.1 and the insulating layer 204.1 to expose a portion 226 of the active layer 202.2, as shown in FIG. 4B. Next, during the first trimming step, a portion of the etch mask 220 is removed to expose another portion 228 of the active layer 202.1. As shown in FIG. 4D, the next etch step is etched through an active layer 202 and an insulating layer 204 to expose a portion 230 of the active layer 202.2 and a portion 232 of the active layer 202.3. Next, referring to FIG. 4E, during the second trimming step, a portion of the etch mask 220 is removed to expose a portion 234 of the active layer 202.1. This step is followed by another etching step, see Figure 4F. Each of the portions 234, 230 and 232 passes through an active layer and an insulating layer to form the structure of the 4F. FIG. 4G illustrates the step of forming a plurality of landing areas 238 for connection to interlayer conductors at different active layers 202.1-202.4 after stripping the remaining etch mask 220 in FIG. 4F. Structure 236.

5A to 5D are diagrams showing an example of a stacked layer having no simple period similar to the 4A to 4G drawings. In this example, the second insulating layer 204.2 is thicker than the insulating layer above or below it. During the etching step of Figure 5D corresponding to the etching step of Figure 4D, the etching is performed sufficient to etch portions 228 of active layer 202.1 and etched into portions of underlying insulating layer 204.1 to expose portions 230 of active layer 202.2 . However, as shown in FIG. 5D, since the thickness of the second insulating layer 204.2 is large, it takes a long time to etch through the second insulating layer 204.2, and the etching here is only enough to etch the portion of the second insulating layer 204.2. . Therefore, unlike the 4D map, the third active layer 202.3 is not exposed by the second etching step. However, if the second etching step is continued to etch through the second insulating layer 204.2 until the third active layer 202.3 is exposed, the exposed portion 230 of the active layer 202.2 may be damaged or destroyed.

Based on the above, an example of the contact structure 250 in the active layer and the insulating layer stack without a simple period is shown in FIG. Contact structure 250 includes a stack 200 of alternating active layers 202 and insulating layers 204. Stack 200 also includes a secondary stack 252 having an upper boundary active layer 202.1. Sub-stack 252 also includes a first layer pair 254 that is positioned between the insulating layer and active layers 202, 204 below each of the upper boundary active layers 202.1. In the example of Figure 6, there are four sub-stacks 252 labeled 252.1 to 252.4. The pair 254 of insulating layers and active layers 202, 204 have a consistent first etch time in the etching process performed. Stack 200 also includes sub-stack insulation layers 256, 258, and 260 between sub-stacks 252. In this example, the insulating layers 256 and 260 have the same composition, typically cerium oxide (SiO ₂ ), and the composition of the secondary stacked insulating layer 258 is not the same, such as tantalum nitride (SiN). The thickness and composition of the sub-stack insulation layers 256, 260 are substantially the same, and thus each has substantially the same etch characteristics. However, the thickness of the insulating layers 256 and 260 is greater than the thickness of the insulating layer 204. Therefore, the required time for etching through the insulating layers 256 and 260 is greater than the time required to etch through the insulating layer 204 during the etching process. .

The secondary stacked insulating layer 256 forms a second layer pair 262 with the underlying active layer 202.1, and the second layer pair 262 has a second etch time during the etching process. The sub-stack insulation layer 260 and the lower adjacent active layer 202.1 form a third layer pair 264 having a third etch time in the middle of the etch process, wherein the third etch time is equal to the second etch time. The secondary stacked insulating layer 258 forms a fourth layer pair 266 with the underlying active layer 202.1, and the fourth layer pair 266 has a fourth etch time during the etching process. The fourth etching time is different from any of the first to third etching times. The etch times for the different layer pairs 254, 262, 264, 266 may be the same or different, using a wide range of different materials having different etch rates in combination with the same or different thicknesses of insulating and active layers.

The contact structure 250 also includes an upper insulating layer 268 and a lower insulating layer 270. The upper insulating layer 268 covers the active layer 202.1 of the sub-stack 252.1. The lower insulating layer 270 is located below the active layer 202.4 of the sub-stack 252.4. Both the upper insulating layer 268 and the lower insulating layer 270 may be composed of cerium oxide. a set of interlayer conductors 272 extending Contact is made with the respective active layers 202 of each of the sub-stacks 252 by a superior insulating layer 268 in a stair step manner. Each of the interlayer conductors 272 is surrounded by a sidewall insulator 314 which may be composed of tantalum nitride.

7 through 25 will show an example of the steps of fabricating the contact structure 250 as shown in Fig. 6 using the multiple photolithography process as discussed in Figs. 2A through 2F.

Figure 7 shows that the stack 200 includes sub-stacks 252.1 through 252.4 between the upper insulating layer 268 and the lower insulating layer 270, the sub-stack being separated by the sub-stack insulating layers 256, 258, 260. Figure 8 shows the structure of Figure 7 having a first etch mask 278 and a first etch mask opening 280 formed therein. FIG. 9 shows the result of etching the structure of FIG. 8 through the upper insulating layer 268 in the opening 280 to etch down the upper active layer 202.1 of the sub-stack 252.1 in the layer 268 to form the first etched opening 282. . Fig. 10 shows the structure after the first etch mask 278 of the structure of Fig. 9 is removed.

11 shows a structure in which the structure of FIG. 10 is formed to form a second etch mask 284 covering one half of the first etch opening 282 and having a second etch mask opening 286 aligned with the other half of the etch opening 282. In Fig. 12, the structure of Fig. 11 is etched through opening 286, and conventionally etched down to the upper active layer 202.1 of the sub-stack 252.3 to form a second etched opening 288. In FIG. 13, the second etch mask 284 has been removed, exposing the first etch opening 282.

Figure 14 shows that after the structure of Figure 13 is formed into a third etch mask 290, there is a third etch mask opening 292.1 exposing one half of the first etch opening 282 and exposing one half of the second etch opening 288. The third etch mask has the structure of the opening 292.2. Figure 15 shows the structure of Figure 14 on the third etch mask The holes 292.1 are etched through the structure after the first stacking of 252.1 and the sub-stacking of the insulating layer 256. Figure 15 also shows the result of etching the third etch mask opening 292.2 through the third stack 252.3 and the sub-stack insulating layer 260. The etching proceeds to form a third etch opening 294 and a fourth etch opening 296. Fig. 16 shows the structure after the third etching mask 290 of the structure of Fig. 15 is removed.

Figure 17 shows the structure of Figure 16 forming a first etched opening 282, a second etched opening 288, a third etched opening 294, and an opening 299 of the fourth etched opening 296 that are exposed. The structure of the four etch masks 298. Figure 18 shows the results of etching through the upper boundary active layer 202.1 and the underlying insulating layer 204.1 in each of the sub-stacks 252.1, 252.2, 252.3, and 252.4. The above etching forms a portion of the etched structure 300, and FIG. 19 shows the result of removing the fourth etched mask 298. The partially etched structure 300 has openings 302 that extend into different levels in the stack 200. Figure 20 shows the structure of Figure 19 forming a fifth etch mask 304 to alternately cover and expose the two openings 302. The fifth etch mask 304 has an opening 306 that overlaps the exposed opening 302 of FIG. Figure 21 shows the result of performing the second etching process such that the two active layers 202 and the two insulating layers 204 are etched through the respective openings 306.

Figure 22 shows the result of stripping the structure of Figure 21 from the fifth etch mask 304 to reveal vias 308 that extend down to the landing zone 310 of the active layer 202. The structure of Fig. 22 has a stepped configuration of the landing zone 310. Figure 23 shows an insulating layer 312 (e.g., tantalum nitride) deposited on the structure of Figure 22, thus forming a layer of sidewall insulators 314 along each via 308. In FIG. 24, the insulating layer 312 overlapping the upper insulating layer 268 and the bottom of each of the vias 308 is removed to expose the landing zone 310. Figure 25 shows the through hole 308 of Figure 24 The structure after filling with a conductor such as tungsten (W) extends from the upper surface 318 of the upper insulating layer 268 to the landing region 310 of each active layer 202 to form the interlayer conductor 272, thus forming the contact structure 250 of FIG. .

FIGS. 26 through 43 illustrate an example of the steps of fabricating a contact structure using a trimming etch process described with respect to the simplified examples discussed above in FIGS. 4A through 4G.

Figure 26 illustrates a stack 330 identical to the stack 200 of Figure 7 except that the upper insulating layer 268 is absent. A first etch mask 332 is formed over the stack 330 to cover a portion 331 of the active layer 202.1 of the first stack 252.1 and expose about half of the active layer. During the first etching step (the result of which is shown in FIG. 27), the portion of the stack 330 exposed by the active layer 202.1 is etched through half of the sub-stack, that is, by the first stack 252.1, the second stack The insulating layer 256, the second stack 252.2, and the sub-stack insulating layer 258, thus exposing a portion 334 of the boundary active layer 202.1 over the third stack 252.3.

Figure 28 shows a second etch mask 336 for the structure of Figure 27 to cover about half of the portion 331 and about half of the portion 334. The exposed regions of portion 331 are then etched through sub-stack 252.1 and sub-stacked insulating layer 256. The exposed regions of portion 334 are etched through sub-stack 252.3 and sub-stacked insulating layer 260. The structure of Fig. 29 is formed through the above etching process, and has surface regions 338, 340, 342, and 344. In Fig. 30, the second etch mask 336 has been removed from the structure in Fig. 29.

Figure 31 shows a third etch mask 346 formed over surfaces 338 through 344 and exposing a portion of each surface. The exposed portions of these surfaces 338 to 344 are etched through an active layer 202 and an insulating layer 204 to form the 32nd The figure has a structure that exposes surfaces 348 to 351. Thereafter, as shown in FIG. 33, the third etch mask 346 is trimmed to form a trimmed etch mask 354, and the trimmed etch mask 354 exposes the boundary active layer of each of the sub-stacks 252.1 to 252.4. The other part of 202.1. Next, another etching step is performed to etch through an active layer 202 and the underlying insulating layer 204. The etching results are shown in FIG. Figure 35 shows the result of trimming the trimmed etch mask 354 to form a trimmed etch mask 356 that again exposes additional portions of the boundary active layer 202.1 above each of the sub-stacks 252.1 through 252.4. Again, another etching step is performed to etch through an active layer 202 and the underlying insulating layer 204. The etching results are shown in FIG.

Figure 37 shows the result of forming the landing zone 358 in a stepped configuration after removing the trimmed etch mask 356 from the structure of Figure 36. As shown in FIG. 38, deposition of an insulating layer 360 is then performed. The insulating layer 360 is sometimes referred to as a stopping layer 360, which may be, for example, tantalum nitride. Next, as shown in Fig. 39, the structure of Fig. 38 is covered with an insulating material 362 formed of, for example, cerium oxide. Next, a fourth etch mask 364 is formed over the insulating material 362, and the fourth etch mask 364 has an opening 366 aligned with the landing zone 358. The via 368 is formed by insulating material 362 and insulating layer 360 down to landing zone 358. The above description is shown in Fig. 41. Figure 42 shows the structure after the structure of Figure 41 is removed from the fourth etch mask 364. Figure 43 shows an interlayer conductor 272 formed in the via 368 to form a contact structure 370 which may be comprised of tungsten (W).

Figure 44 is a simplified flow chart for carrying out an overview of the basic steps of the method of forming the contact structure described in Figures 7 through 25 above. In the steps 380, alternating active layers are formed with a stack 200 of insulating layers 202 and 204. At step 382, a plurality of openings 294, 288, and 296 are etched into the stack, and the openings are stopped on the active layer 202.1 of the upper boundary layer. At step 384, the openings selected in openings 294, 288, and 296 are etched to increase the depth to form vias 308. In steps 386 and 388, insulator 314 is formed in vias 308 and openings 294, 288, and 296 that are not etched. Next, an interlayer conductor 272 is formed in step 390. The interlayer conductor 272 is connected to the landing zone 310 of the active layer 202.

Figure 45 is a simplified flow chart for carrying out an overview of the basic steps of the method of forming the contact structure described in Figures 26 through 43 above. At step 392, alternating active layers are formed with a stack 330 of insulating layers 202 and 204. At step 394, the stack 330 is then etched to expose portions 338, 342, and 344 of the boundary active layer 202.1 above the secondary stack 252. Portions 338, 342, and 344 are also referred to as surface areas 338, 342, and 344. At step 396, the exposed portions are etched to expose the active layers 202.2, 202.3, and 202.4 below the upper boundary active layer 202.1 and to form a stepped structure. At step 398, an insulating layer 360 is formed over the stepped structure. At step 400, insulating layer 360 is covered by insulating material 362. At step 402, vias 368 are formed by insulating material 362 and insulating layer 360. At step 404, interlayer conductors 372 are formed in vias 368 to form contact structures 370.

Figure 46 is a simplified flow chart for carrying out an overview of the basic steps of the method of forming the contact structure described in Figures 7 through 25 and Figures 26 through 43 above. At step 410, the stacks 200, 330 of alternating active and insulating layers 202 and 204 are formed by forming a first stack, a second stack, a third stack, and a fourth stack 252. Each sub-stack 252 includes an insulating layer 204 Separate active layer 202. The active layer of each sub-stack includes an upper boundary active layer 202.1. At step 412, the first stacked insulating layer, the second stacked insulating layer, and the third stacked insulating layer 256, 258, and 260 are formed between the sub-stacks 252, in the etching process performed, the second stacked The etching time of at least two of the insulating layers is different from the etching time of the sub-stacked insulating layer 204. At step 414, the upper boundary active layer 202.1 is processed. After processing the upper boundary active layer 202.1, the other active layers 202.2 through 202.4 are processed in step 416 to form a stepped structure as shown in FIGS. 22 and 42. At step 418, interlayer conductors 272 are formed to extend to landing regions 310, 358, and the interlayer conduction systems are separated from each other by an insulating material.

Figure 47 is a simplified block diagram of the integrated circuit. The integrated circuit 975 includes a 3D NAND flash memory array 960 having a structure similar to that of FIG. 1, for example, having a high density and a narrow pitch on a semiconductor substrate. A bit line (global bit line). A row of decoder 961 is coupled to a plurality of word lines 962 and arranged along a row in memory array 960. A row decoder 963 is coupled to a plurality of source lines (SSL line) 964 and configured in a memory array 960 along a column corresponding to the stack for use in the memory array 960. The memory cells in the cell read data or write data. A plane decoder 958 is coupled to a plurality of planes in the memory array 960 via bit lines 959. The address is supplied to the row decoder 963, the column decoder 961, and the plane decoder 958 on the bus 965. In this example, the sense amplifier and data input structures in block 966 are coupled to row decoder 963 via data bus 967. Data department The data input structure in block 966 is supplied from the input/output port on the integrated circuit 975 via the data-in line 971 or from the internal and external sources of the other integrated circuit 975. In the illustrated embodiment, the other circuit 974 includes an integrated circuit, such as a general purpose processor or a special purpose application circuit, or a system chip (system- The on-a-chip function is integrated by the anti-gate flash memory cell array. The data is supplied from the sense amplifier in block 966 to the input/output port on the integrated circuit 975 via the data output line 972, or to other data objects internal or external to the integrated circuit 975.

The controller employed in this example uses a bia arrangement state machine 969 to control the generation or supply of a bias configuration supply voltage via a voltage supply or supply in block 968, such as reading. , erase, write, erase verification, and write verification. The controller can employ conventional, purpose-specific logic circuits. In another embodiment, the controller includes a general purpose processor that can be implemented in the same integrated circuit and that can execute a computer program to control component operation. In yet another embodiment, the controller can use an integration of a special purpose logic circuit and a general purpose processor.

Figures 48 to 63 show yet another example of how to form a contact structure such as a stepped structure of a landing zone.

The 48th to 51th drawings provide a common problem of the problems caused by the lack of uniformity in the layers when etching a plurality of layers, or the lack of uniformity in the etching process, or the above two The problem that arises. In the layer The lack of consistency can be due, for example, to changes in at least one of the thickness and material composition of the layer.

Figure 48 illustrates a simple example of a stacked component 440 having an upper insulating layer 268 and alternating active and insulating layers 202,204. The etch mask 278 over the upper insulating layer 268 has an etch mask opening 280 that is formed by etching the mask opening 280. Figure 48 shows how etching through the etch mask opening 280 in the etch mask 278 can result in the etched openings 442 having different depths due to lack of uniformity issues.

Figure 49 shows the result of an overetch process for the structure of Figure 48 such that the etched openings 442 completely traverse through the active layer 202, but are still in the lower insulating layer 204 of portions of different depths. When the thickness of the layers 202, 204 is relatively large, the lack of uniformity in the etching process and layer thickness can have minimal impact. However, as the thickness of the layer is reduced, the process window is also reduced, so the lack of uniformity in both the etch process and the layers 202, 204 may cause the etched opening 442 not to extend to the appropriate layer.

Figure 50 illustrates an example of a relatively thin stacked component 440 of layers 202,204. The thickness of layers 202, 204 is continuously reduced to increase component density. The etched openings 442 extend to different active layers 202 due to the lack of uniformity of one or both of the layers 202, 204 and the etch process, rather than the same active layer 202 as required in this example. That is, when less or thicker layers are used, sometimes greater tolerance is provided in the etch depth of the etched openings 442, and the use of many thinner layers is generally not possible.

Fig. 51 shows a structure similar to Fig. 8. The figure shows that the stack 200 extends over the substrate 446 and includes a sub-stack 252, which has four in this example. The sub-stack, each sub-stack has an active layer 202 and an insulating layer 204, and has an etch mask 278 over the upper insulating layer 268, similar to the structure in FIG. The uppermost layer of each sub-stack 252 is sometimes referred to as the upper boundary layer of the sub-stack. The active layer may be composed of, for example, a conductor or a semiconductor. In the following examples discussed in relation to Figures 51 through 60, the secondary stack begins and ends with the active layer 202 separated by an insulating layer 204. The sub-stack 252 is separated by a buffer layer 450, which is similar to the insulating layer 204, and is formed of an electrically insulating material. In some examples, the sub-stack 252 can begin and end with a layer of insulating material separated by a layer of conductor or semiconductor material. In such an example, the upper boundary layer can be an insulating layer.

Fig. 52 shows the etching of the structure of Fig. 51 through the sub-stack of the uppermost layer and into the uppermost buffer layer 450 of the portion. Due to the etching process and the consistency of the composition and thickness of the buffer layer 450, the etched openings 442 extend to different depths in the buffer layer 450. After the structure of Fig. 52 is etched and passed through the uppermost buffer layer 450, a uniform etched surface 452 is formed on the upper boundary layer 202, and the resulting structure is shown in Fig. 53.

Fig. 54 shows the structure after etching the structure of Fig. 53 through the next sub-stack 252 and partially entering the next buffer layer 450, similar to the process of Fig. 52. Figure 55 shows a structure after etching the structure of Figure 54 through the next buffer layer 450, similar to the process of Figure 53, forming a uniform etched surface 452 at the upper boundary layer 202. The etching steps similar to those in Figures 52 and 53 are continued in Figures 56 and 57, and are also continued in Figures 58 and 59. As shown in FIG. 59, the etched opening 442 extends to the substrate 446. By forming a uniform etched surface 452 at the upper boundary layer 202 of each sub-stack 252, the problem with respect to the etch depth discussed in Figure 50 above is addressed. that is, During etching of the overlapping sub-stacks 252, the resulting difference in depth of the etched openings 442 is reduced while etching through the buffer layer 450 to form a uniform etched surface 452 at the upper boundary layer 202.

Figure 60 illustrates a stack 200 similar to that of Figure 16, wherein the openings 442 are formed by stacking onto the upper boundary active layer 202 of each sub-stack 252, one of each active layer in the sub-stack. The active layer 202 of each sub-stack 252 is processed to pass through the etched opening 442 of FIG. 60 to form a stepped structure of the landing zone on the active layer 202 of the sub-stack 252, such as from 17th to 25th. Shown.

Fig. 61 is similar to the schematic of Fig. 52, however, the upper boundary layer 202a overlapping the buffer layer 450 is thicker than the example of Fig. 52. This expands the associated process window. The etched opening 442 is traversed through the sub-stack 25 and through a portion of the buffer layer 450.

Figure 62 shows the structure of the buffer layer 450 after etching the structure of Figure 61. The etched opening 442 completely traverses through the buffer layer 450 and into the upper boundary layer 202a of increased thickness. The increased thickness of the upper boundary layer 202a is based on a selective etch for material confirming that the selected etch process is designated as the buffer layer 450, and specifies that only the material of the upper boundary layer 202 is etched minimally, In some cases, completely etching through the buffer layer 450 will still cause the underlying upper boundary layer 202 to be etched. In one example, the thickness of the upper boundary layer 202a can be about 1.5 times the thickness of the other active layers 202 of the stack 252. The excess thickness of the upper boundary layer 202 accommodates this excessive etching, thereby expanding the process window.

Examples of methods for forming a stepped contact structure can be as follows Said to proceed. A flow chart showing the basic steps and the steps of some other embodiments is shown in Figure 63. The stack 200 consisting of alternating active layers 202 and insulating layers 204 can be performed by the following steps.

Step 460: Form a first stack 252 that includes N active layers 202 and separated by an insulating layer 204.

Step 462: Form a second stack 252 on the first stack, the second stack includes M active layers and separated by an insulating layer. The second stack has an upper boundary layer. In the example of FIG. 51, the upper boundary layer is also an active layer 202.

Step 464: Form a first buffer layer 450 and a second buffer layer. The first buffer layer 450 is located between the first stack and the second stack. The second buffer layer is located below the first stack. In some examples, the first stacking features a first spatial period N1, and the second stacking features a second spatial period N2, see Figure 51, in some examples , N1 is equal to N2. In some examples, each of the first stack and the second stack includes the same number of active layers. In some embodiments, for an individual etch process, the etch time of the buffer layer is greater than the etch time of the second stack of insulating layers. In some examples, having (1) the first stacked buffer layer is composed of the same material as the first stacked insulating layer, but the thickness of the first stacked buffer layer is different from that of the first stacked insulating layer. In the case of the thickness, or (2) the material composition of the first stacked buffer layer is different from the case of the first stacked insulating layer, or (3) has both (1) and (2). In some examples, the thickness of the buffer layer is greater than the thickness of the active layer in the first stack, such as at least greater than 1.5 times. In some examples, the forming step of the first stacking and the second stacking may be performed such that at least one of the active layer and the insulating layer of the corresponding first stack and the second stack of the corresponding second stack More thick.

Step 466: the upper layer of the first stack is exposed to a set of via holes by etching, using a first etching process to form a first set of etched vias through the second stack and stopped at the first buffer layer or through the first The first set of etched vias that are stacked twice and stopped in the first buffer layer, see Figure 52. And a second etching process is used to etch the upper layer through the first buffer layer to the first stack, see Figure 53. In some embodiments, an etch mask 278 is formed over the second stack, the etch mask having an etch mask opening 280, the first etch process being performed by etching the mask opening.

Step 468: etching by etching to pass through the first stack, using a third etching process to etch through the first set of etched vias, by first stacking, and stopping at the second buffer layer or stopping at the second buffer layer Among them, please refer to Figure 54.

Step 470: Next, etching through the second buffer layer is performed using a fourth etching process, as shown in FIG.

Step 472: The stepped structure of the landing zone 310 is located on the active layer of the first stack and the second stack, and the stepped structure of the landing zone 310 can be formed by etching through the through hole, please refer to FIG. 22, and The interlayer conductor can be extended to the landing zone, see Figure 25. In some examples, the etching process to form a stepped structure includes using a single etching process to form a landing zone on an integer multiple of the N layer, the integer multiple of the N layer being at least two.

In various embodiments, a three dimensional array element is provided, such as a memory element. The three-dimensional array element includes a plurality of layers of patterned semiconductor material. Each patterned layer includes a parallel array of semiconductor materials, one end of which is coupled to a first side of the semiconductor liner. Connected to multiple The semiconductor pads of the patterned layer are disposed in a stack. Each of the semiconductor pads includes a landing zone for interconnecting the interlayer conductors to an upper interconnect conductor aligned along a parallel array of semiconductor materials. In a top view, the interlayer conduction system is arranged in a row and disposed in a via structure surrounded by an insulating material. The respective columns of the interlayer conductors are aligned along the X direction, and the X direction is parallel to the first side. In various embodiments, the interlayer conductors may be partially offset in the Y direction, which is perpendicular to the X direction. In various embodiments, the landing zone can be formed in a different type of stepped configuration, such as the stepped configuration illustrated in Figures 6 and 43.

The following structures are described for the structures shown in FIGS. 64 to 71, and the structures shown in FIGS. 64 to 71 further illustrate an example of the stacking of alternating active layers and insulating layers separated by boundary layers to form a vertical The channel and the vertical gate are opposite to the gate structure.

64 to 66 disclose a 3D nonvolatile memory array 471 including a vertical channel NAND-connected transistor 474 String 475. The three-dimensional non-volatile memory array 471 includes an upper insulating layer 268 that covers a String Select Line (SSL) 476, and the tandem select line 476 covers three sub-stacks 252. In each sub-stack 252 of the present example, alternating active layer 202 and insulating layer 204 begin and end at insulating layer 204. Between the secondary stacks 252 is an active buffer layer 477 of active material, such as a doped semiconductor material, such as a phosphorus doped germanium. The active layer 202, the string selection line 476, and the active buffer layer 477 can be composed of the same material. The active buffer layer 477 generally corresponds to the above implementation In the buffer layer 450 in the example, the plurality of active buffer layers 477 also separate the plurality of sub-stacks 252. However, the material of the active buffer layer 477 may be different from the buffer layer 450, the buffer layer 450 may be made of an insulator, and the active buffer layer 477 may be The conductor is made to serve as a gate. . The thickness L2 of the active buffer layer 477 may be greater than 1.5 times the thickness L1 of the active layer 202. The thickness L2 of the active buffer layer 477 forms a gate as will be described later. The length of the gate formed by the thickness L2 of the active buffer layer 477 is greater than 1.5 times the length of the gate formed by the thickness L1 of the active layer 202. A ground select line (GSL) 478 and a lower insulating layer 480 are located between the lowermost sub-stack 252 and the substrate 446.

The opening 482 is formed in a stacked structure as shown in Fig. 64 and extends to the substrate 446, similar to the etched opening 442 shown in Figs. 59 to 62. Opening 482 can be formed in the manner discussed above with respect to the examples of Figures 48-63. The opening 482 is lined with a trapping structure 484, which typically includes an oxide-nitride-oxide layer (ONO) or an oxide-nitride-oxide-nitride-oxide layer ( ONONO). The capture structure 484 is in contact with the respective upper insulating layer 268, the string select lines, the active and insulating layers 202, 204 of each sub-stack 252, the active buffer layer 477, the ground select line 478, and the edge of the lower insulating layer 480. The liner-forming capture structure 484 is a channel layer 486 that is a conductive layer and may be comprised of a doped semiconductor material, such as germanium or polysilicon. The channel layer 486 surrounds the insulating core 488, which may be composed, for example, of yttrium oxide. Referring to FIG. 66, element 490 is, for example, a transistor 474 that can be used as a non-volatile memory cell. Element 490 is formed by active layer 202, capture structure 484, channel layer 486, and active layer 202 is in contact with capture structure 484. The capture structure 484 is in contact with the channel layer 486. In such an example, the active layer 202 is As a gate. Element 490 has a shorter first gate length L1. Element 492 is sometimes referred to as long channel element 492, element 492 is formed in active buffer layer 477, active buffer layer 477 is in contact with capture structure 484, and capture structure 484 is in contact with channel layer 486. Element 492 has a longer gate length L2. The thickness L1 of the active layer 202 can form a transistor having a gate length of less than 0.1 micron, and the thickness L2 of the active buffer layer 477 can form a transistor having a gate length greater than 0.1 micron. The second gate length L2 may be at least 1.5 times the first gate length L1. Referring to Figure 47, circuit 974 controls a series 475 of reverse gate connections. The circuit supplies different path voltages to a plurality of non-volatile memory cells 490 and a plurality of transistors 942 having different gate lengths L1 and L2.

67-71 illustrate a three-dimensional non-volatile memory array 496 that includes a plurality of stacks 498 of substrate 446 and semiconductor strips on substrate 446, the semiconductor strip including first semiconductor strips 500 The second semiconductor strip 502. The first semiconductor strip 500 has a lower first height H1 and the second semiconductor strip 502 has a higher second height H2. The semiconductor strips 500, 502 are separated by an insulating train 503. Stack 498 also includes outer capture structure 507, typically including an oxide-nitride-oxide layer (ONO) or an oxide-nitride-oxide-nitride-oxide layer (ONONO). The first height is not the same as the second height. The second height H2 may be at least 1.5 times the first height H1. A plurality of word lines WL are orthogonally disposed over the capture structures 507 of each of the plurality of stacks 498 and have a conformal surface, a plurality of word lines WL, with the capture structures 507 of each of the plurality of stacks 498. The four of the lines are shown in Figure 68. The 70th and 71st lines are perpendicular to the plane of Fig. 69, and show the inverse gate memory elements disposed on the surface of the plurality of stacks 498 and the intersections between the plurality of word lines. A three-dimensional array of pieces 504, 506. The arrangement described above forms a plurality of tandem-connected transistors 504, 506, and the tandem-connected transistors 504, 506 are formed along the semiconductor strips 500, 502 in a plurality of stacks 498. The above arrangement forms a series 508 of first anti-valve connections of the non-volatile memory cells 504 having a first height H1, see FIG. 70, and a series of second anti-gate connections of the non-volatile memory cells 506 510 has a second height H2 as shown in FIG. In this vertical gate structure, the thicker semiconductor strip 502 can, for example, provide an enlarged process window such that element 504 can be used as a memory cell and element 506 can be used as an error correction code. Memory).

The different first heights H1 and second heights H2 result in the first set of electrical characteristics of the first anti-gate connected series 508 in the first semiconductor strip 500 having the first height, and having the second height H2 The second anti-gate connected series 510 in the second semiconductor strip 502 forms a second set of electrical characteristics. Different electrical characteristics may include: threshold voltage (Vt) and drain to source current (Ids). These different first and second sets of electrical characteristics are caused by different heights of the semiconductor strips, changing the volume of the active string of each transistor. Figure 47 shows an integrated circuit 975 that includes first and second sense amplifiers in block 966. Circuitry 974 is used to control the first sense amplifier to perform electrical measurements of the transistor in the first reverse-gate connected series 508 of the first semiconductor strip 500 in accordance with the first set of electrical characteristics, and the circuit The 974 is used to control the second sense amplifier to perform electrical measurements of the transistor in the series 510 of the second anti-gate connection in the second semiconductor strip 502 in accordance with the second set of electrical characteristics. In some examples, circuit 974 can perform a memory operation on a plurality of first reverse gate connections of transistor 504 to store data in a series of first reverse gate connections 508. The second reverse gate connection sequence 510 is used to correct errors in the data stored on the first reverse gate connection string 508.

The present invention has been described in terms of the preferred embodiments and examples, which are intended to be illustrative of the invention. It will be apparent to those skilled in the art that the present invention can be modified and modified without departing from the spirit and scope of the invention.

200‧‧‧Stacking

202.1, 202.4‧‧‧ active layer

204.1, 204.3, 256, 258, 260, 268, 270‧ ‧ insulation

252.1, 252.2, 252.3, 252.4‧‧‧ times stacking

254, 262, 264, 266‧ ‧ layer matching

272‧‧‧Interlayer conductor

314‧‧‧Insulator

Claims (21)

A method of forming a via in a stack includes: forming a stack of alternating active and insulating layers, comprising: forming a first stack comprising N separated by a plurality of insulating layers An active layer; forming a second stack on the first stack, the second stack including M active layers separated by a plurality of insulating layers; and forming a first buffer layer on the first stack And forming a second buffer layer under the first stack; and exposing one of the first stacks through a set of through holes by using the following steps: using a first Etching process to perform etching to form a first set of etch vias through the second stack and stopping in the first buffer layer or stopping in the first buffer layer, and then using a second etching process Etching, passing the first buffer layer to the upper layer of the first stack; and etching through the first stack by etching: using a third etching process to etch through the first set of etch vias Come through the first Times and stopped at the stacked layer or the second buffer in the second stop on the buffer layer, and then a fourth etching process used to etch through the second buffer layer. The method of claim 1, further comprising: etching through the set of through holes to form a stepped structure of the plurality of landing zones, the landing zones being located in the first stack and the second stack Active layer And forming a plurality of interlayer conductors that extend to the landing zones. The method of claim 2, wherein the etching for forming the stepped structure comprises using a single etching process to form a plurality of landing regions on an integer multiple of an N layer, the integer multiple of the N layer At least 2. The method of claim 1, wherein the first buffer layer is used under the second etching process and the first etching process for each of the first buffer layer and the second stack The etching time is greater than the etching time of one of the insulating layers of the second stack. The method of claim 1, wherein the first buffer layer is composed of the same material as the first stacked insulating layers, but the thickness of the first buffer layer is different. In the case of the thickness of one of the insulating layers stacked for the first time, or (2) the material composition of the first buffer layer is different from the case of the insulating layers stacked for the first time, or (3) The case of both (1) and (2). The method of claim 1, wherein the first buffer layer has a thickness at least 1.5 times greater than a thickness of an active layer in the first stack. The method of claim 1, wherein the first stacking features a first spatial period N1, and the second stacking features a second spatial period N2. Where N1 is equal to N2. The method of claim 1, further comprising: forming an etch mask, the etch mask being over the second stack, the etch mask having a plurality of etch mask openings; and wherein The step of exposing the upper layer is performed by the etching mask openings. The method of claim 1, wherein the forming step of the first stacking and the second stacking is performed such that thicknesses of the upper layer of each of the first stack and the second stack are greater than corresponding And stacking the active layers and at least one of the insulating layers. A stepped contact structure comprising: an alternating stack of active layers and insulating layers, having a plurality of non-simple spatial periods; the stacking of alternating active layers and insulating layers comprises: a first time Stacking, the first stack includes N active layers separated by a plurality of insulating layers, the N active layers including an upper boundary active layer; a second stack, the second stack is located in the first stack Above, the second stack includes M active layers separated by a plurality of insulating layers, the M active layers including an upper boundary active layer; and a first buffer layer, the first buffer layer is interposed Between the first stacking and the second stacking, under the etching process performed, the etching time of the first buffer layer is greater than the etching time of one of the insulating layers of the second stack; a plurality of landing zones a stepped structure, the landing zones are located on the active layers; and a plurality of interlayer conductors extending to the landing zones, the interlayer structures being separated from each other by an insulating material. The stepped contact structure according to claim 10, wherein (1) the first buffer layer is composed of the same material as one of the first stack of insulating layers, but the first buffer layer The thickness is different from the thickness of the insulating layer stacked for the first time, or (2) the material composition of the first buffer layer is different from the first The case of one insulating layer stacked at one time, or the case of (3) having both (1) and (2). The stepped contact structure of claim 10, wherein the stack comprises: a third stack; and a second buffer layer, the second buffer layer being between the second stack and the third Between the sub-stacks, under the etching process performed, the etching time of the second buffer layer is greater than the etching time of one of the insulating layers of the third stack. The stepped contact structure of claim 10, wherein each of the first stack and the second stack of the upper boundary layer are corresponding to the sub-stack of the active layer and the insulating layers At least one of them is thicker. A contact structure includes: a substrate; an alternating stack of active layers and insulating layers on the substrate, the stack of alternating active layers and insulating layers comprising: a first stack, the first stack includes borrowing N active layers separated by a plurality of insulating layers; a second stacking, the second stacking being over the first stack, the second stack comprising M active layers separated by a plurality of insulating layers a first buffer layer, the first buffer layer is between the first stack and the second stack, and the thickness of the first buffer layer is greater than one of the active layers in the first stack a thickness; and a second buffer layer, the second buffer layer is located under the second stack, and the thickness of the second buffer layer is greater than one of the active layers in the second stack a through hole formed in the stack of the alternating active layer and the insulating layer and extending to the substrate; and a channel layer formed in the through hole, wherein the first stack The active layer, the first buffer layer, the active layer in the second stack, and the second buffer layer are electrically connected to the channel layer. A circuit includes: a substrate; and a series of gates connected to the plurality of transistors, the series of the gates being connected to the substrate, comprising: a first plurality of non-volatile memory cells, Having a first gate length; a second plurality of non-volatile memory cells having a second gate length, the second gate length being greater than the first gate length, wherein an electrical channel passes the And a series of gate connections, the electrical channel having a direction perpendicular to the substrate. The circuit of claim 15, further comprising: a circuit for controlling the series of the anti-gate connection, the circuit supplying different path voltages to the non-volatile memory cells and the transistors. The circuit of claim 15, further comprising: a circuit for controlling the series of the anti-gate connection, wherein the first gate length is less than 0.1 micron, and the second gate length is greater than 0.1 Micron. The circuit of claim 15 wherein the series of the anti-gate connections comprises a ground select line transistor (GSL transistor) and a series of select line transistors (SSL transistors). A circuit comprising: a substrate; a plurality of stacks of a plurality of semiconductor strips on the substrate, the semiconductor strips in the stacks comprising at least a first semiconductor strip and a second semiconductor strip, the first semiconductor The strip has a first height, the second semiconductor strip has a second height, the first height is different from the second height, and a plurality of word lines, the word lines are orthogonally disposed on the stacks Above, and the word lines have a surface conformal to the stacks such that a three-dimensional array of the plurality of memory elements is established at a plurality of intersections between the surface of the stack and the word lines And forming a series of the plurality of transistors connected to the gates along the plurality of semiconductor strips in the stacks, comprising: a first anti-valve connection of the plurality of non-volatile memory cells a series, the first anti-gate connection series has the first height; and a plurality of non-volatile memory cells of a second anti-gate connection sequence, the second anti-gate connection series has The second height. The circuit of claim 19, further comprising: wherein the different first height and the second height cause the series of the anti-gate connections in the first semiconductor strip having the first height a first set of electrical characteristics, and causing a second set of electrical characteristics for the series of the anti-gate connections in the second semiconductor strip having the second height, the first set of electrical characteristics being different from the second a first sense amplifier; a second sense amplifier; and a circuit for controlling the first sense amplifier according to the first set of electrical characteristics to An electrical measurement is performed, and the circuit controls the second sense amplifier based on the second set of electrical characteristics for electrical measurement. The circuit of claim 19, further comprising: a circuit for performing a memory operation on the series of the anti-gate connections of the transistors to store a first data in the first Reverse the gate connection and use the second reverse gate connection sequence to correct at least one error in the first data.