TW201635608A - Memory device and manufacturing method of the same - Google Patents

Abstract

A memory device including a substrate, at least one first stacked structure and at least one second stacked structure disposed on the substrate is provided. The first stacked structure includes a plurality of alternately stacked metal layers and oxide layers. The second stacked structure is disposed adjacent to the first stacked structure and includes a plurality of alternately stacked semiconductor layers and oxide layers. The metal layers of the first stacked structure are connected to the semiconductor layers of the second stacked structure.

Description

Memory device and method of manufacturing same 【0001】

The present invention relates to a memory device and a method of fabricating the same.

【0002】

Memory devices are used in many products, such as MP3 players, digital cameras, computer files and other storage components. With the advancement of memory manufacturing technology, the demand for memory devices has also tended to be smaller in size and larger in memory capacity. In response to this demand, it is required to manufacture a memory device having a high component density.

[0003]

Designers have developed a way to increase the density of memory devices by using a three-dimensional stacked memory device to achieve higher memory capacity while reducing the cost per bit. However, due to the repeated stacking of conductors and insulators, the three-dimensional stacked memory device may be subjected to a large word line capacitance. Therefore, how to manufacture a three-dimensional stacked memory device capable of effectively reducing the word line capacitance has become a field in the art. important topic.

[0004]

The present invention relates to a memory device and a method of fabricating the same, which can effectively reduce word line capacitance in a memory device by inserting a thin film transistor in a stacked structure.

[0005]

According to the present invention, a memory device is provided comprising a substrate, at least a first stacked structure, and at least a second stacked structure. The first stack structure is disposed on the substrate and includes a plurality of staggered stacked metal layers and an oxide layer. The second stack structure is disposed on the substrate and adjacent to the first stack structure, and includes a plurality of staggered stacked semiconductor layers and an oxide layer. The metal layer of the first stacked structure is connected to the semiconductor layer of the second stacked structure.

[0006]

According to the present invention, a method of fabricating a memory device is provided, comprising the following steps. A plurality of oxide layers and a tantalum nitride layer are alternately stacked on a substrate. Forming at least one first through hole through the oxide layer and the tantalum nitride layer. A charge storage layer and a channel layer are sequentially deposited in the first through hole. A dielectric structure is deposited to fill the first via. Forming at least one second through hole in a predetermined area. The tantalum nitride layer in the predetermined area is removed. A plurality of semiconductor layers are deposited between the oxide layers in the predetermined region. Depositing at least one gate oxide layer in the second via hole, and the gate oxide layer is on the surface of the semiconductor layer. A gate structure is filled in the second through hole. A third through hole is formed to pass through the oxide layer and the tantalum nitride layer outside the predetermined region. The tantalum nitride layer outside the predetermined area is removed. The filling metal material is between the oxide layers outside the predetermined area to form a plurality of metal layers.

【0007】

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

[0044]

100‧‧‧ memory device
10‧‧‧Substrate
1‧‧‧First stack structure
11‧‧‧metal layer
12, 120, 121, 122‧‧‧ oxide layer
13‧‧‧Charge storage layer
14‧‧‧Channel layer
15‧‧‧Dielectric structure
16‧‧‧Shielding layer
19, 190‧‧‧ layer of tantalum nitride
2‧‧‧Second stacking structure
21‧‧‧Semiconductor layer
23, 231‧‧ ‧ gate oxide layer
24‧‧‧ gate structure
31‧‧‧ first through hole
32‧‧‧Second through hole
33‧‧‧Through hole
51‧‧‧Electrical structure
52‧‧‧Oxidation spacer
61, 62‧‧‧ conductive lines
A-A', B-B', C-C', D-D'‧‧‧ hatching
X, Y, Z‧‧‧ axes

[0008]

FIG. 1 is a plan view showing a memory device according to an embodiment of the present invention.
Fig. 2A is a cross-sectional view of the memory device of Fig. 1 taken along line A-A'.
Fig. 2B is a cross-sectional view of the memory device of Fig. 1 taken along line BB'.
Figure 2C is a cross-sectional view of the memory device of Figure 1 taken along line C-C'.
Figure 2D is a cross-sectional view of the memory device of Figure 1 taken along line DD'.
3A to 9 are views showing a manufacturing embodiment of the memory structure of the present invention.

【0009】

Embodiments of the present invention will be described in detail below with reference to the drawings. The same reference numerals are used to designate the same or similar parts. It is to be noted that the drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to the scale of the actual products, and thus are not intended to limit the scope of the present invention.

[0010]

FIG. 1 is a plan view of a memory device 100 according to an embodiment of the present invention. Fig. 2A is a cross-sectional view of the memory device 100 of Fig. 1 taken along line A-A'. Fig. 2B is a cross-sectional view of the memory device 100 of Fig. 1 taken along line B-B'. Fig. 2C is a cross-sectional view of the memory device 100 of Fig. 1 taken along the line C-C'. Fig. 2D is a cross-sectional view of the memory device 100 of Fig. 1 taken along line D-D'. The memory device 100 of the embodiment of the invention includes a substrate 10, at least one first stacked structure 1 and at least one second stacked structure 2. The first stacked structure 1 and the second stacked structure 2 are disposed on the substrate 10, and the second stacked structure 2 is adjacent to the first stacked structure 1.

[0011]

As shown in FIGS. 1 and 2A, the first stacked structure 1 includes a plurality of staggered stacked metal layers 11 and oxide layers 12. The first stacked structure 1 may include at least one first through hole 31, a charge storage layer 13 and a channel layer 14. The first hole 31 passes through the metal layer 11 and the oxide layer 12, and exposes a part of the surface of the substrate 10. The charge storage layer 13 is disposed on a sidewall of the first through hole 31. The channel layer 14 is disposed on a portion of the surface of the charge storage layer 13 and the exposed substrate 10.

[0012]

For example, the charge storage layer 13 may be a hafnium oxide/tantalum nitride/yttria/tantalum nitride/anthracene oxide (ONONO) structure, and the channel layer 14 may be polysilicon or indium gallium zinc (Indium Gallium Zinc). Oxide, IGZO), but the invention is not limited thereto.

[0013]

In addition, the first stacked structure 1 may include a dielectric structure 15 that fills the first through holes 31. That is, the dielectric structure 15 may be disposed on the surface of the channel layer 14 and fill the remaining space of the first through hole 31.

[0014]

In an embodiment, the oxide layer 121 located at the top of the first stacked structure 1 can serve as a hard mask (HM) layer, and the oxide layer 122 located at the bottom of the first stacked structure 1 can be used as a buried layer. Boiled oxide. In addition, the first stacked structure 1 may also include a cap layer 16 , that is, the shielding layer 16 may cover the upper surface of the oxide layer (hard mask layer) 121 and the dielectric structure 15 .

[0015]

In the embodiment of the present invention, the first stacked structure 1 further includes a high dielectric material layer (not shown), and a high dielectric material layer is disposed between the metal layer 11 and the oxide layer 12 to form a high dielectric. High-κ Metal Gate (HKMG) structure.

[0016]

As shown in FIGS. 1 and 2B, the second stacked structure 2 includes a plurality of staggered stacked semiconductor layers 21 and oxide layers 12, and the semiconductor layer 21 of the second stacked structure 2 is connected to the metal layer 11 of the first stacked structure 1. The second stack structure 2 can include at least one second via 32, at least one gate oxide layer 23, and a gate structure 24. The second through hole 32 passes through the semiconductor layer 21 and the oxide layer 12, and exposes a part of the surface of the substrate 10. The gate oxide layer 23 is disposed in the second through hole 32 and is located on the surface of the semiconductor layer 21. The gate structure 24 fills the second through hole 32. In an embodiment, the gate oxide layer 23 may also be disposed on a portion of the surface of the exposed substrate 10, such as the gate oxide layer 231 in FIG. 2B.

[0017]

As shown in FIG. 2C and FIG. 2D, in the embodiment of the present invention, the memory device 100 may include a plurality of first stacked structures 1 and a second stacked structure 2. In addition, the memory device 100 further includes at least one conductive structure 51 and at least one oxide spacer 52. The conductive structure 51 may be disposed between the first stacked structure 1 (or the second stacked structure 2), and the oxidized spacer 52 is disposed between the first stacked structure 1 (or the second stacked structure 2) and the conductive structure 51. For example, the first, second, and second embodiments show two first stacked structures 1 and two second stacked structures 2, and the conductive structures 51 are disposed on the two first stacked structures 1 (or two second stacked Between the structures 2), the oxidized spacer 52 separates the first stacked structure 1 (or the second stacked structure 2) from the conductive structure 51. The conductive structure 51 can be a source line for connecting the NAND source side of the bottom.

[0018]

In an embodiment, the conductive structure 51 includes, for example, TiN/W or TaN/W, the metal layer 11 of the first stacked structure 1 includes TiN/W, and the semiconductor layer 21 of the second stacked structure 2 includes undoped polysilicon (undoped) Polysilicon). The conductive structure 51 made of TiN/W can be used to reduce the source line resistance.

[0019]

3A through 9 illustrate a manufacturing embodiment of the memory structure 100 of the present invention. First, as shown in FIG. 3A, a plurality of oxide layers 120 and a tantalum nitride layer 190 are alternately stacked on a substrate 10. Here, the substrate 10 can be, for example, a P-type germanium substrate.

[0020]

Next, as shown in FIG. 3B, at least one first through hole 31 is formed through the oxide layer 120 and the tantalum nitride layer 190, and a part of the surface of the substrate 10 is exposed, that is, a plurality of staggered stacked oxide layers 12 and nitride are formed.矽 layer 19. In this embodiment, the topmost oxide layer 121 can serve as a hard mask layer, and the bottommost oxide layer 122 can serve as a buried oxide layer. Further, the first through holes 31 may be formed, for example, by photolithography.

[0021]

As shown in FIG. 3C, a charge storage layer 13 and a channel layer 14 are sequentially deposited in the first through holes 31. In the present embodiment, the charge storage layer 13 is deposited, for example, on the sidewall of the first via 31 and exposes a portion of the surface of the substrate 10. The channel layer 14 is deposited, for example, on the surface of the charge storage layer 13 and the exposed substrate 10. In addition, the charge storage layer 13 may be a hafnium oxide/tantalum nitride/yttria (ONO) structure, a hafnium niobium/tantalum nitride/yttria/yttria/anthracene oxide (ONONO) structure or niobium oxide/nitrogen矽 矽 / 矽 矽 / tantalum nitride / yttria / tantalum nitride / 矽 矽 (ONONONO) structure. Next, a dielectric structure 15 is deposited to fill the first through holes 31.

[0022]

Next, a masking layer 16 is formed on the dielectric structure 15 and the staggered stacked oxide layer 12 and the tantalum nitride layer 19 (i.e., the dielectric structure 15 and the oxide layer 121). In an embodiment, the dielectric structure 15 and the upper surfaces of the staggered stacked oxide layer 12 and tantalum nitride layer 19 may be planarized prior to forming the masking layer 16. For example, a chemical mechanical polish (CMP) process can be performed and stopped at the oxide layer (hard mask layer) 121. The dielectric structure 15 can form an air gap structure to reduce capacitance and coupling effects.

[0023]

Fig. 4 is a plan view of the manufacturing embodiment at this stage. That is, the 3C diagram is, for example, a cross-sectional view taken along line A-A' of the structure of Fig. 4. In Fig. 4, the area surrounded by the broken line is the predetermined area of the second stacked structure 2, and the area outside the broken line is the predetermined area of the first stacked structure 1. That is to say, the processes of the subsequent 5A to 5D drawings are completed in a predetermined region of the second stack structure 2.

[0024]

As shown in FIG. 5A, at least one second through hole 32 is formed in a predetermined region of the second stacked structure 2, and the second through hole 32 passes through the oxide layer 120, the tantalum nitride layer 190 and the shielding layer 16, and the substrate 10 is exposed. A portion of the surface, that is, a plurality of staggered stacked oxide layers 12 and tantalum nitride layers 19 are formed. Similarly, the topmost oxide layer 121 can serve as a hard mask layer and the bottommost oxide layer 122 can serve as a buried oxide layer. Further, the second through holes 32 may be formed, for example, by photolithography.

[0025]

Here, the critical dimension (CD) of the second through hole 32 and the first through hole 31 may be different.

[0026]

Next, as shown in FIG. 5B, the tantalum nitride layer 19 in the predetermined region of the second stacked structure 2 is removed. For example, the tantalum nitride layer 19 can be removed by chemical dry etching (CDE) or phosphoric acid (H ₃ PO ₄ ). The chemical dry etching or phosphoric acid is highly selective to the oxide, and therefore, the tantalum nitride layer 19 can be removed, but the oxide layer 12 is retained.

[0027]

As shown in FIG. 5C, the semiconductor layer 21 is deposited between the oxide layers 12. Here, the semiconductor layer 21 includes, for example, undoped polysilicon or intrinsic polysilicon. The semiconductor layer 21 can be a channel of material and is controlled by a gate structure 24 that is subsequently formed (i.e., Figure 2B).

[0028]

Next, as shown in FIG. 5D, at least one gate oxide layer 23 is deposited in the second via hole 32 and on the surface of the semiconductor layer 21. In an embodiment, the gate oxide layer 23 may also be disposed on a portion of the surface of the exposed substrate 10, such as the gate oxide layer 231 in FIG. 5D. Here, the gate oxide layer 23 may have a thickness of 50 to 500 Å, for example, 300 to 400 Å. The gate oxide layer 23 can withstand higher word line voltage operation.

[0029]

Figure 6 is a plan view of the manufacturing embodiment at this stage. That is, the 5D diagram is, for example, a cross-sectional view of the structure of Fig. 6 taken along line B-B'.

[0030]

Then, the gate structure 24 is filled with the second through holes 32, so that the second stacked structure 2 as shown in FIG. 2B can be formed. Here, the gate structure 24 may, for example, comprise N+ polysilicon or a metal, such as TiN/W. That is to say, the second stack structure 2 can be used as a thin film transistor structure, the gate structure 24 is the gate of the thin film transistor, and the semiconductor layer 21 is the channel of the thin film transistor.

[0031]

As shown in Fig. 7, a third through hole 33 is formed outside the predetermined area of the second stacked structure 2 (i.e., outside the area surrounded by the broken line). Similarly, the third through holes 33 pass through the oxide layer 12 and the tantalum nitride layer 19. Fig. 8A is a cross-sectional view of the structure of Fig. 7 taken along the line C-C'. Fig. 8B is a cross-sectional view of the structure of Fig. 7 taken along line D-D'.

[0032]

As shown in FIGS. 7 and 8A, the tantalum nitride layer 19 in the predetermined region of the first stacked structure 1 (ie, outside the predetermined region of the second stacked structure 2) is removed. Similarly, the tantalum nitride layer 19 can be removed by chemical dry etching or phosphoric acid. The chemical dry etching or phosphoric acid is highly selective to the oxide, and therefore, the tantalum nitride layer 19 can be removed, but the oxide layer 12 is retained. Furthermore, due to the high selectivity of phosphoric acid to polycrystalline germanium and oxide, the semiconductor layer 21 (i.e., the channel of the thin film transistor) in the second stacked structure 2 is not damaged in this step.

[0033]

Next, a metal material is filled between the oxide layers 12 to form the metal layer 11. Here, the metal layer 11 may include, for example, TiN/W. In addition, a high dielectric material (not shown) may be filled in before the step of filling the metal material between the oxide layers 12 to form a high dielectric material layer (not shown) on the metal layer 11 and the oxide layer. Between 12.

[0034]

After filling the metal material between the oxide layers 12, the first stacked structure 1 can be formed as shown in FIGS. 7 and 8A, and the third through holes 33 can separate the two first stacked structures 1. Similarly, as shown in FIGS. 7 and 8B, the third through hole 33 can separate the two second stacked structures 2.

[0035]

Next, as shown in FIG. 9, the oxide spacer 52 and the conductive structure 51 are sequentially formed in the third through hole 33. That is, the oxidized spacer 52 is located between the first stacked structure 1 (or the second stacked structure 2) and the conductive structure 51. Here, the conductive structure 51 may include, for example, TiN/W or TaN/W.

[0036]

After the oxide spacer 52 and the conductive structure 51 are sequentially formed in the third through hole 33, the memory structure 100 as shown in FIG. 1 can be formed. That is, after the oxide spacer 52 and the conductive structure 51 are sequentially formed in the third through hole 33 of FIG. 8A, a structure as shown in FIG. 2C can be formed; the oxide spacer 52 and the conductive layer are sequentially formed. After the structure 51 is in the third through hole 33 of FIG. 8B, the structure as shown in FIG. 2D can be formed.

[0037]

In addition, the memory device 100 of the embodiment of the present invention may include a conductive line disposed on the second stacked structure 2 and electrically connected to the gate structure 24. For example, as shown in FIG. 9, the conductive lines 61, 62 are respectively disposed on the two stacked structures 2 to control the two stacked structures 2, respectively.

[0038]

The memory device 100 of the embodiment of the present invention can be operated in the following manner. First, a portion of the second stacked structure 2 is selected as a selected thin film transistor structure, and the other second stacked structure 2 is a non-selected thin film transistor structure. Next, a gate bias is applied to the selected thin film transistor structure. In this embodiment, the gate bias can be between 2 V and 10 V, for example 3.3 V.

[0039]

In addition, one of the plurality of metal layers 11 of the first stacked structure 1 is selected to be a selected array, and the other metal layers 11 are non-selected arrays. The semiconductor layer 21 of the selected thin film transistor structure connected to the selected array is turned on to enable the metal layer 11 of the selected array to be energized. Here, the metal layer 11 can serve as a word line of the memory device 100.

[0040]

For example, as shown in FIG. 9, a gate bias can be applied to the portion of the second stacked structure 2 by the conductive line 61, and the conductive line 62 is not biased. That is, the second stacked structure 2 electrically connected to the conductive line 61 is a selected thin film transistor structure, and the second stacked structure 2 electrically connected to the conductive line 62 is a non-selected thin film transistor structure.

[0041]

When the selected array is connected to the selected thin film transistor structure, since the selected thin film transistor structure has a gate bias, its semiconductor layer 21 is turned on, allowing the metal layer 11 of the selected array to be energized. When the selected array is connected to the non-selected thin film transistor structure, since the non-selected thin film transistor structure does not have a gate bias, the semiconductor layer 21 cannot be turned on, so that the metal layer 11 cannot be energized.

[0042]

Therefore, whether or not the metal layer 11 in the selected array is turned on can be determined through the second stacked structure 2 (thin film transistor structure). In addition, the selected thin film transistor structure can be determined without additional decoding. This is because the gate structure 24 is connected to the (reverse gate) series select line (SSL). When the selected string select line is on, the gate structure 24 located in the same selected string is also turned on. The second stack structure 2 is made to require no additional decoding circuitry. Since only the metal layer 11 connected to the selected thin film transistor structure can be energized, the capacitance of the metal layer 11 (word line) can be greatly reduced.

[0043]

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory device

1‧‧‧First stack structure

13‧‧‧Charge storage layer

14‧‧‧Channel layer

15‧‧‧Dielectric structure

2‧‧‧Second stacking structure

51‧‧‧Electrical structure

52‧‧‧Oxidation spacer

A-A’, B-B’, C-C’, D-D’‧‧‧ hatching

X, Y‧‧‧ axes

Claims (10)

[Item 1] A memory device comprising:
a substrate;
At least one first stacked structure disposed on the substrate, the first stacked structure includes a plurality of staggered stacked metal layers and an oxide layer; and at least one second stacked structure disposed on the substrate, the second stacked structure abutting In the first stacked structure, and comprising a plurality of staggered stacked semiconductor layers and an oxide layer,
The metal layers are connected to the semiconductor layers. [Item 2] The memory device of claim 1, wherein the first stack structure comprises:
At least one first through hole, passing through the metal layer and the oxide layer, and exposing a portion of the surface of the substrate;
a charge storage layer disposed on a sidewall of the first via hole; and a channel layer disposed on the surface of the charge storage layer and the exposed substrate. [Item 3] The memory device of claim 2, wherein the first stack structure comprises:
A dielectric structure fills the first through hole. [Item 4] The memory device of claim 1, wherein the second stack structure comprises:
At least one second through hole, passing through the semiconductor layer and the oxide layer, and exposing a portion of the surface of the substrate;
At least one gate oxide layer is disposed in the second via hole and located on a surface of the semiconductor layers; and a gate structure fills the second via hole. [Item 5] The memory device of claim 4, wherein the gate oxide layer is disposed on a portion of the surface of the exposed substrate. [Item 6] The memory device according to claim 1, further comprising:
a plurality of the first stacked structures; and at least one conductive structure disposed between the first stacked structures. [Item 7] A method of manufacturing a memory device, comprising:
Stacking a plurality of oxide layers and a tantalum nitride layer on a substrate;
Forming at least one first through hole through the oxide layer and the tantalum nitride layer;
Depositing a charge storage layer and a channel layer in the first through hole in sequence;
Depositing a dielectric structure to fill the first through hole;
Forming at least one second through hole in a predetermined area;
Removing the layer of tantalum nitride in the predetermined area;
Depositing a plurality of semiconductor layers between the oxide layers in the predetermined region;
Depositing at least one gate oxide layer in the second via hole, and the gate oxide layer is located on a surface of the semiconductor layers;
Filling a gate structure in the second through hole;
Forming a third through hole through the oxide layer and the tantalum nitride layer outside the predetermined region;
Removing the tantalum nitride layers outside the predetermined region; and filling the metal material between the oxide layers outside the predetermined region to form a plurality of metal layers. [Item 8] The manufacturing method described in claim 7 of the patent scope further includes:
An oxidized spacer and a conductive structure are sequentially formed in the third through hole. [Item 9] The manufacturing method described in claim 7 of the patent scope further includes:
The dielectric structure is planarized and the upper surfaces of the oxide layer and the tantalum nitride layer are alternately stacked; and a shielding layer is formed on the oxide layer and the tantalum nitride layer of the dielectric structure and the staggered stack. [Item 10] The manufacturing method of claim 7, wherein the charge storage layer is deposited on a sidewall of the first via hole and exposes a portion of the surface of the substrate, the channel layer being deposited on the charge storage layer and the exposed substrate Part of the surface.