KR102063530B1 - Stacked 3d memory - Google Patents

Abstract

The memory may include a plurality of memory blocks including a first block and a second block disposed above the first block. An isolation layer in this structure is disposed between the first and second blocks to separate vertical conductors in the memory kernels of the first and second blocks. Access conductors are provided outside the kernels, such as adjacent to memory blocks or through regions of blocks containing only a decoding element. The access conductors are connected to decoding elements in the first and second blocks and provide a connection of the memory cells to peripheral circuits.

Description

Stacked 3D Memory {STACKED 3D MEMORY}

The present invention relates to high density memory technologies, including those that include three dimensional (3D) arrays of memory cells.

High density flash memory is used for nonvolatile storage in many systems. One common configuration is known as NAND flash and is typically implemented within a two dimensional array of memory cells. As manufacturing technology advances to smaller and smaller nodes, it is widely believed that two-dimensional NAND flash has reached its physical limits. Thus, many different technologies are being explored.

In one trend for implementing high density memory for flash memory and other types of memory, designers look for techniques to stack multiple levels of memory cells to achieve greater storage capacity and lower cost per bit. come. For example, thin film transistor technologies are described in Lai et al. "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory" (IEEE Int'l Electron Devices Meeting). , 11-13 Dec. 2006); Jung et al., "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node) "(IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006). See also US Pat. No. 8,482,052 to the invention of Lue et al., Entitled " Silicon on Insulator and Thin Film Transistor Band gap Engineered Split Gate Memory. &Quot; .

In a second approach, flash memory has been implemented using vertical gate structures that are shared between many levels or memory cells. One 3D vertical gate (3DVG) structure is registered on August 6, 2013, and the inventors are Shih-Hung Chen and Hang-Ting Lue, US Patent No. 8,503,213, the disclosures of which are hereby incorporated by reference in their entirety. The name of the invention is described in "Memory Architecture Of 3D Array With Alternating Memory String Orientation And String Select Structures".

In a third approach, flash memory has been implemented using vertical channel structures shared between many levels or memory cells. For example, US Patent No. 8,363,476, registered on January 29, 2013 (filed January 19, 2011), and whose inventors are Hang-Ting Lue and Shi-Hung Chen (name of invention: "Memory Device, manufacturing method and operating method thereof ". In addition, U.S. Patent Application No. 13 / 772,058 filed on February 20, 2013, filed by Hang-Ting Lue, the disclosure of which is hereby incorporated by reference in its entirety, entitled " Three-dimensional memory (3D NAND Flash). Memory) ").

Another structure that provides vertical channel structures for NAND cells in charge trapping memory technology is Tanaka et al., "Bit Cost Scalable Technology with Punch and Plug Process. for Ultra High Density Flash Memory) "(2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007, pages: 14-15).

These 3D techniques all have practical limitations in the number of layers of memory cells that can be implemented while maintaining reliable operation. A simple stacking approach is expensive because each layer of the stack must be patterned separately. Other structures, including the vertical gate and vertical channel structures, or vertical conductors extending through multiple layers of memory cells, are more cost effective because many layers can be patterned using a single mask and etching process. Can be effective. However, limitations arise because of the high aspect ratio structures that are difficult to etch, and because intermediate structures can be destroyed during processing.

Accordingly, it is desirable to provide techniques for maintaining a stack of three-dimensional (3D) blocks of memory cells that can be reliably implemented to overcome some limitations in the number of layers.

Techniques for stacking three-dimensional (3D) blocks of memory cells are provided.

Stacked structures are described to address other structures in three-dimensional blocks, including structures in a memory kernel and structures of decoding elements coupled to the kernel. The memory kernel is at the core of the structure of the memory block, and decoding elements are connected to the kernel. Conductors in the kernel can be classified into two cases: (1) conductors such as bit lines transmitting signals representing data and (2) conductors such as word lines carrying control signals. . Decoding elements in the kernel are connected to both types of conductors, and the horizontal conductors in the kernel for connection to string or block select transistors, ground transistors, peripheral circuits, and vertical conductors outside the kernel. And stairstep structures for the purpose of connection.

The memory may include a plurality of memory blocks including a first block and a second block disposed above the first block. In this structure, an isolation layer is disposed between the first and second blocks to separate the memory kernels of the first and second blocks. Access conductors are provided outside of the kernels, such as through areas of blocks adjacent to the memory block or containing only decoding elements. The access conductors are connected to decoding elements in the first and second blocks and provide a connection of the memory cells to peripheral circuits.

By separating the connections in one kernel from the cases in the stack described above, the stacked structure can be made with fewer connections. In addition, by providing access conductors that are connected only to decoding elements, larger connection sizes can be used for access conductors that can be used in the memory kernel.

Other aspects and advantages of the present technology can be identified through a review of the following figures, detailed description of the invention, and claims.

According to the invention, by separating the connections in one kernel from the elements in the stack described above, the stacked structure can be made with fewer connections. In addition, by providing access conductors coupled to the decoding elements, larger connection sizes can be used for access conductors that can be used in the memory kernel. In addition, the memory kernels are fabricated according to a first design rule that includes dimensions of vertical conductors through the kernels and is selected to implement dense memory cell structures, and wherein the decoding elements in the memory blocks are loaded through the kernels. In the case of vertical conductors the invention can be advantageously applied when manufactured according to a second design rule characterized by larger characteristic sizes.

The above and other features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings.
1 is a simplified diagram of three-dimensional (3D) memory blocks including device isolation layers with decoding element interconnects.
2 is a perspective view of a three-dimensional block of memory cells in a three-dimensional vertical gate configuration with kernel and decoding element regions suitable for stacking as described herein.
3 is a perspective view of a three-dimensional block of memory cells in a three-dimensional vertical channel configuration with kernel and decoding element regions suitable for stacking as described herein.
4-9 illustrate the steps of the fabrication process for stacking three-dimensional memory blocks as described herein.
10 illustrates a set of conductors connected to respective decoding elements, such as stepped landing regions in first and second blocks of a stacked memory structure.
11 illustrates a set of conductors connected to decoding elements within each layer of a stack of three-dimensional memory blocks.
12 and 13 are cross-sectional and side views of a set of conductors, such as source line conductors, connected to decoding elements in the parallel layers of a stack of three-dimensional memory blocks.
14 illustrates conductors connected to decoding elements in three-dimensional memory blocks but not to corresponding conductors in other blocks in the stack.
15 is a simplified flowchart of a manufacturing process for forming a stack of three-dimensional memory blocks described herein.
FIG. 16 is a simplified block diagram of an integrated circuit having a three-dimensional memory including stacked blocks of memory cells with separate kernels.

Detailed descriptions of embodiments of the present invention are provided with reference to FIGS. 1 to 16.

1 is a simplified diagram of a stacked three dimensional (3D) memory including a plurality of memory blocks. The illustrated structure includes a first block having a memory kernel 104 and a decoding element region 114. The second block disposed above the first block includes a memory kernel 103 and a decoding element region 113. The third block disposed above the second block includes a memory kernel 102 and a decoding element region 112. The fourth block in the illustrated stack has a memory kernel 101 and a decoding element region 111. An isolation layer (eg, 123) is disposed between the blocks. Access conductors are configured between the decoding element regions 111-114. Segments of the access conductors are disposed in the device isolation layers 121-123. In this example, segments 151-153 of access conductors are disposed in the device isolation layer 123 between the second block and the first block. Segments 141-143 of access conductors are disposed in the device isolation layer 122 between the third block and the second block. Segments 131-133 of access conductors are disposed in the device isolation layer between the fourth block and the third block.

In this example, the decoding element regions (eg 111) are shown only on one side of the memory kernel (eg 101). In other embodiments, the decoding element regions may be distributed in other configurations including regions on both sides of the memory kernel, regions on all sides of the memory kernel, and the like.

The memory kernels are fabricated according to a first design rule that includes feature sizes of vertical conductors through the kernels and is selected to implement very dense memory cell structures, and wherein the decoding elements in the memory blocks are loaded through the kernels. For vertical conductors this technique can be advantageously applied when manufactured in accordance with the second design rule characterized by larger characteristic sizes.

The device isolation layers can limit the effect of damaged memory cells in a particular block on the operation of other blocks in the stack by separating the vertical conductors fabricated in the kernels with very strict design rules. In addition, by preventing connections between the kernels in the blocks, any damage in one block will not be multiplied by the shared conductors through the kernels. In addition, the device isolation films may limit the range of effects of any misalignment defects caused during fabrication.

As described above, the memory blocks may include vertical channel or vertical gate three-dimensional structures. 2 and 3 illustrate 3DVG and 3DVC blocks that can be stacked using the techniques described herein. In addition, these figures illustrate that structures in the memory kernel that can be made using small design rules and that decoding elements in the decoding element regions of the blocks that are connected to the memory kernel can be made using larger design rules. Indicates.

2 is published on January 12, 2012 and filed on January 31, 2011, the disclosure of US Patent Application Publication No. 2012/0007167 (name of the invention: “Improved”), the disclosures of which are hereby incorporated by reference in their entirety. A memory block having a three-dimensional vertical gate (3DVG) configuration as described in "3D Memory Array With Improved SSL and BL Contact Layout" is illustrated.

Insulating material is removed from the figure to expose additional structures. For example, insulating layers are erased between the semiconductor strips in ridge-shaped stacks, and between the ridge-shaped stacks of the semiconductor strips. The decoding regions are represented by boxes 198 and 199. The memory kernel is represented by box 197.

The multilayer array is formed on an insulating layer. The kernel 197 includes a plurality of word lines 225-1,..., 225 -N-1, 225 -N having vertical extensions that are conformal to a plurality of ridge shaped stacks. do. The plurality of ridge shaped stacks include horizontal semiconductor strips 212, 213, 214, 215 configured as channels for corresponding NAND strings in each layer of the block.

The decoding elements in the block are stairstep structures 212A, 213A, 214A, 215A in the decoding element region 198 and stepped structures 202B, 203B, 204B, in the decoding element region 199. 205B). The stepped structures 212A, 213A, 214A, 215A end with horizontal semiconductor strips, such as semiconductor strips 212, 213, 214, 215. As illustrated, these stepped structures 212A, 213A, 214A, 215A are connected by vertical conductors for connection to page buffers and other decoding circuitry that selects planes within the array. Other data lines overlying the block, in this example, are electrically connected in the metal layer ML3. These stepped structures 212A, 213A, 214A, and 215A may be patterned at the same time that the plurality of ridge shaped stacks are defined using larger design rules used within the kernel.

Stepped structures 202B, 203B, 204B, and 205B in the decoding element region 199 terminate semiconductor strips, such as semiconductor strips 202, 203, 204 and 205. As illustrated, these stepped structures 202B, 203B, 204B, and 205B are electrically connected to other data lines for connection to page buffers and other decoding circuitry that selects planes within the array. These stepped structures 202B, 203B, 204B, and 205B can be patterned at the same time that the plurality of ridge shaped stacks are defined using larger design rules used within the kernel.

Any given stack of semiconductor strips in the kernel 197 are connected to the stepped structures 212A, 213A, 214A, 215A or the stepped structures 202B, 203B, 204B, 205B, but not all. The stack of semiconductor strips has one of two opposing orientations, a source line end orientation at the bitline end or a bit line end orientation at the source line end. For example, the stack of semiconductor strips 212, 213, 214, 215 has a source line end orientation at the bit line end, and the stack of semiconductor strips 202, 203, 204, 205 has a source line end At the bit line end orientation.

The stack of semiconductor strips 212, 213, 214, 215 is terminated at one side by the stepped structures 212A, 213A, 214A, 215A, and the SSL gate structure 219 and ground select line GSL Pass the decoding elements in region 198 that includes 226. Further, the stack of semiconductor strips 212, 213, 214, 215 passes through decoding elements in region 199 having a ground select line (GSL) 227 and a source line 228 terminating the strips. do. The stack of semiconductor strips 212, 213, 214, 215 does not reach the stepped structures 202B, 203B, 204B, and 205B.

The stack of semiconductor strips 202, 203, 204, 205 is terminated at one end by the stepped structures 202B, 203B, 204B, and 205B, an SSL gate structure 209 and a ground select line (GSL). Pass through the decoding elements in the region 199 containing 227). Further, the stack of semiconductor strips 202, 203, 204, 205 includes a decoding element in region 198 that includes a ground select line (GSL) 226 and a source line (ambiguous due to other portions of the figure). Pass through them. The stack of semiconductor strips 202, 203, 204, 205 does not reach the stepped structures 212A, 213A, 214A, 215A.

A layer of memory material separates the word lines 225-1 through 225 -N from the semiconductor strips 212-215 and 202-205.

Ground select lines (GSL) 226 and GSL 227 include conformal vertical extensions to the plurality of ridge shaped stacks similar to the horizontal lines and the word lines.

The stack of all semiconductor strips is terminated at one end by stepped structures and terminated at the other end by a source line. For example, the stack of semiconductor strips 212, 213, 214, 215 is terminated at one end by stepped structures 212A, 213A, 214A, 215A, and the other end by source line 228. End on the phase. In the right part of the figure, every other stack of semiconductor strips is terminated by the stepped structures 202B, 203B, 204B, and 205B, and every other stack of semiconductor strips is terminated by a separate source line. In the left part of the figure, every other stack of semiconductor strips is terminated by the stepped structures 212A, 213A, 214A, and 215A, and every other stack of semiconductor strips is terminated by a separate source line.

Transistors are formed between the stepped structures 212A, 213A, and 214A and the word line 225-1. In the transistors, the semiconductor strip (e. G. 213) functions as a channel region of the device. SSL gate structures (e.g., 219, 209) are patterned during the same step in which the word lines 225-1 through 225-N are defined. A layer of silicide (shown filled with diagonal lines) may be formed over the SSL gate structures along the top surface of the word lines, along the ground select lines. The layer of memory material 215 serves as a gate dielectric layer for the transistors. These transistors function as string select gates connected to decoding circuitry for selecting ridge shaped stacks within a particular said array.

Data lines and string select lines are formed in the metal layers ML1, ML2 and ML3 overlying the memory block. In a stacked structure, the metal layers comprise conductors connecting access lines from the blocks to peripheral circuits, which may be shared by the stacked blocks and need to be repeated for individual blocks. There is no.

In this example, the first metal layer ML1 includes conductors connecting string select lines in a longitudinal orientation parallel to the semiconductor material strips. These ML1 string select lines are connected to other SSL gate structures (eg, 209, 219) by short vias.

The second metal layer ML2 includes conductors that connect string select lines in a horizontal orientation parallel to the word lines. These ML2 string select lines are connected to other ML1 string select lines by short vias.

In combination, these ML1 string select lines and ML2 string select lines allow a string select line signal to select a particular stack of semiconductor strips.

The first metal layer ML1 also includes conductors connecting two source lines in a horizontal orientation parallel to the word lines.

Finally, the third metal layer ML3 includes conductors connecting bit lines in a longitudinal orientation parallel to the semiconductor material strips. Other data lines are electrically connected to other steps of the stepped structures 212A, 213A, 214A, 215A and 202B, 203B, 204B, 205B. These ML3 data lines allow the bit line signal to select a particular horizontal plane of semiconductor strips.

Since a particular word line enables the word line to select a particular plane of memory cells, the triple combination of word line signals, bit line signals and string select line signals may cause a particular memory cell to be extracted from the three-dimensional array of memory cells. Enough to choose.

FIG. 3 is a U.S. patent application Ser. No. 13 / 772,058 filed on Feb. 20, 2013, the disclosures of which are hereby incorporated by reference in their entirety. FIG. 3A " 3D NAND Flash Memory " Is a schematic diagram of an exemplary vertical channel three dimensional (3D) memory block, as described in FIG. The memory blocks shown in FIG. 3 can be stacked as described herein. The memory block includes high density memory cells in the kernel 299 and decoding elements in the decoding element region 298.

The 3DVC memory block includes an array of NAND strings of memory cells and may be a double gate vertical channel memory array (DGVC). The memory block is separated by an insulating material and comprises a stack of a plurality of conductive strips including at least a bottom surface GSL of the conductive strips, a plurality of intermediate surfaces WL of the conductive strips and an upper surface SSL of the conductive strips. Equipped. In the example shown in FIG. 3, the stack in the stacks 310 is the bottom surface GSL of the conductive strips, a plurality of intermediate surfaces WL and the conductive strips of the conductive strips ranging from WL0 to WLN-1. Top surface (SSL), where N may be 8, 16, 32, 64, and the like.

The plurality of bit line structures are disposed on top of each other at right angles, and a connection element on stacks connecting vertical inter-stack semiconductor body elements 320 between the stacks and the inter-stack semiconductor body elements 320. It has conformal vertical extensions in a plurality of stacks including linking elements 330. In this example, the connection elements 330 include a semiconductor having a relatively high doping concentration, such as polysilicon, so that they have a higher conductivity than the inter-stack semiconductor body elements 320, and they are cells within the stacks. To provide channel regions for the user.

The memory device interfaces at intersections 380 between side surfaces of the conductive strips in the plurality of intermediate surfaces WL in the stacks and the interstacked semiconductor body elements 320 of the plurality of bit line structures. There are charge storage structures in the regions. In the example shown, the memory cells in the intersections 380 are constructed in vertical, double-gate NAND strings, where the conductive strips on both sides of a single stack semiconductor body element are double gated. And can work in concert for read, erase and program operations.

The memory device includes string select switches 390 in the interface regions having the top surfaces of the conductive strips and reference select switches 370 in the interface regions having the bottom surface GSL of the conductive strips. The dielectric layers of the charge storage structure may serve as gate dielectric layers for the switches 370 and 390 in some examples.

A reference conductor 360 is disposed between the bottom surface GSL of the conductive strips and the integrated circuit board (not shown). Such conductors may be located at the bottom of the stack of memory blocks and may be shared by the blocks within the stack. In example embodiments, the memory device may include a lower gate 301 near the reference conductor 360 to reduce the resistance of the reference conductor 360. During read operations, the doped well or wells or other underlying patterned conductor structure in the substrate positioned below the lower gate 301 to increase the conductivity of the reference conductor 360. It can be turned on by an appropriate pass voltage applied to the field.

Decoding elements in the decoding element regions are disposed orthogonally on top of the plurality of stack lights and include inter-stack vertical conductive elements 340 between the stacks in electrical communication with the reference conductor 360. Connection elements 350 on top of the stack 310 that connect a reference line structure and the inter-stack vertical conductive elements 340. The inter-stack vertical conductive elements 340 may have higher conductivity than the inter-stack semiconductor body elements 320.

A stack of memory blocks, such as the case shown in FIG. 3, is patterned located on top of a first top connected to the plurality of bit line structures having a plurality of global bit line structures coupled to page buffers and other decoding circuitry. Conductive layer (not shown). The memory device also includes a patterned conductive layer (not shown) located on the second top, which can be patterned and can be over or under the first patterned conductive layer. The conductive layer located above the second upper portion is connected to the at least one reference line structure as by contacting the connecting element 350 in the decoding element region of the block. The second patterned conductive layer may connect the at least one reference line structure to a circuit portion for providing a reference voltage source or a reference voltage.

In the example shown in FIG. 3, the connection elements 330 of the bit line structures comprise an N + doped semiconductor material. The inter-stack semiconductor body elements 320 of the bit line structures comprise a lightly doped semiconductor material. In the example shown in FIG. 3, the reference conductor 360 includes an N + doped semiconductor material, and the connection elements 350 of the at least one reference line structure include an N + doped semiconductor material. The inter-stack vertical conductive elements 340 of the at least one reference line structure also include an N + doped semiconductor material. In alternative implementations, a metal or metal compound may be used in place of the doped semiconductors in the inter-stack vertical conductive elements 340.

The decoding elements in decoding element region 298 provide pad regions in the conductive strips for the horizontal word line and GSL line structures and are configured for stepped contacts to the decoding circuits located thereon. It includes structures. String select lines in the top surface of the conductive strips are independently connected and controlled by the string select line decoding circuits. The stepped structures 361 and 362 are pad areas for connecting sets of word lines in the intermediate surfaces WL, and a landing area in the connection elements consisting of stepped structures 361 and 362. Interlayer connectors, such as interlayer connectors 371 and 372, which are connected to the interconnections, wherein the connecting elements comprise openings through which the interlayer connectors are connected to landing areas in the lower intermediate surfaces. . The landing regions are interface regions between the bottom surfaces of the interlayer connectors and the upper surfaces of the connecting elements.

As illustrated in FIG. 3, interlayer connections for sets of word lines in multiple layers within the plurality of intermediate surfaces are arranged in a stepped structure. Thus, interlayer connections 371 and 372 are connected to landing regions at different layers in the plurality of intermediate surfaces. The staircase structure may be formed in a decoding element region near a boundary of an area for a block of NAND strings of memory cells and an area for peripheral circuits.

In the example shown in FIG. 3, the memory device comprises: connection elements such as connection element 363 in the decoding element region 298 connecting sets of ground select lines in the bottom surface GSL of conductive strips; And interlayer connectors such as interlayer connectors 373 connected to landing areas in the connecting elements in the bottom surface, wherein the interlayer connectors are openings in the connecting elements in the intermediate surfaces WL. Extends through them. The landing regions are the interface regions between the bottom surfaces of the interlayer connectors such as the interlayer connector 373 and the top surfaces of the connecting elements such as the connection element 363.

4-9 illustrate steps of a fabrication process for stacking three-dimensional memory blocks representing the formation of the interlayer connections in a stepped structure in the decoding element regions of the blocks. The order of the steps is similar to the case for other conductors used to connect the decoding elements in the decoding element regions of the stacked blocks.

4 illustrates a structure after forming a first memory block, the first memory block having a plurality of layers (eg, four layers) of memory cells (eg, four). Layers) and a decoding element region 411 comprising decoding elements connected to the memory kernel. Vertical segments 412-1, 413-1, 414-1, 415-1 are formed in the decoding element region 411, which is for example stepped structures as shown in FIG. 2 (not shown). To the landing regions on the backplane). The memory block shown in FIG. 4 may be manufactured using processes such as those described in many applications incorporated herein by reference. Block with four vertical segments 412-1, 413-1, 414-1, 415-1, fabricated as shown for FIG. 2 and connected to the stepped structures in the decoding element region 411 May have four planes of memory cells in the kernel 401. In a stacked structure, the width of the block may be larger than the width required for the space of the vertical segments 412-1, 413-1, 414-1, 415-1, and may be connected to respective vertical segments. Increase the number of columns of memory cells in each layer.

5 illustrates a structure after the device isolation layer 421 is formed on the first memory block. The device isolation layer 421 may be made of silicon oxide or another insulating material that may be used in combination with integrated circuit fabrication.

6 shows a structure after forming the second segments 412-2, 413-2, 414-2, and 415-2 of the vertical conductors on the decoding element region 411, which is the vertical conduction. First segments 412-1, 413-1, 414-1, 415-1 of the sieves. The second segments 412-2, 413-2, 414-2, and 415-2 may be made with a relatively large design rule compared to the case where the second segments 412-2, 413-2, 414-2, and 415-2 are used in the memory kernel 401. Facilitates and enables more reliable manufacturing.

7 illustrates a structure after forming a second memory block on the device isolation layer 421, wherein the second memory block includes a memory kernel 501 including a plurality of layers of memory cells and the memory kernel 501. Decoding elements in decoding element region 511, Vertical segments 512, 513, 514, 515 are formed inside the decoding element region 511, which are located in landing regions on stepped structures (not shown), for example as shown in FIG. 2. Connected. In conjunction with the first block, the use of four vertical segments 512, 513, 514, 515 supports four planes of memory cells when the kernels are made as described with reference to FIG. 2.

8 illustrates the peaking after forming third segments 412-3, 413-3, 414-3, and 415-3 in decoding element region 511 of the second block, which are the decoding element region (511). 411 is aligned and contacted with the second segments 412-2, 413-2, 414-2, and 415-2 of the vertical conductors in the device isolation layer 421. First segments 412-1, 413-1, 414-1, 415-1 of the vertical conductors inside the decoding element region 411 and joining with corresponding second and third segments. Implements a vertical connection from the stepped structure in the first block through the decoding element region 511 in the second block.

FIG. 9 schematically illustrates the structure after back-end processes used to form the conductor structures located on top of which contact vertical conductors in the decoding element region 511 of the upper block. The conductor structures located above these in the illustrated example include the bit lines BL1 to BL8, which are connected to page buffers or other decoding circuitry.

10 is a cross-sectional view of the stepped interlayer conductors as in the cases shown in FIG. 10 shows active layers 605-608 in the second block separated by the active layers 601-604 and the isolation layer 621 in the first block. Within the blocks, insulating layers 651-654 and insulating layers 655-658 separate active layers. In the decoding element regions of the blocks, stepped structures as in the cases described above provide landing regions for interlayer conductors. The interlayer conductors in this example are implemented within the decoding element regions of the blocks without limiting the strict design rules of the conductors formed inside the kernels of the blocks. The interlayer conductors for the active layers 601-604 in the lower block can each include three segments. Thus, the interlayer conductors may contact the active layer 601, the segment 615-2 in the device isolation layer 621, and the segment 615-3 passing through the upper block by the segment 615-1. It is formed in the lower block. The device isolation layer (eg, 620) surrounds the interlayer conductors when the interlayer conductors pass through the active layers disposed thereon. In addition, the interlayer conductor for the active layer 602 may include a segment 614-1 in the lower block, a segment 614-2 in the device isolation layer 621, and a segment 614-3 in the upper block. Include. The interlayer conductor for the active layer 603 includes a segment 613-1 in the lower block, a second segment 613-2 in the device isolation layer 621, and a segment 613-3 in the upper block. Include. The interlayer conductor for the active layer 604 does not include a segment through the lower block because in this example the active layer is the top layer. However, the interlayer conductor for the active layer 604 includes a segment 612-2 in the device isolation layer 621 and a segment 612-3 in the upper block.

Interlayer conductors for the active layers 605-608 in the upper block include single segment conductors (not classified) in this example.

As described above, after forming the interlayer conductors in the decoding element regions of the blocks, a back-end process is used to implement patterned conductive layers located on top, such as bit line structures BL1 to BL8. Is used.

The multi-segment interlayer conductors shown in FIG. 10 in contact with active layers in the lower block do not electrically contact decoding elements or memory cells in the upper block, but in the data lines or in some embodiments only the lower block. Provides control lines for

11-14 illustrate other forms of conductors for decoding elements in the memory blocks. FIG. 11 illustrates a structure for string select line (SSL) structures, such as SSL gate structure 219 in decoding element region 198 of FIG. 12 and 13 show a structure for a source line, such as source line 228 in decoding element region 199 of FIG. 2. FIG. 14 illustrates a structure for a gate select line GSL, such as gate select line 227 in decoding element region 199 of FIG. 2.

Figure 11 shows two SSL structures, which are respectively connected to conductor SSL1 and conductor SSL2 for connection to peripheral circuitry used for control of the memory. In the SSL structures, the active layers include active strips in respective stacks. Thus, in the SSL structure connected to SSL1, the strips for the active layers 601-604 in the first block are in this example insulating layers 651-654 with an insulating layer 664 located thereon. Separated by). In addition, the strips for the active layers 605-608 in the second block are separated by insulating layers 655-658 with an insulating layer 668 located on top in this example. Dielectric layers 804-1, 804-2, 804-3, and 804-4, which can be multilayer stacks also used in the memory kernel as the dielectric charge storage structure, are gate insulators between the SSL structure and the strips. Is arranged as. The SSL gate structure connected to SSL1 includes a first segment 801-1 overlying the stack in the lower block, a second segment 801-2 extending through the device isolation layer 621, and within the upper block. And a third segment 801-3 located above the stack. Metal structures located on top form the conductor SSL1. In a similar manner, the SSL structure connected to SSL2 overlies the strips for the active layers in the first and second blocks. The SSL structure has the first segment 802-1 located above the stack in the lower block, and in this example has two portions connected to opposite sides of the SSL structures in the decoding element regions of the blocks. The second segment 802-2 extends through the device isolation layer 621. A third segment 802-3 located above the stack in the upper block is connected to the second segment 802-2. The first segment 802-1 may be manufactured during fabrication of the first block using larger design rules applied to the decoding element in a manner similar to the formation of the word lines. Similarly, the third segment 802-3 may be manufactured during manufacture of the second block using larger design rules.

The SSL structures illustrated in FIG. 11 are examples of connections for lower block decoding elements that do not process data for the upper memory but can control the upper memory portions. The SSL structures are also examples of connections extending from lower blocks through the decoding element region of the upper blocks.

FIG. 12 illustrates a source line structure for terminating strips in the active layers having a connection to a reference voltage source, such as ground or other reference voltage in accordance with both implementation and operation of the device. The source line structure carries current through the memory cells in some embodiments. FIG. 12 shows two source line structures, which are connected to source line conductors 860 and 861 overlying each one in a patterned conductive layer. The source line conductors 860, 861 provide a connection for the decoding circuitry and other peripheral circuitry for the operation of the device. A dielectric layer (eg, 854) may be present on the sidewalls of the source line structures, which may be a multilayer stack that is also used within the memory kernel as a dielectric charge storage structure.

13 shows that strips of semiconductor material in the active layers 601-608 terminate in segments 881-1 and 851-3 of source line structures in the decoding element regions of the first and second blocks. Indicates. The source line structure connected to the conductor 860 includes a first segment 881-1 connected to the strips in the active layers 601-604 in the decoding element region of the lower block. In addition, the second segment 851-2 penetrates the device isolation layer 621. Third segment 851-3 terminates the strips in the active layers 605-608 in the decoding element region of the upper block. In a similar manner, the source line structure connected to the conductor 861 has a first segment 852-1 in the decoding element region of the lower block, and a second segment 852-2 passing through the device isolation layer 621. And a third segment 852-3 in the decoding element region of the upper block.

The source line structure shown in FIGS. 12 and 13 provides electrical connections that carry the current of memory cells in the upper and lower memory blocks, such as a common source line. However, the structure is located in the decoding element region outside the kernel of the memory cells.

14 illustrates another conductor disposed in the decoding element regions of the first and second blocks. In this example, a ground select line (GSL) structure is illustrated, such as the GSL structure 226 in the decoding element region 198 of the structure of FIG. The lower block includes a GSL line 871. The upper block includes a GSL line 872. There is no connection between the GSL line 871 and the GSL line through the device isolation layer 621. This allows the GSL lines 871 and 872 to be controlled independently if desired. Further, in other embodiments, the GSL lines 871 and 872 may be electrically connected to neighboring blocks arranged horizontally or other interconnect structures outside the memory blocks.

Thus, the GSL structure shown in FIG. 14 illustrates a connection for decoding elements that can be used to control the operation of the memory blocks, which are not connected to blocks that are placed above or below the stack. .

Thus, a first set of conductors (eg, stepped data lines) are connected to the decoding elements in the first and second blocks, and decoded outside the memory kernels of the first and second blocks. It is provided to be disposed in the element regions. The first set of conductors includes conductors disposed vertically in decoding element regions that are connected to decoding elements in respective layers in the first and second blocks.

A second set of conductors (eg, SSL gates or source lines) are also connected to the decoding elements in the first and second blocks, and the first and second blocks outside the memory kernels. Are provided to be placed inside the field. Each conductor in the second set of conductors includes vertical extensions that pass through all layers in the first and second blocks.

15 illustrates a basic fabrication process for stacking blocks of memory cells. The flowchart begins with an indication 1000 and is provided with an integrated circuit board on which stacked three-dimensional memory devices are formed. The process includes forming 1001 a first memory block having a kernel and a decoding element region as described above. Of course, many memory blocks can be formed in a first layer of blocks that provide a high storage density of large storage capacity. An isolation layer is formed on the first memory block 1002. The device isolation layer provides a means for separating the kernel of the first block from the first block. The device isolation film separates small design rules, high density features of the kernels in the stacked blocks in operation of the device. Next, a second memory block (or a layer of second memory blocks) is formed on the device isolation layer 1003. The second memory block includes a kernel and decoding element region aligned above corresponding regions of the first memory block.

The process includes providing access conductors coupled to the decoding elements in the first and second blocks. In the illustrated embodiment, the access conductors comprise a first set of conductors, such as stepped data lines, which are connected to decoding elements in the first and second blocks, Disposed vertically within the decoding element regions (1004). The first set of such conductors provides a connection to the decoding elements in the respective layers of the first and second blocks and does not touch or control the elements in the other blocks.

The access conductors implemented in an exemplary process also include a second set of conductors, such as SSL gates or source lines, which are connected to decoding elements in the first and second blocks, and wherein 1005 vertical extensions passing through all layers in the first and second blocks. This second set of conductors provides a connection to the decoding elements in every layer of the first and second blocks and can be used for control of the decoding elements in both blocks.

The process may include the formation of other conductors as described above.

Furthermore, according to the illustrated process, peripheral circuits are provided that are configured to access selected memory cells via decoding elements in the selected memory blocks, which utilize first and second sets of conductors 1006. do.

Back-end-of-line (BEOL) processes are performed to complete the manufacture of the device, so that the flowchart ends with indication 1007.

The flowchart is intended to provide a basic manufacturing process. The order steps may be changed to suit a particular implementation. Similarly, the types of conductors implemented within the first set of conductors and the second set of conductors depend on the particular embodiments of the memory blocks and the decoding elements accessed.

FIG. 16 is a block diagram of an integrated circuit including a three-dimensional memory array having stacked blocks with separate kernels with peripheral circuits used for access memory cells in the blocks, as described herein, for other purposes. to be. A row decoder 901 is connected and electrically in communication with the string select line, ground select line and word line drivers in block 912 and is arranged along the columns in the memory array 900. And drive word lines 902.

A page buffer 906 is electrically connected to a plurality of bit lines 904 disposed along rows in the memory array 900 for reading and writing data from memory cells in the memory array 900. Communicating. Addresses are provided on the bus 905 for the column decoder 901 and the page buffer 906. Data is provided to the page buffer 906 from input / output ports on the integrated circuit 950. Data is passed from the page buffer 906 via a data-out line 915 to input / output ports on the integrated circuit 950 or other data destinations inside or outside the integrated circuit 950. Is provided. State machine, clock circuitry and other control logic are in circuitry 909. Biasing arrangement supply voltages are generated in block 908 using charge pumps and other voltage sources, and are supplied to the word line drivers in block 912 and other circuitry on the integrated circuit. The integrated circuit 950 includes terminals used to connect to a power source, which provides the supply voltages VDD and VSS to the chip.

Although not illustrated, the integrated circuit 950 may include other peripheral circuits such as processors, gate arrays, login circuitry, and the like.

The 3D memory structure is described as suitable for three-dimensional blocks in the form of vertical gates and vertical channels. The structure includes a stack of three-dimensional blocks with respective memory kernels and decoding element regions. Connections extending through one or more blocks in the stack are placed only within decoding element regions outside the kernel, and larger design rules can be implemented. The connections include connections that are connected to decoding elements in only one block, but pass through blocks located above in the decoding element areas. Further, the connections may include connections connected to decoding elements in the decoding element regions of all blocks in the stack.

While the present invention has been described with reference to preferred embodiments and experimental examples, it will be understood that these examples are intended by way of example and not by way of limitation. Those skilled in the art will understand that many variations and combinations can be easily carried out, and those variations and combinations are within the spirit of the invention and the scope of the following claims. Will belong.

101, 102, 103, 104 ： Memory kernel
111, 112, 113, 114: Decoding element regions 121, 122, 123: Device isolation film
131, 132, 133, 141, 142, 143, 151, 152, 153: segment of access conductor
202, 203, 204, 205, 212, 213, 214, 215: semiconductor strip
202B, 203B, 204B, 205B, 212A, 213A, 214A, 215A: Stepped structure
209 and 219: SSL gate structure 215: layer of memory material
225-1... 225-N: Word lines 226 and 227: Ground select line (GSL)
228 ： Source line 298 ： Decoding element area
299: Memory kernel 301: Lower gate
310: Stacks 320: Semiconductor body elements
330, 350, 363: connecting elements 340: vertical stack between conductive elements
360: reference conductors 361 and 362: staircase structures
370: reference select switches 371, 372, 373: interlayer connectors
380: intersections 390: string select switches
401: memory kernel 411: decoding element area
412-1, 413-1, 414-1, 415-1: First segments
412-2, 413-2, 414-2, 415-2: second segments
412-3, 413-3, 414-3, 415-3: Third segments
421: element separator 501: memory kernel
511 ： Decoding element area
512, 513, 514, 515: vertical segments
601, 602, 603, 604, 605, 606, 607, 608: active layers
612-1, 612-2, 612-3: Segments 614-1, 614-2, 614-3: Segments
615-1, 615-2, 615-3: segments 620, 621: device isolation membrane
651, 652, 653, 654, 655, 656, 657, 658: insulating layers
655, 656, 657, 658, 668: insulating layers 801-1, 802-1: first segment
801-2, 802-2: second segment 801-3, 802-3: third segment
804-1, 804-2, 804-3, and 804-4: Dielectric Layers 851-1: First Segment
851-2: Second segment 851-3: Third segment
854: Dielectric layer 860, 861: Source line conductors
871, 872: GSL line 900: memory array
901: column decoder 902: word lines
904 ： Bit lines 905 ： Bus
906: Page buffer 909: Circuit portion
915: data output line 950: integrated circuit
ML1, ML3, ML3: Metal layer BL1-BL8: Bit lines

Claims (28)

A memory kernel having a plurality of memory blocks, each memory block having a plurality of layers of memory cells and vertical conductors through the plurality of layers and decoding elements coupled to the memory kernel. Wherein the plurality of memory blocks includes a first block and a second block disposed over the first block;
An element isolation film between the first and second blocks for separating the vertical conductors in the memory kernels of the first and second blocks;
Having access conductors connected to the decoding elements in the first and second blocks;
The access conductors,
A first set of conductors coupled to decoding elements in the first and second blocks, the first set of conductors being disposed in a decoding element region outside of the memory kernels of the first and second blocks; A first set includes conductors disposed vertically in the decoding element region that are connected to decoding elements in respective layers in the first and second blocks;
A second set of conductors coupled to the decoding elements in the first and second blocks and disposed within the first and second blocks, wherein each conductor in the second set of conductors is And vertical extensions extending through all layers in the first and second blocks outside the memory kernels. delete 2. The apparatus of claim 1, wherein the access conductors comprise specific conductors coupled to decoding elements within the first and second blocks and disposed within the first and second blocks, A first segment connected to the decoding element in the first block, a second segment connected to the decoding element in the second block and nominally aligned with the corresponding first segment, and through the device isolation layer; And a second segment and a third segment coupled to the first segment. 2. The memory of claim 1 wherein said first set of conductors is coupled to corresponding layers of said memory kernels in stepped structures comprising landing pads extending horizontally into said decoding element region. 2. The apparatus of claim 1, wherein the access conductors comprise specific conductors coupled to decoding elements in the first block, wherein the particular conductors are:
A first segment disposed adjacent to the second block;
A second segment nominally aligned with the first segment disposed adjacent to the first block, the second segment contacting a decoding element within the first block; And
And a third segment connected to the second segment and the first segment through the device isolation layer. 2. The memory of claim 1 wherein a conductor in the second set of conductors is coupled to a decoding element in the first block and a decoding element in the second block. 2. The memory of claim 1 wherein the kernels of memory blocks comprise vertical word lines. 2. The memory of claim 1 wherein the kernels of memory blocks comprise vertical channel lines. The method of claim 1, wherein the decoding elements of the memory blocks include vertical source lines, wherein the vertical source lines in the first block are connected to the vertical source lines in the second block through the device isolation layer. Memory. 2. The apparatus of claim 1, wherein the kernels comprise horizontal NAND strings, and wherein the decoding elements comprise string select switches connected to the access conductors that provide vertical string select lines, the first selector within the first block. The vertical string select lines are connected to the vertical string select lines in the second block through the device isolation layer. 2. The method of claim 1 wherein the vertical conductors in the memory kernels have dimensions according to a first design rule and the decoding elements in the memory kernels have dimensions according to a second design rule that is greater than the first design rule. Characterized by memory. 2. The memory of claim 1 including peripheral circuits coupled to the access conductors and configured to access selected memory cells through decoding elements within the selected memory blocks. In the manufacturing method of the memory,
Providing a first memory block, the first memory block including a memory kernel having a plurality of layers of memory cells and decoding elements coupled to the memory kernel;
Forming an isolation layer over the first memory block;
Forming a second memory block on the device isolation layer, the second memory block including a memory kernel having a plurality of layers of memory cells and decoding elements coupled to the memory kernel;
Providing a first set of conductors coupled to decoding elements in the first and second memory blocks and disposed in a decoding element region outside of the memory kernels of the first and second memory blocks; The first set of conductors comprises conductors disposed vertically within a decoding element region connected to decoding elements at respective layers in the first and second memory blocks;
Providing a second set of conductors coupled to decoding elements in the first and second memory blocks and disposed inside the first and second memory blocks outside the memory kernels, Wherein each conductor in the second set of conductors includes vertical extensions extending through all layers in the first and second memory blocks. 15. The method of claim 13, wherein providing a second set of conductors comprises: forming first segments connected to decoding elements within the first memory block during the forming of the first memory block; Forming interconnects connected to corresponding first segments through device isolation layers, and connecting to decoding elements in the first memory block and over corresponding interconnects to corresponding first segments through the device isolation layers; Forming second segments to be connected. 15. The method of claim 13 including forming stepped structures with landing regions extending horizontally into the decoding element region, the first set of conductors corresponding to the memory kernels in the landing regions. Connected to the layers. 15. The method of claim 13, wherein providing a first set of conductors comprises forming first block conductors coupled to decoding elements in the first memory block, wherein the first block conductors ,
First segments disposed adjacent the second memory block and separated from the second memory block;
Second segments nominally aligned with the first segments disposed adjacent to the first memory block and in contact with corresponding decoding elements within the first memory block; And
And interconnections connected to the first and second segments through the device isolation layer. 14. The method of claim 13, wherein a conductor in the second set of conductors is coupled to a decoding element in the first memory block and a decoding element in the second memory block. 15. The device of claim 13, wherein the kernels of the memory blocks comprise vertical word lines, wherein the vertical word lines in the first memory block are connected in rows by horizontal lines and through the device isolation layer. And not connected to vertical word lines in the memory block. 15. The device of claim 13, wherein the kernels of the memory blocks comprise vertical channel lines, wherein the vertical channel lines in the first memory block are connected in columns by horizontal lines and through the device isolation layer. And not connected to the vertical channel lines in the memory block. The method of claim 13, wherein the decoding elements of the memory blocks include vertical source lines, and the vertical source lines in the first memory block are connected to the vertical source lines in the second memory block through the device isolation layer. The manufacturing method of the memory. 14. The apparatus of claim 13, wherein the kernels comprise horizontal NAND strings, the decoding elements include string select switches coupled to vertical string select lines, and the vertical string select lines in the first memory block are And a vertical string select line in the second memory block through an isolation layer. 14. The apparatus of claim 13, wherein the memory kernels of the first and second memory blocks comprise vertical elements having dimensions according to a first design rule, wherein at least some of the decoding elements of the first and second memory blocks are selected from the first and second memory blocks. And a dimension according to the second design rule larger than the one design rule. 15. The method of claim 13 including providing peripheral circuits configured to access selected memory cells through the decoding elements in the selected memory blocks. A memory kernel including a plurality of memory blocks, the memory blocks including a plurality of layers of memory cells each having vertical elements having layout view dimensions according to a first design rule; Decoding elements including vertical elements having layout view dimensions according to a second design rule that is greater than the first design rule, wherein the plurality of memory blocks are a first block and a second block disposed above the first block; It includes;
A device isolation layer between the first and second blocks;
Stepped structures connected to decoding elements in the first and second blocks, the stepped structures including landing areas extending horizontally into a decoding element area outside of the first and second blocks;
A first set of conductors disposed vertically in said decoding element region, which in said layers of said first and second blocks are connected to landing regions in said stepped structure;
A second set of conductors coupled to the decoding elements in the first and second blocks and disposed within the first and second blocks, wherein each conductor in the second set of conductors is Vertical extensions passing through all layers in the first and second blocks outside the memory kernels;
And peripheral circuits configured to access memory cells selected through the first and second sets of conductors in the selected memory blocks. 25. The device of claim 24, wherein the kernels of the memory blocks comprise vertical word lines, wherein vertical word lines in the first block are connected in columns by horizontal lines, and vertical words in the second block through the device isolation layer. Memory not connected to the lines. 25. The device of claim 24, wherein the kernels of the memory blocks comprise vertical channel lines, wherein vertical channel lines in the first block are connected in rows by horizontal lines and vertical channel ain in the second block through the device isolation layer. Not connected to the memory. 26. The method of claim 25, wherein the decoding elements of the memory blocks comprise vertical source lines, wherein the vertical source lines in the first block are connected to the vertical source lines in the second block through the device isolation layer. Memory. 26. The device of claim 25, wherein the kernels include horizontal NAND strings, the decoding elements include string select switches connected to vertical string select lines, and the vertical string select lines in the first block are the device. And a vertical string select line in the second block through a separator.

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