TW201714249A - Multilayer 3-D structure with mirror image landing regions - Google Patents

Abstract

An integrated circuit includes blocks and global lines overlying the blocks. The blocks include a plurality of levels including two dimensional arrays of memory cells having horizontal lines and being intersected by vertical lines coupled to corresponding memory cells. Levels include contact pads communicating with horizontal lines for a given block. The global lines include connectors. Connectors coupled to given global lines are coupled to landing areas on corresponding contact pads of the blocks. The blocks include first and second blocks disposed so that a first set of the contact pads associated with the first block are next to a second set of contact pads associated with the second block. The landing areas of the contact pads of the first and second blocks are mirror image surfaces of one another. The horizontal lines can be bit lines and the vertical lines can be word lines.

Description

Multi-layer three-dimensional structure with mirrored falling area

The present invention relates to a device for a 3-D integrated circuit, and more particularly to an interlayer conductor that improves the landing regions of active layers. Device of process window.

The three-dimensional integrated circuit includes a plurality of active layers in which conductor elements or semiconductor elements are disposed. The three-dimensional memory volume circuit includes a stack of two-dimensional memory cell arrays. The active layer in the stack may, for example, comprise bit lines or word lines, which must be connected to peripheral circuits such as decoders, sense amplifiers (sense amplifier) and the like. In some configurations, the connection is achieved using an interlayer conductor extending from each active layer to a routing layer, such as a patterned metal layer over the two-dimensional array stack. The patterned metal layer can be used to pass signals and biases between the array and appropriate peripheral circuitry. A similar signal routing structure can be used for other types of three-dimensional integrated circuits.

The three-dimensional integrated circuit may also include other kinds of structures, including a three-dimensional vertical gate structure and a three-dimensional vertical channel structure. Both of these have a stack of alternating active and insulating layers and have interlayer conductors that extend to the landing zone above the different active layers, also known as landing pads. .

The interlayer conductor has a length that varies depending on the active layer forming the contact. As the number of active layers increases, some processes involved in the formation of interlayer conductors may become more difficult. One of the reasons why it becomes more difficult is that as the length of the interlayer conductor becomes longer, the interlayer conductor is tapered to obtain a smaller diametrical dimension, thus reducing the interlayer conductor and the active layer. Process margin between the falling areas on the top.

The present invention describes an integrated circuit that includes blocks and global lines located above the blocks. The block includes a plurality of levels, the level includes a corresponding two-dimensional array of memory cells, and the corresponding two-dimensional array includes horizontal lines interleaved with vertical lines coupled to a plurality of corresponding memory cells in the array. (horizontal lines). A hierarchy in a given block includes corresponding contact pads that are electrically connected to horizontal lines in a given block. The global line includes connectors. The connector is coupled to a given global line and coupled to the landing area of the corresponding contact pad of the block. The block includes a first block and a second block, the first set of contact pads associated with the first block being adjacent to the second set of the contact pads of the second block. The landing pads of the contact pads of both the first block and the second block are each a plurality of mirror image surfaces.

Embodiments of the integrated circuit described in the present invention may include one or more of the following. The horizontal line can be a bit line, and the vertical line can be a word line. Each block may have N levels (where the level indices z of the N levels are 1 to N, respectively); the connector may be configured to correspond to the global line, such that the first group related to the first block The hierarchical index of the layers of the contact pads may be changed in a stepwise manner from the first level to the second level toward the corresponding level of the second set of contact pads; the second set of the contacts related to the second block The hierarchical index in the hierarchy of the pads may change from a first level to a second level in a stepped fashion toward a corresponding level of the first set of contact pads; and, the first block and the second block The connectors in the block that contact the contact pads of the first level may be adjacent to each other with no other connectors therebetween. The first set of contact pads and the second set of contact pads may be substantially V-shaped. The array of memory cells can include NAND arrays, and the horizontal lines can include local bit lines.

The present invention describes a three-dimensional structure comprising a substrate, and a first unit and a second unit of a plurality of layers formed by alternately stacking the insulating layer and the active layer on the substrate. The first unit includes first to nth active layers, wherein the first active layer of the first unit is located at a selected level. The second unit includes first to nth active layers, wherein the first active layer of the second unit is located at the selected level. The first unit and the second unit each comprise a stair step arrangement of a landing zone above the active layer. The landing zones of the first unit and the second unit are mirror images of each other. The insulating layer is located above the landing zone. The interlayer conductors are arranged in a stepped manner through the insulating layer to the landing regions of the first unit and the second unit to electrically contact the landing regions in the first unit and the second unit.

Embodiments of the three-dimensional structure described in the present invention may include the following. A plurality of blocks, wherein the plurality of blocks include a plurality of levels corresponding to the first to nth active layers, and the level includes a corresponding two-dimensional array of memory cells. The corresponding two-dimensional array includes a horizontal line selected from one of a bit line or a word line, the horizontal line is interlaced with the vertical line, and the vertical line is selected from a bit line or a word line that is not selected as a horizontal line. The hierarchy is connected to the landing zone in the corresponding active layer such that the landing zone is electrically connected to the horizontal line in a given block.

Embodiments of the three-dimensional structure described in the present invention may include one or more of the following. An insulating sleeve separates the insulating layer from the interlayer conductor. The interlayer conductor can electrically contact the landing areas of the first unit and the second unit. The mirrored surface can be formed in a substantially V-shaped arrangement. The interlayer conductors contacting the landing areas in the first unit and the second unit may be disposed opposite each other with no other interlayer conductor therebetween. The mirrored surface can be formed into a substantially inverted V-shaped arrangement.

Other aspects and advantages of the techniques described herein can be found by reference to the following drawings, embodiments, and claims.

1-1‧‧‧Cutting line
10‧‧‧Three-dimensional structure
12‧‧‧ active layer
14‧‧‧Insulation
15‧‧‧Substrate
16‧‧‧First stepped unit
18‧‧‧Second stepped unit
18A, 18B‧‧‧ stepped unit
20, 20A‧‧‧ falling area
22, 22.1, 22.2‧‧‧ side surface
24, 24A‧‧‧ interlayer conductor
26‧‧‧Insulation sleeve
28‧‧‧Insulation materials
30‧‧‧etch stop layer
32, 32A‧‧‧ etching stop sidewall
34‧‧‧First stack
36‧‧‧Second laminate
38‧‧‧First photoresist layer
40‧‧‧second photoresist layer
42‧‧‧First opening area
44‧‧‧Second photoresist layer unit
46‧‧‧Extension of the first open area
48‧‧‧Re-deposition of the first photoresist layer
50‧‧‧Re-deposition of the second photoresist layer
52‧‧‧Second opening area
54‧‧‧Extended second open area
56‧‧‧Secondary redeposition of the first photoresist layer
58‧‧‧Second redeposited second photoresist layer
60‧‧‧ third open area
62‧‧‧Extended third open area
64, P1~P8‧‧‧ position
68‧‧‧Three-dimensional memory structure
70, 125-1~125-N‧‧‧ character line
72, 73‧‧‧Vertical gate transistor/memory cell
74‧‧‧Serial selection line gate
76‧‧‧First direction
78‧‧‧First block
79‧‧‧Second block
80‧‧‧ third block
81‧‧‧Fourth block
102, 103, 104, 105, 112, 113, 114, 115‧‧‧ semiconductor strips
102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A‧‧‧ bit line contact pad structure
109, 119‧‧‧ tandem selection line gate structure
126, 127‧‧‧ Grounding selection line
128‧‧‧ source line
1058‧‧‧Planar decoder
1059‧‧‧ bit line
1060‧‧‧Array
1061‧‧‧ column decoder
1062‧‧‧ character line
1063‧‧‧ line decoder
1064‧‧‧Sequence selection line
1065‧‧‧ Busbar
1066, 1068‧‧‧ squares
1067‧‧‧ data bus
1069‧‧‧ state machine
1071‧‧‧ data input line
1072‧‧‧ data output line
1074‧‧‧Other circuits
1075‧‧‧Integrated circuit
BL0~BL15‧‧‧Global bit line
L1~L8‧‧‧
ML1~ML3‧‧‧ metal layer

1 is a simplified cross-sectional view showing a three-dimensional structure of an active layer and an insulating layer and first and second stepped cells alternately stacked.
Fig. 1A is a partially enlarged view showing the structure shown in Fig. 1.
Fig. 1B is a simplified cross-sectional view showing a portion of a three-dimensional structure illustrating the problems caused when adjacent stepped cells do not have mirror symmetry.
FIG. 1C is a simplified representation of a V-shaped stepped unit and an inverted V-shaped stepped unit.
2 to 11 illustrate exemplary process steps for forming the three-dimensional structure shown in Fig. 1.
2 is a first stack and a second stack formed by alternately stacking an active layer and an insulating layer, wherein the first photoresist layer and the second photoresist layer are electrically separated, and the first etching is performed. structure.
Figure 3 is a diagram showing the structure of the structure of Figure 2 after the second etching.
FIG. 4 illustrates the structure of the structure of FIG. 3 after further depositing a photoresist material to form a redeposited first photoresist layer and a second photoresist layer.
Fig. 5 is a view showing the structure after the third etching of the structure of Fig. 4.
Figure 6 is a diagram showing the structure of Figure 5 after further depositing a photoresist material to form a second redeposited first photoresist layer and a second redeposited second photoresist layer.
Fig. 7 is a view showing the structure after the fourth etching of the structure of Fig. 6.
FIG. 8 is a view showing the structure after removing the second redeposited first photoresist layer and the second redeposited second photoresist layer in the structure of FIG. 7.
Fig. 9 is a view showing the structure after the etch stop layers are provided for the structure of Fig. 8.
Fig. 10 is a view showing the structure after covering the insulating material over the structure of Fig. 9 having an etch stop layer.
11 is a view showing the structure of FIG. 10 forming an insulating layer through the insulating material, the etch stop layer and the uppermost layer, and having the interlayer conductor extending to and contacting the contact pad landing region of the active layer of each stepped cell; The structure after.
Figure 12 is a schematic plan view of a three-dimensional memory structure including a first stepped unit and a second stepped unit similar to the three-dimensional structure of Figure 1.
FIG. 12A is a diagram showing an exemplary simplified layout of the three-dimensional memory structure of FIG. 12 repeated twice, illustrating how global bit lines can connect adjacent three-dimensional memory structures to different three-dimensional memories. The blocks of the transistor/memory elements on each side of the stepped cells in the bulk structure provide access.
Figure 13 is a perspective view showing the structure of a three-dimensional inverse gate memory array. For illustrative purposes, the insulating material is removed from the figure to expose other structures.
Figure 14 is a simplified block flow diagram of an integrated circuit memory using a memory cell and a bias circuit in accordance with one embodiment of the present technology.

The following description will typically refer to particular embodiments and methods. It is to be understood that the invention is not limited to the specific embodiments and methods disclosed herein. The present invention has been described in terms of a preferred embodiment, but the scope of the invention is defined by the scope of the claims. Those skilled in the art will recognize various equivalent variations based on the following description. Similar elements in the various embodiments generally correspond to similar element symbols. Moreover, unless otherwise specifically stated, the insulator and the conductor mean an electrical insulator having a bulk electrical resistivity of at least 10 ⁶ ohm-cm, and more preferably an electrical insulator of at least 10 ⁸ ohm-cm, and more preferably An electrical insulator of at least 10 ¹² ohm-cm and an electrical conductor having a volume resistivity between 10 ^-6 and 1 ohm-cm.

1 is a simplified cross-sectional view of a three-dimensional structure 10 having a plurality of levels, designated L1 through L8 in the figure, with active layers 12 and insulating layers 14 alternately stacked on a substrate 15. The alternating layers formed by the active layer 12 and the insulating layer 14 form a first stepped unit 16 and a second stepped unit 18 which are mirror images of each other. The first stepped unit 16 and the second stepped unit 18 are the landing areas 20 on the contact pads of the active layer 12, and the side surfaces 22.1 extending from the falling areas of the positions P1 to P7, as shown in FIG. Stepped arrangement of 22.2. The side surfaces 22.1 and 22.2, collectively referred to as side surfaces 22, are formed on the edges of the active layer 12 and the insulating layer 14 adjacent to the landing region 20. The landing zone 20 is located at each of the positions P1 to P8 of each of the first stepped unit 16 and the second stepped unit 18. In some embodiments, the locations of the active layer 12 and the insulating layer 14 can be swapped such that in such embodiments only side surfaces corresponding to the side surfaces 22.1 are formed. The active layer 12 is a conductive layer formed of a semiconductor material, a conductor material, or a combination thereof, and is separated from the insulating layer by the active layer carrying voltage and current for the mission function of the component, and the insulating layer The active layers are then separated from each other. In this embodiment, the active layer 12 is composed of a patterned polysilicon layer and has a doping pattern suitable for implementing the memory structure. The insulating layer 14 is an electrically insulating layer, and in this embodiment is composed of silicon dioxide (SiO ₂ ). Other electrically insulating materials, such as tantalum nitride, niobium oxynitride, and other materials that can operate as interlayer dielectric layers can also be used as the insulating layer 14.

The interlayer conductor 24, surrounded by an insulating sleeve 26, passes through the insulating layer 28 to contact the active layer of the landing region 20 at each of the positions P1 to P8 of each of the first stepped unit 16 and the second stepped unit 18. 12. The etch stop layer 30 overlies the landing region 20 and the side surface 22 except for the portion of the landing region 20 that is occupied by the interlayer conductor 24 and the insulating sleeve 26. The interlayer conductor 24 is a conductive material.

In this embodiment, the interlayer conductor 24 is doped polysilicon (using dopants such as arsenic, phosphorus, boron). However, other conductive materials such as other doped semiconductors, metals, conductive metal compounds such as metal halides, and combinations of these materials can also be used.

The insulating sleeve 26 is made of an electrically insulating material, such as tantalum nitride (SiN) in this embodiment, and may be of the same or different material as the material used for the insulating layer 14.

The etch stop layer 30 is an electrically insulating material selected from materials having different etching characteristics than those used for the insulating material 28. In one embodiment, the etch stop layer 30 can be a tantalum nitride, for example, with an insulating material 28 that is a material of tantalum oxide. Other materials such as niobium oxynitride (SiON) may also be used to etch stop layer 30.

Fig. 1B illustrates a problem caused when adjacent stepped cells, such as the stepped cells 18A and the stepped cells 18B, do not have mirror symmetry. In the example shown in FIG. 1B, the etch stop sidewall 32 between most of the positions P2 to P8 is relatively short without significantly affecting the process in which the interlayer conductor 24 is formed on the contact region 20. Margin. However, between the position P8 of the stepped unit 18A and the position P1 of the stepped unit 18B, the etching stop side wall 32A adjacent to the interlayer conductor 24A of the stepped unit 18B has a tapered profile due to its height (tapered profile) ). As the etching stop side wall 32A gradually approaches the falling area 20A at the position P1, the thickness thereof also increases. The tapered shape of the etch stop sidewall 32A thus reduces the contact process margin of the interlayer conductor 24A at the position P1 of the stepped cell 18B.

The first stepped unit 16 and the second stepped unit 18, which are mirror images of each other, have a landing area 20 which is substantially V-shaped. That is, a line (not shown) passing through the center of each of the landing areas of the first stepped unit 16 and the second stepped unit 18, in this embodiment, a wide and low angle is formed. V-shaped. Although in the embodiment disclosed herein, the line passing through the center of each of the landing regions of each of the first stepped unit 16 and the second stepped unit 18 is a single straight line, each of the stepped units may be defined as A set of lines, a single curve, a set of curves, or a combination of lines and curves. Thus, the substantially V-shaped mirrored stepped cells include stepped cells having other mirror shapes, the other mirrored shapes including, for example, a narrower, higher elevation V-shape, and closer to the line passing through each of the landing zones 20. When the substrate 15 is curved, it can be described as being substantially U-shaped.

Fig. 1C illustrates a V-shaped stepped unit and an inverted V-shaped stepped unit. Both the V-shaped stepped unit and the inverted V-shaped stepped unit provide the advantage of avoiding the etch stop sidewall 32A as in FIG. 1B, generally surrounded by a high and tapered etch stop sidewall, formed by an insulating sleeve 26. The opening of the channel of the layered conductor 24. That is to say, the process margin of the adjacent interlayer conductors 24 in the adjacent stepped cells is no longer smaller than the process margin of the interlayer conductors 24A of the stepped cells 18B at the position P1. Figure 1C also illustrates the situation when adjacent stepped cells do not have the same number of landing zones.

2 to 11 illustrate exemplary process steps for forming the three-dimensional structure shown in Fig. 1.

2 is a cross-sectional view showing the first laminate 34 and the second laminate 36 in which the active layer 12 and the insulating layer 14 are alternately stacked. The first photoresist layer 38 covers the first laminate 34 and the second laminate 36. The second photoresist layer 40 is formed to cover the first photoresist layer 38. In this embodiment, the second photoresist layer 40 is etched to form a first opening region 42 between the second photoresist layer units 44. The first opening 34 and the second photoresist layer unit 44 of the first laminate 34 and the second laminate 36 are mirror images of each other. The first open area 42 is located at positions P1, P3, P5, and P7 of both the first laminate 34 and the second laminate 36.

FIG. 3 illustrates that the structure of FIG. 2 is etched through the first opening region 42 through the first opening region 42 to form an extended first opening region 46. This first stack etch step removes the 2 ^n-1 layer of insulating layer 14 and active layer 12, where n = 1, since this is the first stack etch step. Thus, a first stack etch step removes the insulating layer ²⁰ = 1 layer 14 and the active layer 12, i.e. the first stack 34 and the second stack 36 of the uppermost layer of the active layer 12 and the insulating layer 14 .

FIG. 4 illustrates the structure of FIG. 3 after further depositing a photoresist material to form a redeposited first photoresist layer 48, followed by deposition of a photoresist material to form a redeposited second photoresist layer 50. The redeposition of the second photoresist layer 50 is shown followed by a second image etch to form a second open region 52 that extends down to the redeposited first photoresist layer 48. The second open area 52 is located at positions P1, P2, P5, and P6 of each of the first laminate 34 and the second laminate 36.

5 shows that the structure of FIG. 4 is formed by the third etching to form the extended second opening region 54, and the positions P1 and P5 of the first laminate 34 and the second laminate 36 are additionally etched by 2 ^n-1 = 2 ¹ = 2 layers of insulating layer 14 and active layer 12. This etching step also etches the uppermost two layers of insulating layer 14 and active layer 12 of the positions P2, P6 of each of the first laminate 34 and the second laminate 36.

FIG. 6 illustrates that the structure of FIG. 5 is further deposited with a photoresist material to form a second redeposited first photoresist layer 56, followed by deposition of a photoresist material to form a second redeposited second photoresist layer 58. The second redeposited second photoresist layer 58 is shown to be subsequently subjected to a third image etch to form a third open region 60 extending down to the second redeposited first photoresist layer 56. The third open area 60 is located at positions P1, P2, P3, and P4 of each of the first laminate 34 and the second laminate 36.

7 shows that the structure of FIG. 6 is subjected to a fourth etching to form an extended third opening region 62, and is etched at the uppermost position of the first laminate 34 and the second laminate 36 by 2 ^n-1 = 2 ^{3 -1} = 2 ² = 4 layers of insulating layer 14 and active layer 12, and four layers of insulating layer 14 and active layer 12 are additionally etched at locations P1, P2, P3.

FIG. 8 illustrates the second redeposition of the second photoresist layer 58 and the second redeposition of the first photoresist layer 56 in the structure of FIG. This exposes the landing zone 20 on the active layer 12 at each of the locations P1 through P8 of each of the first laminate 34 and the second laminate 36. The side surface 22.1 extending from the landing zone 20 is also exposed. FIG. 9 is a view showing the structure of FIG. 8 further having an overlying region 20 and a side surface 22.1 and an active layer 12 and an insulating layer 14 located at opposite positions P1 of the first laminate 34 and the second laminate 36. The etch stop layer 30 of position 64. FIG. 10 illustrates the covering of the insulating material 28 over the structure of FIG. 9 having the etch stop layer 30.

11 is a view showing the structure of FIG. 10, in which the insulating material 28, the etch stop layer 30, and the uppermost insulating layer 14 are formed at each of the positions P1 to P8 of each of the first laminate 34 and the second laminate 36. The structure behind the hole. An insulating sleeve 26 surrounds the interlayer conductor 24 in each of the holes. The interlayer conductor 24 extends to and contacts the landing zone 20 of the active layer 12 at each of the positions P1 to P8 of each of the first stepped unit 16 and the second stepped unit 18. The tops formed at the top of the interlayer conductor 24 are the global bit lines BL0 to BL15.

Figure 12 is a schematic top plan view of a three-dimensional memory structure 68 comprising first stepped cells 16 and second stepped cells 18 similar to the three dimensional structures of Figures 1 and 11, plus some associated circuitry. FIG. 12A is a diagram showing an exemplary simplified layout of the three-dimensional memory structure 68 of FIG. 12 repeated twice. The layout of Fig. 12 depicts a three dimensional vertical gate structure, although other techniques, such as a three dimensional vertical channel structure, may be utilized in the techniques discussed herein. 12 shows that the first stepped unit 16 and the second stepped unit 18 have a falling area 20 at positions P1 to P8 along the first direction 76. The global bit lines BL0 to BL15 are located above the landing area 20 and are electrically connected to the interlayer conductors 24 extending from each of the landing areas 20. The global bit lines BL0 to BL15, also referred to as the global line, are related to the global line of the metal layer ML3 located in FIG.

The tandem select line gate 74 for the string select line (SSL) gate structure 109 in Fig. 13 is also shown in Fig. 12. The tandem select line gate structure 109 is coupled to the stack of vertical gate transistors/memory cells 72 located on the ground select line (GSL) 127 and to the vertical of the word lines 125-1 to 125-N. The stack of gate transistors/memory cells 73; in this embodiment the word lines 125-1 to 125-N may be referred to as vertical lines. This connection is illustrated in FIG. 13 by conductors such as semiconductor strips 112 to 115 and semiconductor strips 102 to 105. The semiconductor strips 112 to 115 and the semiconductor strips 102 to 105 are horizontal lines, which are horizontal bit lines in this embodiment. The vertical gate transistor/memory cell 73 of each of the word lines 125-1 to 125-N serves as a two-dimensional array of memory cells.

The first block 78 and the second block 79 of the string selection gate 74 and the associated transistor/memory cell block are referred to in FIG. 12A and are located in the first stepped unit 16 and the second stepped unit 18. One side is adjacent to each other; the third block 80 and the fourth block 81 of the string selection gate 74 and the associated transistor/memory cell block are located in the first stepped unit 16 and the second stepped unit 18 The other side is adjacent to each other.

The word line 70 of Fig. 12 is a horizontal line extending perpendicular to the global bit lines BL0 to BL15 and electrically connected to the vertical gate transistor/memory cell 73 of Fig. 13. The word line 70 is a conductive structure corresponding to the horizontally extending arrangement of the vertically extending word lines 125-1 to 125-N shown in FIG.

Figure 12A illustrates how global bit lines BL0 through BL15 can connect adjacent three dimensional memory structures 68 to each of first stepped cells 16 and second stepped cells 18 in adjacent three dimensional memory structures 68. The first block 78, the second block 79, the third block 80, and the fourth block 81 of the transistor/memory elements on the side provide access. In practice, tens of thousands of three-dimensional memory structures 68 are typically formed. The cutting plane line 1-1 in Fig. 12A substantially corresponds to the cross-sectional view shown in Fig. 11. In other embodiments, the bit lines can be vertical lines and the word lines can be horizontal lines.

In the illustrated embodiment, the first block 78, the second block 79, the third block 80, and the fourth block 81 share the landing area of the first stepped unit 16 and the second stepped unit 18. 20, such that the same landing zone can be considered as part of more than one block. In other embodiments, the landing zone of the stepped unit may also be unshared such that in such a case, the landing zone may be considered part of a single block. The landing zone may belong to only one block in one direction, except that adjacent blocks share the landing zone in the same direction. In the 12th and 12th drawings, the first block 78, the second block 79, the third block 80, and the fourth block 81 have been illustrated, and for the sake of clarity, It does not include the landing zone 20. However, the landing zone may treat one or both sides as part of the block.

Figure 13 is a perspective view showing the structure of a three-dimensional inverse gate memory array. For illustrative purposes, the insulating material in the figure is removed to expose other structures. For example, the insulating layer between the semiconductor strips (eg, semiconductor strips 112-115) in the stack is removed and the insulating layer between the semiconductor strip stacks is removed.

The array of layers is formed on an insulating layer and includes a plurality of word lines 125-1 to 125-N conformal to the plurality of layers. The plurality of stacks include semiconductor strips 112, 113, 114, 115. In the same plane, the semiconductor strips are electrically coupled to corresponding bit line contact pad structures (eg, bit line contact pad structures 102B-105B, and bit line contact pad structures 112A-115A).

The illustrated word lines 125-1 through 125-N are incremented from 1 to N from the back of the overall structure to the front, and are used for even number of memory pages. For odd-numbered memory pages, the word lines 125-1 through 125-N are numbered from N to 1 from the back of the overall structure to the front.

The bit line contact pad structures 112A, 113A, 114A, 115A terminate semiconductor strips, such as semiconductor strips 112, 113, 114, 115, in active layers of each layer of the structure. As shown, the bit line contact pad structures 112A, 113A, 114A, 115A are electrically connected to different global bit lines in the patterned conductor layer (metal layer ML3) above to be connected to the decoding circuit. To select a plane in the array. These bit line contact pad structures 112A, 113A, 114A, 115A can be patterned while defining multiple stacks.

The bit line contact pad structures 102B, 103B, 104B, 105B terminate semiconductor strips, such as semiconductor strips 102, 103, 104, 105. As shown, the bit line contact pad structures 102B, 103B, 104B, 105B are electrically connected to different global bit lines in the patterned conductor layer (metal layer ML3) above to be connected to the decoding circuit. Select the plane in the array and connect to the sense amplifier and other circuitry. These bit line contact pad structures 102B, 103B, 104B, 105B can be patterned while defining multiple stacks.

Any given semiconductor strip stack is coupled to bit line contact pad structures 112A, 113A, 114A, 115A, or to bit line contact pad structures 102B, 103B, 104B, 105B, but not simultaneously coupled To both. The semiconductor strip stack has one of two opposite directions from the direction of the bit line end to the source line end and the source line end to the bit line end. For example, the stack of semiconductor strips 112, 113, 114, 115 has the direction of the bit line end to the source line end; and the stack of semiconductor strips 102, 103, 104, 105 has the source line end The direction of the end of the line. In an alternative embodiment, all of the semiconductor strips in one of the active layers of the block may terminate in the same bit line contact pad structure.

The stack of semiconductor strips 112, 113, 114, 115 terminates at one end by bit line contact pad structures 112A, 113A, 114A, 115A, through tandem select line gate structure 119, ground select line 126, characters Lines 125-1 through 125-N, ground select line 127, and terminated by source line 128 at the other end. The stack of semiconductor strips 112, 113, 114, 115 does not reach the bit line contact pad structures 102B, 103B, 104B, 105B.

The stack of semiconductor strips 102, 103, 104, 105 terminates at one end by bit line contact pad structures 102B, 103B, 104B, 105B, through tandem select line gate structure 109, ground select line 127, characters Lines 125-1 through 125-N, ground select line 126, and terminate at the other end by a source line (blocked by other portions of Figure 13). The stack of semiconductor strips 102, 103, 104, 105 does not reach the bit line contact pad structures 112A, 113A, 114A, 115A.

The memory material layer separates word lines 125-1 through 125-N from semiconductor strips 112-115 and 102-105. Similar to word lines 125-1 through 125-N, ground select line 126 and ground select line 127 are conformal to a plurality of stacks.

The global bit line and the string selection line are formed in the patterned conductor layer, such as the metal layers ML1, ML2, and ML3.

A vertical gate transistor/memory cell 72 is formed at the intersection between the semiconductor strips (e.g., semiconductor strips 112-115) and the word lines 125-1 through 125-N. In a transistor, a semiconductor strip (e.g., semiconductor strip 113) acts as a channel region for the device. Semiconductor strips (e.g., semiconductor strips 112 through 115) can serve as gate dielectrics for the transistors.

The tandem selection structure (e.g., tandem select line gate structures 119, 109) can be patterned in the same step of defining word lines 125-1 through 125-N. The electro-crystalline system is formed at the intersection between the semiconductor strips (e.g., semiconductor strips 112-115) and the tandem select structures (e.g., tandem select line gate structures 119, 109). These transistors act as a series select switch coupled to the decode circuit to select a particular stack in the array.

In an alternative example, the active layer is patterned with the word lines and the channels are vertically between the stacks. For example, please refer to the application filed on January 19, 2011, entitled "Memory Device, Manufacturing Method and Operating Method of the Same", and the inventor is U.S. Patent Application Publication No. 2012/0182808, which is commonly owned by Lu. It is considered as a reference to the full inclusion of its contents.

The three-dimensional memory structure shown in Fig. 13 uses a finger vertical gates structure similar to that applied for on April 1, 2011, entitled "Memory Architecture of 3D Array with Alternating Memory String Orientation and String". "Select Structures", the inventor is described in U.S. Patent Application Publication No. 2012/0182806, which is incorporated by reference. In some embodiments, a three-dimensional vertical channel memory element can be used instead of a three-dimensional vertical gate memory element, for example, applied on May 21, 2014, the invention name is "3D Independent Double Gate Flash Memory", and the inventor is Lu Yuting. The disclosure of U.S. Patent Application Serial No. 14/284,306, which is incorporated herein by reference.

Various techniques for joining the interlayer conductors to the landing regions on the bit line pad structures use relatively thick hard masks in the process. One type of thick hard mask uses an organic dielectric layer (ODL) as a hard mask layer. However, in order to withstand the process of multiple layers, the thickness of the organic dielectric layer hard mask layer may need to be 2,000 nm or higher. However, it is difficult to fabricate such a material having a thickness greater than about 400 nanometers using a typical spin coating process, while a thickness of 400 nanometers may be only a fraction of the desired thickness. Therefore, it may be necessary to apply the process multiple times to achieve the desired thickness.

Another type of hard mask can be made of tantalum nitride. However, the stress considerations associated with the thickness of the niobium nitride limit its effective thickness for this purpose.

Figure 14 is a schematic diagram of a three-dimensional integrated circuit including a three-dimensional inverse gate memory array. The integrated circuit 1075 includes a three-dimensional reverse gate flash memory array on a semiconductor substrate, such as the substrate 15 shown in FIG. Column decoder 1061 is coupled to a plurality of word lines 1062 and is arranged along columns in memory array 1060. Row decoder 1063 is coupled to a plurality of SSL lines 1064, including a serial selection structure, and row decoders 1063 are arranged along rows corresponding to the stacks in memory array 1060 to read and write from memory cells in array 1060. Enter the information. A plane decoder 1058 is coupled to a plurality of planes in the memory array 1060 via bit line 1059. The address is provided to the bus 1065 and is provided to the row decoder 1063, the column decoder 1061, and the plane decoder 1058. The sense amplifier and data input structure in block 1066 is coupled to row decoder 1063 via data bus 1067 in this example. The data is supplied to the data input structure in block 1066 via data input line 1071 from an input/output port on integrated circuit 1075 or a data source internal or external to other integrated circuit 1075. In the illustrated embodiment, other circuits 1074 are included in the integrated circuit, such as a general purpose processor or a special purpose application circuit, or a system chip supported by an anti-gate flash memory cell array. Functional module combination. The data is supplied from the sense amplifier in block 1066 to the input/output ports on the integrated circuit or other data destinations internal or external to the integrated circuit 1075 via the data output line 1072.

Implementing a controller that uses a bias arrangement state machine 1069 in this example, controls the application of the bias configuration supply voltage generated or provided by the voltage supply in block 1068, The bias configuration supply voltages are, for example, read, erase, write, erase verify, and write verify voltages.

The controller can be implemented using special purpose logic circuitry as is known in the art to which the invention pertains. In an alternative embodiment, the controller includes a general purpose processor that can be implemented in the same integrated circuit to execute a computer program to control the operation of the device. In other embodiments, the controller may be implemented using a combination of special purpose logic circuitry and a general purpose processor.

Words such as above, below, top, bottom, above, below may be used in the above description. These terms may be used in the specification and claims to assist the understanding of the invention, but are not intended to be limiting. When the elements are described as being, for example, the same size, having the same length, or being described as having similar aspects, dimensions, lengths, etc., can be considered as having normal manufacturing tolerances for nominal length, size, etc. equal. Any and all patent applications and publications mentioned above are incorporated herein by reference.

While the invention has been described above in terms of the preferred embodiments, these examples are intended to be illustrative and not restrictive. Various modifications and combinations can be made without departing from the spirit and scope of the invention.

10‧‧‧Three-dimensional structure

12‧‧‧ active layer

14‧‧‧Insulation

15‧‧‧Substrate

16‧‧‧First stepped unit

18‧‧‧Second stepped unit

20‧‧‧Down area

24‧‧‧Interlayer conductor

26‧‧‧Insulation sleeve

28‧‧‧Insulation materials

30‧‧‧etch stop layer

32‧‧‧ etching stop sidewall

L1~L8‧‧‧

P1~P8‧‧‧ position

Claims (10)

An integrated circuit comprising:
a plurality of blocks, wherein the plurality of blocks comprise a plurality of levels, and a plurality of the levels include a plurality of two-dimensional arrays of a plurality of corresponding memory cells Correspondingly, the two-dimensional array includes a plurality of horizontal lines, the horizontal lines are interlaced with a plurality of vertical lines, and the vertical lines are coupled to the corresponding ones of the two-dimensional arrays, wherein the areas are One or more of the plurality of levels in a given block of the block includes a plurality of corresponding contact pads, and the contact pads are electrically connected to the horizontal lines in the given block;
a plurality of global lines located on the plurality of global lines, the plurality of the global lines including a plurality of connectors, and the plurality of connectors of the connectors are coupled And a plurality of landing regions coupled to the corresponding contact pads of the plurality of regions, and wherein the plurality of regions comprise a first region And the second block is configured to be related to the first group of the first block, the first group of the contact pads being adjacent to the second group of the second block, the second group of the contact pads, the first region The landing zones of the first set of contact pads of the block and the landing zones of the second set of contact pads of the second block are each a plurality of mirror image surfaces.
For example, the integrated circuit described in claim 1 is as follows:
Each of the blocks is associated with N of the classes, and one of the classes has a hierarchical index of 1 to N;
The connectors are configured to correspond to the plurality of the global lines in the plurality of global lines such that the hierarchical index in the plurality of levels of the first set of the contact pads of the first block is from a first level And the second level is changed in a stepwise manner toward the corresponding layers of the second set of the contact pads; and the plurality of layers of the second set of the contact pads of the second block The hierarchy index changes from the first level to the second level toward the corresponding levels of the first set of contact pads in a stepwise manner.
The integrated circuit of claim 2, wherein the contacts in the first block contacting the contact pads of the first level are in contact with the second block. The connectors of the contact pads of the hierarchy are adjacent and there are no other connectors in between.
The integrated circuit of claim 1, wherein the first set of the contact pads and the second set of the contact pads are in a V-shaped arrangement.
A three-dimensional structure that includes:
a substrate;
a plurality of insulating layers and a plurality of active layers alternately stacking one of a plurality of levels formed by the first unit and a second unit;
The first unit includes a first active layer to an nth active layer, wherein the first active layer of the first unit is located at a selected level;
The second unit includes the first active layer to the nth active layer, wherein the first active layer of the second unit is located at the selected level;
The first unit and the second unit are each included in a stair step arrangement of a plurality of landing regions above the active layers;
The landing zones of the first unit and the second unit are each a plurality of mirror image surfaces;
An insulating material over the landing region; and a plurality of interlayer conductors passing through the insulating material to the stepped arrangement of the landing regions of the first unit and the second unit, Electrically contacting the landing areas of each of the first unit and the second unit.
The three-dimensional structure described in claim 5 of the patent scope further includes:
a plurality of blocks, the plurality of blocks in the plurality of blocks including a plurality of levels corresponding to the first active layer to the nth active layer, the plurality of the levels of the plurality of levels including corresponding ones a plurality of two-dimensional arrays of a plurality of memory cells, wherein the two-dimensional arrays comprise a plurality of horizontal lines, the horizontal lines being selected from one of a plurality of bit lines or a plurality of word lines, the horizontal lines Interlaced with a plurality of vertical lines, the vertical lines being selected from the plurality of bit lines or the number of the character lines not selected as the horizontal lines, wherein the plurality of the levels of the plurality of levels are connected to Corresponding to the landing zones in the active layers, the landing zones are electrically connected to the horizontal lines in a given block.
The three-dimensional structure of claim 5, wherein the mirror images are formed in a V-shaped arrangement.
A three-dimensional structure that includes:
a substrate;
a plurality of insulating layers and a plurality of active layers alternately stacking one of a plurality of levels formed by the first units and a second unit;
The first unit includes a first active layer to an nth active layer, wherein the first active layer of the first unit is located at a selected level, wherein n is a positive integer greater than 3;
The second unit includes the first active layer to an mth active layer, wherein the first active layer of the second unit is located at the selected level, where m is a positive integer less than or equal to the n;
The first unit and the second unit each include a stair step arrangement of a plurality of landing regions above the active layers, and a plurality of extending from the landing regions Side surface
The landing areas of the first unit and the second unit are a plurality of mirror image surfaces in the first active layer to the m active layer;
An etch stop layer is disposed on the landing regions of the first unit and the second unit and the side surfaces, and a plurality of etch stop sidewalls are formed along the side surfaces (etch stop Sidewalls);
An insulating layer over the etch stop layer;
a plurality of blocks, wherein the plurality of blocks include a plurality of levels corresponding to the first active layer to the nth active layer, and a plurality of the levels include a plurality of corresponding levels a plurality of two-dimensional arrays of memory cells, wherein the two-dimensional arrays comprise a plurality of horizontal lines, the horizontal lines being selected from one of a plurality of bit lines or a plurality of word lines, the horizontal lines being a plurality of vertical lines interlaced, wherein the plurality of vertical lines are selected from the plurality of bit lines or one of the plurality of horizontal lines, wherein the plurality of the hierarchical lines are connected to the corresponding ones The landing areas of the active layers such that the landing areas are electrically connected to the horizontal lines in a given block;
a plurality of interlayer conductors passing through the insulating layer and the etch stop layer to the stepped arrangement of the landing regions of the first unit and the second unit to electrically contact each of the first unit and the first The landing areas of the two units.
A three-dimensional structure as described in claim 8 wherein m is equal to n.
The three-dimensional structure of claim 8, wherein the interlayer conduction systems contacting the landing regions in the first unit and the interlayer conductors contacting the landing regions in the second unit Relatively placed, and there are no other interlayer conductors in between.