CN107359166A - A kind of storage organization of 3D nand memories and preparation method thereof - Google Patents
A kind of storage organization of 3D nand memories and preparation method thereof Download PDFInfo
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- CN107359166A CN107359166A CN201710775126.XA CN201710775126A CN107359166A CN 107359166 A CN107359166 A CN 107359166A CN 201710775126 A CN201710775126 A CN 201710775126A CN 107359166 A CN107359166 A CN 107359166A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The embodiment of the present application provides a kind of storage organization of 3D nand memories and preparation method thereof.In the preparation method, metal gates and vertical conducting layer are integrally formed, wherein, each bar gate bar on same Metal gate layer connects a face vertical conducting layer altogether, and formed and turned on wordline, so avoid the influence of silicon wafer warpage in vertical connection passage manufacturing process in the prior art, and in the method, metal gates are integrally formed with vertical conducting layer, so, this method can ensure that vertical conducting layer connects one by one with ladder Metal gate layer exactly, thus, it is possible to form effective storage wordline area.
Description
Technical field
The application is related to memory technology field, more particularly to a kind of storage organization of 3D nand memories and its preparation
Method.
Background technology
3D nand memories are a kind of flush memory devices for possessing three-dimensional stacking structure, and its memory core area is by alternately heap
Folded Metal gate layer and insulating barrier combination vertical furrow deferent composition.Under the conditions of equal area, the Metal gate layer of vertical stacking is more,
The storage density that means flush memory device is bigger, capacity is bigger.Storage organization metal gate stacking number common at present is up to number
Ten layers up to a hundred.
The Metal gate layer stacked in common 3D nand memories is ladder pattern, each ladder platform terrace with it is vertical
Metal connecting line is independently connected, and forms storage wordline (Word-line) area.The storage organization of this step appearance is generally in preceding road work
Skill is etched to form ladder pattern, and vertical metal line is then formed in postchannel process.
The formation of vertical metal line is needed first by vertical etch dielectric layer, and it is logical that formation reaches Metal gate layer connection
Road, then the deposited metal medium in vertical channel, forms the vertical metal line turned on Metal gate layer.And with 3D
NAND stacking numbers are more and more, by multilayer film stack caused by stress distribution it is uneven so that wafer sticks up in manufacturing process
Qu Chengdu is increasing.Therefore the alignment precision for causing to etch when forming vertical connection passage substantially reduces, vertical connection passage is past
Toward that can not be connected one by one with ladder Metal gate layer exactly, effective storage wordline area can not be finally formed.
The content of the invention
In view of this, this application provides a kind of storage organization of 3D nand memories and preparation method thereof, so that storage
The formation in the wordline area in structure preparation process is not influenceed by silicon wafer warpage.
In order to solve the above-mentioned technical problem, the application employs following technical scheme：
A kind of storage organization preparation method of 3D nand memories, including：
Rectangular recess is etched on substrate；
Along groove surfaces alternating deposit silicon oxide layer and sacrifice layer, silicon oxide layer/sacrifice layer alternatively layered structure is formed；
Surface planarisation is carried out to silicon oxide layer/sacrifice layer alternatively layered structure of formation；Stepped construction after planarization
In in addition to top, other rectangular groove-like of each layer；
Patterning etching is carried out to the stepped construction after the surface planarisation, it is more to be formed in stepped construction middle section
The spaced list structure of bar, and only retain in the neighboring area of stepped construction the silicon oxide layer at the list structure both ends/
Sacrifice layer alternatively layered structure；
Sacrifice layer in stepped construction after surface planarisation after etching is replaced with into metal medium, with the stacking
Structure middle section forms a plurality of metal gate lines, and multilayer vertical conducting layer is formed in the stepped construction neighboring area；
Wherein, the stepped construction middle section only includes the silicon oxide layer parallel with the substrate/sacrifice layer stackup knot
Region shared by structure part, the stepped construction neighboring area include removing the stepped construction middle section in the stepped construction
Region in addition, and the stepped construction neighboring area includes the stepped construction middle section.
Alternatively, before the stepped construction after to the surface planarisation carries out patterning etching, methods described is also wrapped
Include：
Stepped construction middle section after surface planarisation forms raceway groove hole；Charge trap is formed in the raceway groove hole
Type storage organization.
Alternatively, it is described that charge trap type storage organization is formed in the raceway groove hole, specifically include：
One layer of epitaxial layer is formed in the bottom in the raceway groove hole；The upper surface of the epitaxial layer exceedes the stepped construction most
Bottom sacrifice layer upper surface；
Electric charge barrier layer, charge trapping layer, tunnel layer and polycrystalline silicon channel are sequentially formed in the side wall in the raceway groove hole；
Silica is filled into raceway groove hole, then forms drain contact at the top in raceway groove hole.
Alternatively, it is described to be formed in the raceway groove hole after charge trap type storage organization, described to the surface
Before stepped construction after planarization carries out patterning etching, in addition to：
Depositing insulating layer in stepped construction after surface planarisation.
Alternatively, the sacrifice layer in the stepped construction after the surface planarisation by after etching replaces with metal medium,
To form a plurality of metal gate lines in the stepped construction middle section, it is vertical to form multilayer in the stepped construction neighboring area
After conductting layer, in addition to：
The interval region filling insulating barrier of interval region and vertical conducting layer between different metal grid line bar.
Alternatively, the interval region filling of the interval region and vertical conducting layer between different metal grid line bar
After insulating barrier, in addition to：
Form channel groove, connect source line, wordline, bit line and source line altogether.
Alternatively, the metal medium is tungsten.
Alternatively, the sacrifice layer in the stepped construction after the surface planarisation by after etching replaces with metal medium,
Specifically include：
Wet etching method removes the sacrifice layer in stepped construction；
The sacrifice layer region is filled with metal medium.
A kind of storage organization of 3D nand memories, including：Substrate；
Positioned at the multiple layer metal gate layer of substrate, multiple layer metal conductting layer and a plurality of wordline,
Every wordline passes through one layer of metal conduction layer and the Metal gate layer vertical connection respectively；
Wherein, the multiple layer metal gate layer and the multiple layer metal conductting layer are formed in one structure.
Alternatively, the material of the Metal gate layer and the metal conduction layer is tungsten.
Compared to prior art, the application has the advantages that：
As seen through the above technical solutions, in the preparation method of the storage organization for the 3D nand memories that the application provides,
Metal gates and vertical conducting layer are integrally formed, wherein, each bar gate bar on same Metal gate layer connects one side and vertically led altogether
Logical layer, and formed and turned on wordline, so avoid the shadow of silicon wafer warpage in vertical connection passage manufacturing process in the prior art
Ring, and in the method, metal gates are integrally formed with vertical conducting layer, so, this method can ensure vertical conducting layer
Connected one by one with ladder Metal gate layer exactly, thus, it is possible to form effective storage wordline area.
In addition, in the embodiment of the present application, the Metal gate layer ladder pattern in storage organization can be with the process of thin film deposition
In automatically form, thus, the present embodiment provide preparation method form ladder pattern without etching technics, so, compared to
The method for forming 3D nand memory storage organizations in the prior art, the preparation method that the application provides are relatively simple.
Brief description of the drawings
In order to which the technical scheme of the application is expressly understood, be described below used during the application embodiment it is attached
Figure does a brief description.
Fig. 1 is the storage organization birds-eye view for the 3D nand memories that the embodiment of the present application provides；
Fig. 2 is the storage organization top view for the 3D nand memories that the embodiment of the present application provides；
Fig. 3 is the storage organization preparation method schematic flow sheet for the 3D nand memories that the embodiment of the present application provides；
Fig. 4 A to Fig. 4 I are a series of systems of storage organization preparation method for the 3D nand memories that the embodiment of the present application provides
Partial cutaway schematic corresponding to journey.
Reference：
11：Metal gate layer, 12：Grid line bar, 13：Vertical conducting layer, 14：Wordline, 15：Top selectivity grid, 16：Position
Line, 17：Source line, 18：Bottom selectivity grid.
401：Substrate, 402：Silicon oxide layer, 403：Rectangular recess, 404：Silicon oxide layer, 405：Sacrifice layer, 406：Raceway groove
Hole, 407,411：Insulating barrier, 408：List structure, 409：Metal gate lines,
410：Vertical conducting layer, 412：Wordline, 413：Bit line, 414：Source line, 415：Top selectivity grid, 416：Bottom
Selective grid.
Embodiment
In order to avoid the vertical connection passage that is resulted in due to silicon wafer warpage can not exactly with ladder Metal gate layer one
One connection, and then the phenomenon in effective storage wordline area can not be formed, this application provides ladder Metal gate layer and vertical connection
Storage organization of the integrally formed 3D nand memories of passage and preparation method thereof.Due to metal gates and vertical conducting layer one
It is body formed, so, the storage organization and preparation method thereof can ensure vertical conducting layer exactly with ladder Metal gate layer one by one
Connection, thus, it is possible to form effective storage wordline area.
In addition, in the embodiment of the present application, the Metal gate layer ladder pattern in storage organization can be with the process of thin film deposition
In automatically form, thus, the present embodiment provide preparation method form ladder pattern without etching technics, so, compared to
The method for forming 3D nand memory storage organizations in the prior art, the preparation method that the application provides are relatively simple.
The embodiment of the application is described in detail below in conjunction with the accompanying drawings.
Fig. 1 is the storage organization birds-eye view for the 3D nand memories that the embodiment of the present application provides, and Fig. 2 is that the application is implemented
The storage organization top view for the 3D nand memories that example provides.
As depicted in figs. 1 and 2, the storage organization of the 3D nand memories includes：
Multiple layer metal gate layer 11 with step appearance, every layer of Metal gate layer include a plurality of grid line bar 12；
With all grid line bars 12 vertical conducting layer 13 connected vertically on Metal gate layer 11, wherein, each Metal gate layer
A 11 corresponding vertical conducting layers 13；
Different vertical conductting layer 13 connects one by one from different wordline 14 respectively；
The storage organization also includes：Top selectivity grid 15, bit line 16, source line 17, bottom selectivity grid 18.
Wherein, the multiple layer metal gate layer and the multilayer vertical conducting layer are formed in one structure, in this way, the storage knot
Structure can ensure that vertical conducting layer connects one by one with ladder Metal gate layer exactly, thus, it is possible to form effective storage wordline
Area.
It is to be appreciated that in Fig. 1, in order to which the 3D NAND memories of the embodiment of the present application offer are more clearly understood
Storage organization, by the internal junction of the separated displaying memory of the vertical conducting layer 13 actually to link together and Metal gate layer 11
Structure, but the position relationship that should not be construed as between the two is segmentation.
The storage organization of the 3D nand memories provided above for the embodiment of the present application.In the storage organization, metal gate
Pole and vertical conducting layer are integrally formed, wherein, each bar gate bar on same Metal gate layer connects a face vertical conducting layer altogether, and with
Wordline forms conducting, so avoids the influence of silicon wafer warpage in vertical connection passage manufacturing process in the prior art, Er Qie
In the storage organization, metal gates are integrally formed with vertical conducting layer, so, the storage organization can ensure vertical conducting layer standard
Really connected one by one with ladder Metal gate layer, thus, it is possible to form effective storage wordline area.
In addition, as shown in Fig. 2 connecting up scope compared to storage organization wordline common in the art, the application is implemented
The storage organization for the 3D nand memories that example provides has broader wordline join domain.
Fig. 3 is the storage organization preparation method schematic flow sheet for the 3D nand memories that the embodiment of the present application provides.Fig. 4 A
To part corresponding to a series of processing procedures of storage organization preparation method that Fig. 4 I are the 3D nand memories that the embodiment of the present application provides
Diagrammatic cross-section.
Referring to Fig. 3, the storage organization preparation method for the 3D nand memories that the embodiment of the present application provides includes following step
Suddenly：
S301：Silicon oxide layer deposited 402 on the substrate 401, and rectangular recess 403 is etched on silicon oxide layer 402.
Rectangular recess 403 is used for the Metal gate layer that can accommodate the stacking in storage organization to be formed.Therefore, rectangle is recessed
The depth of groove 403 is deeper.
The step has performed corresponding part section structural representation as shown in Figure 4 A.
S302：Along the surface alternating deposit silicon oxide layer 404 of groove 403 and sacrifice layer 405, silicon oxide layer/sacrifice layer is formed
Alternatively layered structure.
It is to be appreciated that in order to remove the cumbersome of lithographic patterning process from, this step can be in whole substrate 401 and recessed
Equal alternating deposit silicon oxide layer 404 and sacrifice layer 405 on the surface of groove 403, form the alternately laminated knot of silicon oxide layer/sacrifice layer
Structure.Wherein, the bottom of silicon oxide layer/sacrifice layer alternatively layered structure is sacrifice layer 405, and top is silicon oxide layer 404.
Wherein, the material of sacrifice layer can be silicon nitride.In this way, multiple O-N-O structures are formed in groove 403.
The step has performed corresponding part section structural representation as shown in Figure 4 B.
S303：Surface planarisation is carried out to the alternatively layered structure of 404/ sacrifice layer of silicon oxide layer 405 of formation.
Fig. 4 C (1) are part section structural representation corresponding to the step has performed, and it is right that Fig. 4 C (2) have performed for the step
The top view answered.
As shown in Fig. 4 C (1) and Fig. 4 C (2), in the stepped construction after planarization, the material layer of top is and the lining
The parallel plane layer in bottom.In addition to top, other rectangular groove-like of each layer.
In order to facilitate subsequent descriptions, the stepped construction after planarization can be divided into two regions：Middle section and week
Border area domain, wherein, the stepped construction middle section only includes silicon oxide layer 404/ sacrifice layer parallel with the substrate 401
Region shared by 405 laminated units, such as the region corresponding to the I in Fig. 4 C (1), the stepped construction neighboring area includes
Region in the stepped construction in addition to the stepped construction middle section, such as the region corresponding to the II in Fig. 4 C (2), and
Stepped construction neighboring area surrounds stepped construction middle section.
S304：Stepped construction middle section after surface planarisation forms multiple raceway groove holes 406, in raceway groove hole 406
Form charge trap storage organization.
Stepped construction middle section after being planarized by dry etch process etching surface, until substrate 401, is formed more
Individual raceway groove hole 406, and charge trap storage organization is formed in raceway groove hole 406.
The step has performed corresponding top view as shown in Figure 4 D.
The embodiment of the present application can use technological means customary in the art to form charge trap in raceway groove hole 406 and deposit
Storage structure.As an example, charge trap storage organization is formed in raceway groove hole 406 to be specifically included：
A1：One layer of epitaxial layer of bottom epitaxial growth in raceway groove hole 406.It is to be appreciated that the material of epitaxial layer and substrate 401
Material it is corresponding, such as when substrate 401 is silicon substrate, the material of epitaxial layer is monocrystalline silicon.
In the embodiment of the present application, the upper surface of epitaxial layer exceedes the upper table of stepped construction bottom sacrifice layer 405
Face.
A2：Silicon oxide layer, silicon nitride layer, silicon oxide layer and polycrystalline silicon channel are sequentially formed along the side wall in raceway groove hole.
A3：Silica, oxide etch, polysilicon deposition, ion implanting, finally in raceway groove hole are filled into raceway groove hole
Drain contact is formed on top.
S305：The depositing insulating layer 407 in the stepped construction formed with charge trap type storage organization, then to the table
Stepped construction after the planarization of face carries out patterning etching, to form a plurality of spaced strip in stepped construction middle section
Structure 408, and the silicon oxide layer/sacrifice layer for only retaining in the neighboring area of stepped construction the list structure both ends is alternately laminated
Structure.
Because the structure that the stepped construction middle section after etching is formed is a plurality of spaced list structure, if strip knot
, it is necessary to could stablize by supporting construction support if structure is very long, therefore, in order to preferably support the structure for etching formation,
As the alternative embodiment of the application, can may be used also before the stepped construction after to surface planarisation carries out patterning etching
With including：The depositing insulating layer 407 in the stepped construction formed with charge trap storage organization.The insulating barrier 407 it is main
Effect is that the structure formed to etching is played a supporting role.
This step can use dry etch process to pattern etching to the stepped construction part after surface planarisation, so that
To form a plurality of spaced list structure 408 in stepped construction middle section, and only protected in the neighboring area of stepped construction
Stay the silicon oxide layer/sacrifice layer alternatively layered structure at the list structure both ends.
The step has performed corresponding structure top view as shown in Figure 4 E.
S307：All sacrifice layers 405 in the stepped construction after surface planarisation are removed, form engraved structure.
All sacrifice layers 405 in the stepped construction after surface planarisation are removed using wet-etching technology, form hollow out
Structure.
The step has performed corresponding structure top view still as shown in Figure 4 E.The diagrammatic cross-section in its A2-A2 direction is as schemed
Shown in 4F (1), shown in diagrammatic cross-section such as Fig. 4 F (2) in its A1-A1 direction.
S308：The metal medium in the filling of the void region of engraved structure, to be formed in the stepped construction middle section
A plurality of metal gate lines 409, multilayer vertical conducting layer 410 is formed in the stepped construction neighboring area.
The step has performed corresponding structure top view still as shown in Figure 4 E.The diagrammatic cross-section in its A2-A2 direction is as schemed
Shown in 4G (1), shown in diagrammatic cross-section such as Fig. 4 G (2) in its A1-A1 direction.As an example, metal medium can be tungsten.
Realized by step S307 to S308 by the sacrifice layer in the stepped construction after the surface planarisation after etching
Metal medium is replaced with, to form a plurality of metal gate lines in the stepped construction middle section, on the stepped construction periphery
Region forms the purpose of multilayer vertical conducting layer.
S309：The interval region filling insulating barrier of interval region and vertical conducting layer between different metal grid line bar
411。
It is to be appreciated that in the embodiment of the present application, in step S308, in the position where original sacrifice layer 405
While filling metal medium, it is also possible between interval region and vertical conducting layer that can be between different metal grid line bar
Every metal medium on area filling.Therefore, before step S309 is performed, it is also possible to need etching to be filled in different metal grid
Interval region between lines and the metal medium on the interval region of vertical conducting layer.
The step has been performed shown in corresponding structure top view such as Fig. 4 H (1).The diagrammatic cross-section in its A2-A2 direction is as schemed
Shown in 4H (2), shown in diagrammatic cross-section such as Fig. 4 H (3) in its A1-A1 direction.
S310：Form channel groove (not shown), connect source line (not shown), wordline 412, bit line 413, source line altogether
414th, top selectivity grid 415 and bottom selectivity grid 416.
The step has performed corresponding storage organization top view as shown in fig. 41.
The structure ultimately formed by above step is the memory construction shown in Fig. 1.
Storage organization of 3D nand memories provided above for the embodiment of the present application and preparation method thereof.In the preparation
Metal gates and vertical conducting layer are integrally formed in method, wherein, each bar gate bar on same Metal gate layer connects one side altogether
Vertical conducting layer, and formed and turned on wordline, so avoid wafer in vertical connection passage manufacturing process in the prior art and stick up
Bent influence, and in the method, metal gates are integrally formed with vertical conducting layer, so, this method can ensure vertically
Conductting layer connects one by one with ladder Metal gate layer exactly, thus, it is possible to form effective storage wordline area.
In addition, in the embodiment of the present application, the Metal gate layer ladder pattern in storage organization can be with the process of thin film deposition
In automatically form, thus, the present embodiment provide preparation method form ladder pattern without etching technics, so, compared to
The method for forming 3D nand memory storage organizations in the prior art, the preparation method that the application provides are relatively simple.
Embodiments herein is these are only, is not limited to the application.To those skilled in the art,
The application can have various modifications and variations.All any modifications made within spirit herein and principle, equivalent substitution,
Improve etc., it should be included within the scope of claims hereof.
Claims (10)
- A kind of 1. storage organization preparation method of 3D nand memories, it is characterised in that including：Rectangular recess is etched on substrate；Along groove surfaces alternating deposit silicon oxide layer and sacrifice layer, silicon oxide layer/sacrifice layer alternatively layered structure is formed；Surface planarisation is carried out to silicon oxide layer/sacrifice layer alternatively layered structure of formation；Removed in stepped construction after planarization Outside top, other rectangular groove-like of each layer；Patterning etching is carried out to the stepped construction after the surface planarisation, to form a plurality of phase in stepped construction middle section The list structure being mutually spaced, and only retain in the neighboring area of stepped construction the silicon oxide layer/sacrifice at the list structure both ends Layer alternatively layered structure；Sacrifice layer in stepped construction after surface planarisation after etching is replaced with into metal medium, with the stepped construction Middle section forms a plurality of metal gate lines, and multilayer vertical conducting layer is formed in the stepped construction neighboring area；Wherein, the stepped construction middle section only includes the silicon oxide layer parallel with the substrate/sacrifice multilayer laminated structure portion Region shared by point, the stepped construction neighboring area are included in the stepped construction in addition to the stepped construction middle section Region, and the stepped construction neighboring area includes the stepped construction middle section.
- 2. according to the method for claim 1, it is characterised in that the stepped construction after to the surface planarisation carries out figure Before caseization etching, methods described also includes：Stepped construction middle section after surface planarisation forms raceway groove hole；Charge trap type is formed in the raceway groove hole to deposit Storage structure.
- 3. according to the method for claim 2, it is characterised in that described that the storage of charge trap type is formed in the raceway groove hole Structure, specifically include：One layer of epitaxial layer is formed in the bottom in the raceway groove hole；The upper surface of the epitaxial layer exceedes the stepped construction bottom Sacrifice layer upper surface；Electric charge barrier layer, charge trapping layer, tunnel layer and polycrystalline silicon channel are sequentially formed in the side wall in the raceway groove hole；Silica is filled into raceway groove hole, then forms drain contact at the top in raceway groove hole.
- 4. according to the method for claim 2, it is characterised in that described that the storage of charge trap type is formed in the raceway groove hole After structure, before the stepped construction to after the surface planarisation carries out patterning etching, in addition to：Depositing insulating layer in stepped construction after surface planarisation.
- 5. according to the method described in claim any one of 1-4, it is characterised in that after the surface planarisation by after etching Sacrifice layer in stepped construction replaces with metal medium, to form a plurality of metal gate lines in the stepped construction middle section, After multilayer vertical conducting layer being formed in the stepped construction neighboring area, in addition to：The interval region filling insulating barrier of interval region and vertical conducting layer between different metal grid line bar.
- 6. according to the method for claim 4, it is characterised in that the interval region between different metal grid line bar with And after the interval region filling insulating barrier of vertical conducting layer, in addition to：Form channel groove, connect source line, wordline, bit line and source line altogether.
- 7. according to the method described in claim any one of 1-4, it is characterised in that the metal medium is tungsten.
- 8. according to the method described in claim any one of 1-4, it is characterised in that after the surface planarisation by after etching Sacrifice layer in stepped construction replaces with metal medium, specifically includes：Wet etching method removes the sacrifice layer in stepped construction；The sacrifice layer region is filled with metal medium.
- A kind of 9. storage organization of 3D nand memories, it is characterised in that including：Substrate；Positioned at the multiple layer metal gate layer of substrate, multiple layer metal conductting layer and a plurality of wordline,Every wordline passes through one layer of metal conduction layer and the Metal gate layer vertical connection respectively；Wherein, the multiple layer metal gate layer and the multiple layer metal conductting layer are formed in one structure.
- 10. storage organization according to claim 9, it is characterised in that the Metal gate layer and the metal conduction layer Material is tungsten.
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| CN108649034A (en) * | 2018-05-11 | 2018-10-12 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN108807405A (en) * | 2018-06-12 | 2018-11-13 | 长江存储科技有限责任公司 | Three-dimensional storage and preparation method thereof |
| WO2020051826A1 (en) * | 2018-09-13 | 2020-03-19 | Yangtze Memory Technologies Co., Ltd. | Novel 3d nand memory device and method of forming the same |
| CN112164698A (en) * | 2017-11-21 | 2021-01-01 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
| CN116206640A (en) * | 2022-08-18 | 2023-06-02 | 北京超弦存储器研究院 | Memory, manufacturing method thereof and read-write control method |
| WO2023097662A1 (en) * | 2021-12-03 | 2023-06-08 | 华为技术有限公司 | Memory and electronic device |
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