KR20160021376A - Semiconductor device - Google Patents

Abstract

The present invention relates to a three-dimensional semiconductor memory device having memory cells which are arranged in a three-dimension structure. More particularly, since an insulating layer integrally supports neighboring gate electrodes, a structural stability of a stacked structure can be improved. Also, a problem such as a pattern deformation and a resistance increase of the gate electrodes can be solved. Moreover, since common source lines are separated from a substrate to be formed as conductive patterns, the generation of an error such as a internal seam of the common source lines can be ameliorated.

Description

[0001]

The present invention relates to a semiconductor device, and more particularly, to a three-dimensional semiconductor memory device having three-dimensionally arranged memory cells.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price required by consumers. In the case of semiconductor devices, the degree of integration is an important factor in determining the price of the product, and therefore, an increased degree of integration is required in particular. In the case of a conventional two-dimensional or planar semiconductor device, the degree of integration is largely determined by the area occupied by the unit memory cell, and thus is greatly influenced by the level of the fine pattern forming technique. However, the integration of the two-dimensional semiconductor device is increasing, but it is still limited, because the ultrafast equipment is required for the miniaturization of the pattern.

In order to overcome these limitations, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass-produce a three-dimensional semiconductor memory device, there is a demand for a process technology capable of reducing the manufacturing cost per bit compared to that of the two-dimensional semiconductor device and realizing reliable product characteristics.

A problem to be solved by the present invention is to provide a three-dimensional semiconductor device with improved structural stability and optimized for high integration.

According to the concept of the present invention, a semiconductor device includes: an insulating film provided on a substrate in one body; A first gate electrode and a second gate electrode disposed on the insulating film and extending in a first direction parallel to an upper surface of the substrate; A first channel structure connected to the substrate through the insulating film and the first gate electrode; A second channel structure connected to the substrate through the insulating film and the second gate electrode; And a contact which is disposed between the first gate electrode and the second gate electrode and penetrates the insulating film and connects to a common source region of the first conductivity type in the substrate. At this time, the first gate electrode and the second gate electrode may be spaced apart from each other in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction, at a vertically same level.

The first gate electrode and the second gate electrode form a unit structure. The plurality of unit structures are stacked on the substrate repeatedly. The first gate electrode and the second gate electrode are alternately stacked on the substrate. Wherein the first gate electrode structure and the second gate electrode structure define a first gate electrode structure and the second gate electrodes alternately stacked with the insulating films define a second gate electrode structure, And may be spaced apart from each other in the second direction across the contacts.

Each of the first gate electrode and the second gate electrode includes a depressed sidewall, the depressed sidewalls adjacent the contact, and from a planar viewpoint, the contact may be surrounded by the depressed sidewalls.

The distance between the inner wall of the insulating film adjacent to the contact and the contact may be shorter than the distance between each of the recessed sidewalls and the contact.

The insulating film supports both the first and second gate electrodes, and the insulating film includes a through hole in a region between the first and second gate electrodes, and the contact can be provided in the through hole.

Wherein the contacts are provided in a plurality and are spaced apart from each other along the first direction, wherein each of the first gate electrode and the second gate electrode includes a projecting sidewall, As shown in FIG.

The semiconductor device may further include a common source line extending in the first direction. At this time, the common source line may be disposed on the contacts, and may be electrically connected to the contacts.

The semiconductor device may further include a common source line extending in the first direction. At this time, the common source line may be disposed on the contacts, and may be electrically connected to the contacts.

The contacts are provided in a plurality and are arranged apart from each other along the first direction, and at least one of the contacts can be connected to a well pickup region of a second conductivity type in the substrate.

The semiconductor device may further include a gate dielectric layer covering the top and bottom surfaces of each of the first and second gate electrodes and interposed between the first and second gate electrodes and the first and second channel structures, . At this time, the gate dielectric layers may extend to cover the upper surface and the inner wall of the insulating layer.

Wherein the first channel structures are provided in a plurality and are spaced apart from each other along the first direction and the second channel structures are provided in a plurality and are arranged apart from each other along the first direction, Wherein the first channel structures and the second channel structures are spaced apart from each other along the first direction and the insulating film is provided between the sidewalls of the first channel structures, Sidewalls and sidewalls of the contacts.

The semiconductor device may further include: a first vertical insulator interposed between the first gate electrode and the first channel structure; And a second vertical insulator interposed between the second gate electrode and the second channel structure. At this time, each of the first and second vertical insulators may include a charge storage film.

The first channel structure may pass through the first gate electrode structure and the second channel structure may pass through the second gate electrode structure.

According to another aspect of the present invention, a semiconductor device includes: an insulating film disposed on a substrate; And a first gate electrode and a second gate electrode disposed on the insulating film and extending in a first direction parallel to an upper surface of the substrate. Wherein the first gate electrode comprises first protruding sidewalls defined by first depressed sidewalls and two neighboring first depressed sidewalls, the second gate electrode comprises second depressed sidewalls, And second protruding sidewalls defined by two adjacent second sidewall sidewalls. Wherein the insulating film is integrally provided to support both the first and second gate electrodes, and wherein the first gate electrode and the second gate electrode are formed at a vertically same level, parallel to an upper surface of the substrate, In a second direction intersecting the first direction.

The semiconductor device may further include a common source line that is vertically spaced from the substrate, the first gate electrode, and the second gate electrode and extends in the first direction. At this time, from a plan viewpoint, the common source line may be disposed between the first gate electrode and the second gate electrode.

Wherein the insulating film, the first gate electrode, and the second gate electrode are provided in a plurality of layers and are repeatedly stacked on the substrate, the first gate electrodes are vertically stacked to each other with the insulating films interposed therebetween, Gate electrode structure, and the second gate electrodes may be stacked vertically with respect to each other with the insulating films interposed therebetween to define a second gate electrode structure. From a plan viewpoint, the first gate electrode structure and the second gate electrode structure may be spaced apart from each other in the second direction with the common source line interposed therebetween.

The semiconductor device may further include a contact hole penetrating the insulating film and disposed between the first gate electrode and the second gate electrode and vertically and electrically connecting the substrate and the common source line.

At least one of the first depressed sidewalls and at least one of the second depressed sidewalls is adjacent to the contact, and from a planar viewpoint, the contact is formed between the one first depressed sidewalls and the one second depressed sidewalls As shown in FIG.

The semiconductor device may include first channel structures arranged in the first direction, the first channel structures being connected to the substrate through the first gate electrode; And second channel structures connected to the substrate through the second gate electrode and arranged in the first direction.

According to another aspect of the present invention, a semiconductor device includes: a laminated structure including gate electrodes and insulating films alternately and repeatedly stacked on a substrate; A common source line disposed on the laminated structure and extending in a first direction parallel to an upper surface of the substrate; And channel structures passing through the laminate structure and spaced apart from each other along the first direction. At this time, from a plan viewpoint, the gate electrodes are separated from each other in the second direction with the common source line interposed therebetween, and from the plan view point, the insulating films are separated from each other in the second direction with the common source line interposed therebetween . The second direction may be parallel to the upper surface of the substrate and intersect with the first direction.

The three-dimensional semiconductor memory device according to the present invention can improve the structural stability of the stacked structure because the insulating film supports the neighboring gate electrodes integrally. In addition, problems such as pattern deformation and resistance increase of the gate electrodes can be improved. Furthermore, since the common source lines can be formed in the conductive patterns apart from the substrate, the occurrence of defects such as seam inside the common source lines can be improved.

1 is a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to embodiments of the present invention.
2 is a schematic plan view of a three-dimensional semiconductor memory device according to embodiments of the present invention.
FIG. 3A is a plan view showing the cell region CR of the three-dimensional semiconductor memory device according to one embodiment of the present invention, which is an enlarged view of the region M of FIG.
FIG. 3B is a cross-sectional view taken along the line I-I 'in FIG. 3A.
3C is a cross-sectional view taken along line II-II 'in FIG. 3A.
4A to 4G are cross-sectional views corresponding to line I-I 'in FIG. 3A, illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention.
5A and 5B illustrate a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention, which are cross-sectional views corresponding to line II-II 'in FIG. 3A.
6A is a plan view showing the cell region CR of the three-dimensional semiconductor memory device according to another embodiment of the present invention, which is an enlarged view of the region M in FIG.
6B is a cross-sectional view taken along line I-I 'of FIG. 6A.
6C is a cross-sectional view taken along line II-II 'of FIG. 6A.
FIG. 7A is a plan view showing the cell region CR of the three-dimensional semiconductor memory device according to still another embodiment of the present invention, which is an enlarged view of the M region of FIG. 2. FIG.
7B is a cross-sectional view taken along the line I-I 'in FIG. 7A.
8A to 8C illustrate a method of manufacturing a three-dimensional semiconductor memory device according to another embodiment of the present invention, which are cross-sectional views corresponding to line I-I 'in FIG. 7A
9 is a schematic block diagram illustrating an example of a memory system including a three-dimensional semiconductor memory device according to embodiments of the present invention.
10 is a schematic block diagram showing an example of a memory card having a three-dimensional semiconductor memory device according to embodiments of the present invention.
11 is a schematic block diagram showing an example of an information processing system for mounting a three-dimensional semiconductor memory device according to embodiments of the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be embodied in various forms and various modifications may be made. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thickness of the components is exaggerated for an effective description of the technical content. The same reference numerals denote the same elements throughout the specification.

Embodiments described herein will be described with reference to cross-sectional views and / or plan views that are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention. Although the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various components, these components should not be limited by these terms. These terms have only been used to distinguish one component from another. The embodiments described and exemplified herein also include their complementary embodiments.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms "comprises" and / or "comprising" used in the specification do not exclude the presence or addition of one or more other elements.

1 is a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to embodiments of the present invention.

1, a cell array of a three-dimensional semiconductor memory device according to embodiments of the present invention includes a common source line CSL, a plurality of bit lines BL, a common source line CSL, And a plurality of cell strings CSTR disposed between the plurality of cell strings BL.

The common source line CSL may be a conductive thin film disposed on the substrate 100 or an impurity region formed in the substrate 100. In this embodiment, the common source line CSL may be conductive patterns (e.g., metal lines) disposed on the substrate 100, spaced from the substrate 100. The bit lines BL may be conductive patterns (e.g., metal lines) spaced from the substrate 100 and disposed on the substrate 100. In the present embodiments, the bit lines BL may be vertically spaced apart from the common source line CSL. The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR may be connected in parallel. The cell strings CSTR may be connected in common to the common source line CSL. That is, a plurality of the cell strings CSTR may be disposed between the plurality of bit lines BL and the common source line CSL. According to one embodiment, the common source lines CSL are provided in plural and can be two-dimensionally arranged. Here, electrically the same voltage may be applied to the common source lines CSL, or each of the common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, And a plurality of memory cell transistors MCT arranged between the memory cells GST and SST. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be connected in common to the sources of the ground selection transistors GST. In addition, a ground selection line GSL, a plurality of word lines WL0-WL5 and a plurality of string selection lines SSL, which are disposed between the common source line CSL and the bit lines BL, May be used as gate electrodes of the ground selection transistor GST, the memory cell transistors MCT and the string selection transistors SST, respectively. In addition, each of the memory cell transistors MCT may include a data storage element.

2 is a schematic plan view of a three-dimensional semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 2, the substrate 100 includes a cell region CR and a peripheral circuit region PR around the cell region CR. The substrate 100 may be a single crystal epitaxial layer grown on a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline silicon substrate.

According to one embodiment, the substrate 100 may have a first conductivity type. The substrate 100 includes a well impurity layer 100n of a second conductivity type opposite to the first conductivity type and a first conductivity type pocket-well impurity layer 100p in the well impurity layer 100n. . In detail, the well impurity layer 100n may be formed by doping the impurity of the second conductivity type into the substrate 100. [ The pocket-well impurity layer 100p may be formed by doping the impurity of the first conductivity type into the well impurity layer 100n.

In one embodiment, memory cell arrays may be formed on the pocket-well impurity layer 100p of the cell region CR, and peripheral circuits (e.g., PMOS and NMOS transistors) The well impurity layer 100n in the peripheral circuit region PR, and the substrate 100 in the peripheral circuit region PR. In particular, a plurality of stacked structures SS may be disposed on the pocket-well impurity layer 100p. Each of the stacked structures SS may include a plurality of gate electrodes 155a and 155b stacked on the substrate 100 vertically. This will be described in more detail with reference to FIGS. 3A to 3C.

According to these embodiments, the well pick-up regions 125 may be disposed in the pocket-well impurity layer 100p around the stacked structures SS. According to an embodiment of the present invention, the well pick-up regions 125 may be disposed between the stacked structures SS. This will be described in more detail with reference to Figs. 6A to 6C. The well pick-up regions 125 may be formed by doping impurities of the same conductivity type as the pocket-well impurity layer 100p. The impurity concentration in the well pickup region 125 may be higher than the impurity concentration in the pocket-well impurity layer 100p. According to these embodiments, a high erase voltage (for example, about 20 V) is applied to the pocket-well impurity layer 100p through the well pickup regions 125 in the erasing operation of the three-dimensional semiconductor memory device . At this time, since the well pickup regions 125 are disposed between the periphery of the stacked structures SS and the stacked structures SS, a uniform erase voltage is provided to the pocket-well impurity layer 100p .

Further, the PMOS transistors (PMOS) may be disposed on the well impurity layer 100n of the peripheral circuit region PR and the NMOS transistors NMOS may be disposed on the substrate 100 of the peripheral circuit region PR .

Example  One

FIG. 3A is a plan view showing the cell region CR of the three-dimensional semiconductor memory device according to one embodiment of the present invention, which is an enlarged view of the region M of FIG. FIG. 3B is a cross-sectional view taken along line I-I 'of FIG. 3A, and FIG. 3C is a cross-sectional view taken along line II-II' of FIG. 3A.

Referring to FIGS. 3A to 3C, a structure in which gate electrodes 155a and 155b and insulating films 110 are alternately and repeatedly stacked may be disposed on a substrate 100. FIG. The substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may include common source regions 120 doped with impurities. From a plan viewpoint, the common source regions 120 may correspond to the shapes of the through-holes 210 and may be, for example, circular. The common source regions 120 may be spaced apart from each other and arranged along a first direction D1 parallel to an upper surface of the substrate. The insulating films 110 may include a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, or a silicon nitride film.

In the present embodiment, the gate electrodes 155a and 155b may include first gate electrodes 155a and second gate electrodes 155b. In addition to the first and second gate electrodes 155a and 155b, other gate electrodes may be disposed apart from each other. However, in this embodiment, the first and second gate electrodes 155a and 155b For example. The first gate electrodes 155a may be alternately stacked with the insulating layers 110 interposed therebetween to define a first gate electrode structure ES1. The second gate electrodes 155b may be alternately stacked with the insulating films 110 interposed therebetween to define a second gate electrode structure ES2. The first gate electrode structure ES1 may be spaced apart from the second gate electrode structure ES2 in the second direction D2. The second direction D2 may be parallel to the upper surface of the substrate and intersect with the first direction D1. The first gate electrode structure ES1 and the second gate electrode structure ES2 may have a line shape extending in the first direction D1.

The gate electrodes 155a and 155b disposed at the lowermost portions of the first and second gate electrode structures ES1 and ES2 are connected to the ground selection transistors GST described with reference to FIG. As shown in FIG. The gate electrodes 155a and 155b located at the top of the first and second gate electrode structures ES1 and ES2 are connected to the gate of the string selection transistors SST, May be used as the electrodes 155a and 155b. The gate electrodes 155a and 155b between the uppermost and lowermost gate electrodes can be used as the gate electrodes of the memory cell transistors MCT described with reference to FIG.

From a plan viewpoint, the common source regions 120 may be disposed between the first gate electrode structure ES1 and the second gate electrode structure ES2. The lower insulating film 105 may be disposed between the substrate 100 and the first gate electrode 155a at the lowermost part and between the substrate 100 and the second gate electrode 155b at the lowermost part. The lower insulating film 105 may be, for example, a silicon oxide film. The lower insulating layer 105 may have a thickness smaller than that of the insulating layers 110.

In another aspect, each of the laminated structures SS according to the present embodiment may include repeatedly stacked unit structures UT. Each of the unit structures UT includes at least one of the insulating film 110, the first gate electrode 155a disposed on one side of the insulating film 110, and the first gate electrode 155a disposed on the other side of the insulating film 110. [ And a second gate electrode 155b. That is, the first gate electrode 155a and the second gate electrode 155b may be simultaneously disposed on a single insulating layer 110 (see FIG. 3C).

A plurality of channel structures CS1 and CS2 extend through the unit structures UT in a third direction D3 and may be electrically connected to the substrate 100. [ The third direction D3 may be a direction perpendicular to both the first direction D1 and the second direction D2. The channel structures CS1 and CS2 may be spaced apart from each other along the first direction D1 in plan view, as shown in FIG. 3A. The channel structures CS1 and CS2 may include first channel structures CS1 and second channel structures CS2.

The first channel structures CS1 may pass through the insulating films 110 and the first gate electrodes 155a and the second channel structures CS2 may pass through the insulating films 110 and the first gate electrodes 155a. And can penetrate the second gate electrodes 155b. That is, both the first and second channel structures CS1 and CS2 may pass through the insulating films 110. [ As described above, since the first and second gate electrode structures ES1 and ES2 are spaced apart from each other in the second direction D2, the first and second channel structures CS1 and CS2 are also separated from each other And may be spaced apart from each other in the second direction D2. The first channel structures CS1 may be arranged in a zigzag manner along the first direction D1. The second channel structures CS2 may be arranged in a zigzag manner along the first direction D1.

Each of the first channel structures CS1 includes a first vertical semiconductor pattern 130a electrically connected to the substrate 100 through the first gate electrode structure ES1 and the insulating films 110, And may include a first connecting semiconductor pattern 135a. The first vertical semiconductor pattern 130a may cover the inner walls of the first gate electrode structure ES1 and the insulating films 110. [ The first vertical semiconductor pattern 130a may be an open pipe shape or a macaroni shape. The first vertical semiconductor pattern 130a may be spaced apart from the substrate 100 without contacting the substrate 100. [ The first connected semiconductor pattern 135a may be formed in a closed pipe shape or a macaroni shape. The inside of the first connecting semiconductor pattern 135a may be filled with a vertical insulating pattern 150. [ The first connection semiconductor pattern 135a may be in contact with the inner wall of the first vertical semiconductor pattern 130a and the substrate 100.

The first semiconductor patterns 130a and 135a may include a semiconductor material. For example, the first semiconductor patterns 130a and 135a may include silicon (Si), germanium (Ge), or a mixture thereof. The first semiconductor patterns 130a and 135a may be impurity-doped semiconductors or impurity- It is possible. In addition, the first semiconductor patterns 130a and 135a may have a crystal structure of at least one of single crystal, amorphous, and polycrystalline. The first semiconductor patterns 130a and 135a may be in an unselected state or may be doped with an impurity having the same conductivity type as that of the substrate 100. [

Each of the second channel structures CS2 includes a second vertical semiconductor pattern 130b electrically connected to the substrate 100 through the second gate electrode structure ES2 and the insulating films 110, And a second connected semiconductor pattern 135b. The second semiconductor patterns 130b and 135b may be the same as those described in the first semiconductor patterns 130a and 135a.

A conductive pad 160 may be provided on each of the first and second channel structures CS1 and CS2. The upper surface of the conductive pad 160 may be substantially coplanar with the uppermost insulating layer 110 and the bottom surface of the conductive pad 160 may be in contact with the first semiconductor patterns 130a, And can directly contact the semiconductor patterns 130b and 135b. The conductive pad 160 may be an impurity region doped with an impurity, or may include a conductive material.

Vertical insulators 140 may be interposed between the first and second gate electrode structures ES1 and ES2 and the first and second channel structures CS1 and CS2. The vertical insulators 140 may be in the form of a pipe or a macaroni with open upper and lower ends. According to one embodiment, the vertical insulators 140 may be in contact with the substrate 100.

The vertical insulators 140 may comprise memory elements of a flash memory device. That is, the vertical insulators 140 may include a charge storage layer (not shown) of the flash memory device. Alternatively, the vertical insulators 140 may comprise a thin film capable of storing information (e.g., a thin film for a phase change memory or a thin film for a variable resistance memory). According to one embodiment, each of the vertical insulators 140 may include the charge storage film and the tunnel insulating film (not shown) sequentially stacked. According to another embodiment, each of the vertical insulators 140 may further include a blocking insulating film (not shown) interposed between the charge storage film and the first and second gate electrodes 155a and 155b have. According to another embodiment, each of the vertical insulators 140 includes a capping layer (not shown) interposed between the first and second channel structures CS1 and CS2 and the insulating layers 110 You may.

The charge storage layer may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a laminated trap layer. The tunnel insulating layer may include a material having a band gap larger than that of the charge storage layer. For example, the tunnel insulating film may be a silicon oxide film. The blocking insulating layer may include a material having a larger energy band gap than the charge storage layer. For example, the blocking insulating film may be a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film. The capping film may include at least one of a silicon film, a silicon oxide film, a polysilicon film, a silicon carbide film, and a silicon nitride film, and may include a material different from the insulating films 110. As another example, the capping film may be a high-k film such as a tantalum oxide film (Ta ₂ O ₅ ), a titanium oxide film (TiO ₂ ), a hafnium oxide film (HfO ₂ ), and / or a zirconium oxide film (ZrO ₂ ).

The gate dielectric layers 180 covering the upper surfaces and the lower surfaces of the first and second gate electrodes 155a and 155b are formed between the first and second gate electrodes 155a and 155b and the insulating layers 110 As shown in FIG. In addition, the gate dielectric layers 180 may be provided between the first and second gate electrodes 155a and 155b and the first and second channel structures CS1 and CS2. According to one embodiment, the vertical insulators 140 may be provided between the first and second channel structures CS1 and CS2 and the gate dielectric layers 180. [ Further, the gate dielectric layers 180 may further extend to cover the inner walls of the insulating layers 110. The inner walls of the insulating layers 110 may define the through holes 210.

Each of the gate dielectric layers 180 may be formed of one thin film or a plurality of thin films. According to one embodiment, each of the gate dielectric layers 180 may comprise a blocking insulating layer (not shown) of a charge trapped flash memory device. According to another embodiment, each of the gate dielectric layers 180 may include a plurality of blocking insulating layers (not shown). According to another embodiment, each of the gate dielectric layers 180 may comprise a charge storage layer (not shown) and a blocking insulating layer (not shown) of a charge trapped flash memory device.

The through-holes 210 may be formed between the first and second gate electrode structures ES1 and ES2. The through holes 210 may be formed in the insulating films 110 and may be spaced apart from each other along the first direction D1. The through holes 210 may be vertically communicated through the insulating films 110.

The contacts 170 connecting to the common source regions 120 may be disposed in the through holes 210. [ The contacts 170 may pass through the insulating films 110 and be disposed between the first and second gate electrode structures ES1 and ES2. In other words, the first gate electrode structure ES1 and the second gate electrode structure ES2 may be spaced apart from each other in the second direction D2 with the contacts 170 therebetween. However, each of the insulating films 110 is integrally formed, and may not be separated by the contacts 170 in plan view. That is, the insulating films 110 may surround the sidewalls of the first channel structures CS1, the sidewalls of the second channel structures CS2, and the sidewalls of the contacts 170.

Spacer films 175 may be interposed between the contacts 170 and the insulating films 110 and between the contacts 170 and the first and second gate electrode structures ES1 and ES2 have. Through the spacer films 175, the first and second gate electrodes 155a and 155b and the contacts 170 can be electrically isolated from each other. The spacer films 175 may include a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, or a silicon nitride film.

Common source lines (SS) across the stacked structures SS are formed on the stacked structures SS including the first and second gate electrode structures ES1 and ES2 and the insulating films 110 CSL) may be disposed. The common source lines CSL may extend in the first direction D1 and may be spaced apart from each other along the second direction D2. In the present embodiment, the common source lines CSL may be conductive patterns (e.g., metal lines) vertically spaced from the upper surface of the substrate 100.

The common source lines CSL may be formed on the contacts 170 and may be electrically connected to the contacts 170. From a planar viewpoint, the common source lines CSL may overlap with the contacts 170 arranged apart from each other along the first direction D1. Although not shown, contact plugs may be disposed between the common source lines CSL and the contacts 170, wherein the common source lines CSL and the contacts 170 are connected through the contact plugs, Can be electrically connected. A voltage may be applied to the common source regions 120 connected to the contacts 170 through the common source lines CSL disposed apart from the substrate 100. [

A first interlayer insulating film 190 covering the common source lines CSL may be disposed. A bit line plug BPLG may be electrically connected to the conductive pad 160 through the first interlayer insulating film 190. [

Bit lines BL across the stacked structures SS may be disposed on the first interlayer insulating film 190. [ The bit lines BL may extend in the second direction D2 and may be spaced apart from each other along the first direction D1. The bit lines BL may intersect the common source lines CSL while being vertically spaced from the common source lines CSL. The bit lines BL may be connected to the plurality of conductive pads 160 through a plurality of the bit line plugs BPLG. Furthermore, each of the bit lines BL may be simultaneously connected to the first channel structure CS1 and the second channel structure CS2 which are overlapped in the second direction D2 in a plan view.

Referring again to FIGS. 3A and 3B, each of the first gate electrodes 155a of the first gate electrode structure ES1 includes first depression sidewalls 155as and first projecting sidewalls 155ap . Each of the second gate electrodes 155b of the second gate electrode structure ES2 may include second recessed sidewalls 155bs and second protruded sidewalls 155bp.

From a plan viewpoint, the first depression sidewalls 155as may be adjacent to the contacts 170. The first depressed sidewalls 155as may correspond to a planar shape of the through holes 210 and may surround the contacts 170 in a state of being spaced apart from the contacts 170. [ The first distance L 1 between the inner wall of the insulating layer 110 defining the through hole 210 and the contact 170 is greater than the first distance L 1 between the first recessed sidewall 155as and the contact 170, May be shorter than the second distance (L2) The second recessed sidewalls 155bs may be the same as those described in the first recessed sidewalls 155as.

Each of the first protruding sidewalls 155ap may be located between the contacts 170 that are adjacent to each other. Further, each of the first projecting sidewalls 155ap may be defined between the adjacent first sidewall sidewalls 155as. The third distance L3 between the first protruding sidewall 155ap and the second protruding sidewall 155bp is greater than the fourth distance between the first sinking sidewall 155as and the second sinking sidewall 155bs L4). The second projecting sidewalls 155bp may be the same as those described in the first projecting sidewalls 155ap.

The first recessed sidewall 155as and the second recessed sidewall 155bs face each other in the second direction D2 and the first protruded sidewall 155ap and the second protruded sidewall 155bp are spaced apart from each other, Can face each other in two directions (D2).

The three-dimensional semiconductor memory device according to an embodiment of the present invention can have improved structural stability. Although the first and second gate electrodes 155a and 155b are separated from each other and separated from each other, each of the insulating films 110 integrally includes the first and second gate electrodes 155a and 155b, Because they support it. That is, since the insulating films 110 connect the first and second gate electrode structures ES1 and ES2 even if the stacked number of stacked structures SS increases, the stacked structures SS Can be prevented. In addition, problems such as pattern deformation and resistance increase of the first and second gate electrodes 155a and 155b, which may be caused by the stress of the metal conductive film, can be improved.

Furthermore, since the common source lines CSL may be formed of conductive patterns (for example, metal lines) spaced apart from the substrate, defects such as a seam inside the common source lines CSL The occurrence can be improved. Thus, even if the length of the common source lines CSL is increased, the problem of resistance increase can be solved and the problem of poor connection with the common source regions 120 in the substrate can be overcome.

FIGS. 4A to 4G and FIGS. 5A and 5B are cross-sectional views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. 4A to 4G are cross-sectional views corresponding to line I-I 'in FIG. 3A. 5A and 5B are cross-sectional views corresponding to line II-II 'in FIG. 3A.

3A and 4A, a thin film structure TS may be formed by alternately and repeatedly depositing sacrificial films 151 and insulating films 110 on a substrate 100. The substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

The sacrificial layers 151 may be formed of a material that can be etched with respect to the insulating layers 110 with an etching selectivity. According to the present embodiment, the sacrificial films 151 and the insulating films 110 have a high etch selectivity in a wet etching process using a chemical solution, and a low etch selectivity in a dry etching process using an etching gas Lt; / RTI >

According to one example, the sacrificial films 151 may be formed to have the same thickness. However, according to another example, the sacrificial films 151 at the lowermost and uppermost portions of the sacrificial films 151 may be formed thicker than the sacrificial films 151 located therebetween. The insulating films 110 may have the same thickness or a part of the insulating films 110 may have different thicknesses.

The sacrificial layers 151 and the insulating layers 110 may be formed by thermal chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (CVD), physical vapor deposition (CVD) Can be deposited using an Atomic Layer Deposition (ALD) process.

According to one embodiment, the sacrificial films 151 and the insulating films 110 are formed of an insulating material, and may have different etch selectivities. For example, the sacrificial films 151 may include a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, or a silicon nitride film. The insulating films 110 may include a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, or a silicon nitride film, but may be a material other than the sacrificial films 151. For example, the sacrificial layers 151 may be formed of a silicon nitride layer, and the insulating layers 110 may be formed of a silicon oxide layer. Meanwhile, according to another example, the sacrificial films 151 may be formed of a conductive material, and the insulating films 110 may be formed of an insulating material.

In addition, a lower insulating film 105 may be formed between the substrate 100 and the thin film structure TS. For example, the lower insulating layer 105 may be a silicon oxide layer formed through a thermal oxidation process. Alternatively, the lower insulating layer 105 may be a silicon oxide layer formed using a deposition technique. The lower insulating layer 105 may have a thickness smaller than that of the sacrifice layers 151 and the insulating layers 110 formed thereon.

Referring to FIGS. 3A and 4B, first channel holes 200a and second channel holes 200b may be formed to expose the substrate 100 through the thin film structure TS. From a plan viewpoint, the first channel holes 200a may be arranged along a first direction D1 parallel to the top surface of the substrate. The second channel holes 200b may be arranged along a first direction D1 parallel to an upper surface of the substrate. At this time, the first channel holes 200a and the second channel holes 200b may be spaced apart from each other in a second direction D2 intersecting the first direction D1. Further, the first channel holes 200a may be arranged in a zigzag shape along the first direction D1. The second channel holes 200b may be arranged in a zigzag shape along the first direction D1 (see FIG. 3A).

The formation of the first and second channel holes 200a and 200b may be performed by forming the first and the second channel holes 200a and 200b on the thin film structure TS by forming the first and second channel holes 200a and 200b on the thin film structure TS, 1 mask pattern (not shown), and etching the thin film structure (TS) using the first mask pattern as an etching mask. The first mask pattern may be formed of a material having etch selectivity with respect to the sacrifice films 151 and the insulating films 110. During the etching process, the top surface of the substrate 100 may be over-etched. Accordingly, the upper surface of the substrate 100 can be recessed. Also, the width of the lower portion of each of the first and second channel holes 200a and 200b may be narrower than the width of the upper portion of each of the first and second channel holes 200a and 200b by the etching process. Thereafter, the first mask pattern may be removed.

3A and 3C, vertical insulators 140 and vertical semiconductor patterns 130a and 130b, which cover the inner walls of the first and second channel holes 200a and 200b and expose the substrate 100, 130b may be formed. The vertical semiconductor patterns 130a and 130b may include first vertical semiconductor patterns 130a and second vertical semiconductor patterns 130b. A vertical insulating film (not shown) and a vertical semiconductor film (not shown) for covering the inner walls of the first and second channel holes 200a and 200b are formed on the resultant of the first and second channel holes 200a and 200b, Not shown) may be formed in order. The vertical insulating film and the vertical semiconductor film may fill a part of the first and second channel holes 200a and 200b. The sum of the thicknesses of the vertical insulating film and the vertical semiconductor film may be less than half the width of each of the first and second channel holes 200a and 200b. That is, the first and second channel holes 200a and 200b may not be completely filled with the vertical insulating film and the vertical semiconductor film. Further, the vertical insulating film may cover the upper surface of the substrate 100 exposed by the first and second channel holes 200a and 200b. The vertical insulating film may be formed of a plurality of thin films, for example, plasma enhanced chemical vapor deposition (CVD), physical CVD, or atomic layer deposition (ALD) Can be deposited.

The vertical insulating film may include a charge storage film (not shown) used as a memory element of the flash memory device. For example, the charge storage film may be an insulating film including a trap insulating film or conductive nano dots. Alternatively, the vertical insulating layer may comprise a thin film (not shown) for a thin film or variable resistance memory for a phase change memory.

According to one embodiment, although not shown, the vertical insulating film may include a blocking insulating film, a charge storage film, and a tunnel insulating film which are sequentially stacked. The blocking insulating layer may cover the sidewalls of the sacrificial layers 151 and the insulating layers 110 exposed by the first and second channel holes 200a and 200b and the upper surface of the substrate 100 . The blocking insulating layer may be formed of a silicon oxide layer, for example. The charge storage layer may include a trap insulating layer, or an insulating layer containing conductive nano dots. For example, the charge storage layer may comprise at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a laminated trap layer. have. The tunnel insulating film may be one of materials having a band gap larger than that of the charge storage film. For example, the tunnel insulating film may be a silicon oxide film.

The vertical semiconductor film may be formed on the vertical insulating film. According to one embodiment, the vertical semiconductor film is a semiconductor material (e.g., a polysilicon film, a monocrystalline silicon film, or an amorphous silicon film) formed using one of atomic layer deposition (ALD) or chemical vapor deposition Membrane).

After the vertical insulating film and the vertical semiconductor film are sequentially formed, the vertical semiconductor film and the vertical insulating film may be anisotropically etched to expose the substrate 100. Accordingly, the vertical insulators 140 and the first vertical semiconductor patterns 130a may be formed on the inner walls of the first channel holes 200a. Vertical insulators 140 and second vertical semiconductor patterns 130b may be formed on the inner walls of the second channel holes 200b. The vertical insulators 140 and the first and second vertical semiconductor patterns 130a and 130b may be formed into a cylindrical shape having open ends. The top surface of the substrate 100 may be recessed as a result of an over-etching during the anisotropic etching of the vertical semiconductor film and the vertical insulating film.

In addition, as a result of the anisotropic etching of the vertical semiconductor film and the vertical insulating film, the upper surface of the thin film structure TS may be exposed. The vertical insulators 140 and the first and second vertical semiconductor patterns 130a and 130b may be locally formed in the first and second channel holes 200a and 200b.

Referring to FIGS. 3A and 4D, connected semiconductor patterns 135a and 135b are formed on the resultant structure in which the vertical insulators 140 and the first and second vertical semiconductor patterns 130a and 130b are formed . The connecting semiconductor patterns 135a and 135b may include first connecting semiconductor patterns 135a and second connecting semiconductor patterns 135b. Specifically, a connecting semiconductor film (not shown) and a buried insulating film (not shown) may be sequentially formed on the resultant structure described with reference to FIG. 4C. The connection semiconductor film may be conformally formed in the first and second channel holes 200a and 200b to a thickness that does not completely fill the first and second channel holes 200a and 200b. The connecting semiconductor film may be a semiconductor material (e.g., a polycrystalline silicon film, a monocrystalline silicon film, or an amorphous silicon film) formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. The buried insulating film may be formed to completely fill the inside of the first and second channel holes 200a and 200b. The buried insulating film may be one of insulating materials and a silicon oxide film formed using an SOG (SOG) technique. The connecting semiconductor film and the buried insulating film are then planarized to expose the upper surface of the thin film structure TS so that the first connecting semiconductor patterns 135a and the vertical insulating patterns 150 may be locally formed. In addition, the second connecting semiconductor patterns 135b and the vertical insulating patterns 150 may be locally formed in the second channel holes 200b.

The first and second connecting semiconductor patterns 135a and 135b are formed in a pipe-shaped state in which one end is closed in the first and second channel holes 200a and 200b, A hollow cylindrical shape, or a cup shape. However, according to another example, the first and second connecting semiconductor patterns 135a and 135b may be formed in a pillar shape filling the first and second channel holes 200a and 200b. The vertical insulating patterns 150 may be formed to fill the inside of the first and second channel holes 200a and 200b formed with the first and second connecting semiconductor patterns 135a and 135b. The first vertical semiconductor patterns 130a and the first connecting semiconductor patterns 135a may form the first channel structures CS1 and the second vertical semiconductor patterns 130b and the second connection The semiconductor patterns 135b may form the second channel structures CS2.

Referring to FIGS. 3A and 4E, the through holes 210 may be formed through the thin film structure TS to expose the substrate 100. From a plan viewpoint, the through-holes 210 may be arranged along the first direction D1 to form a row. At this time, the through-holes 210 of the other columns may be spaced apart from the through-holes 210 of the one column with the first channel structures CS1 or the second channel structures CS2 therebetween (See FIG. 3A).

The formation of the through-holes 210 may include forming a second mask pattern (not shown) having openings on the thin film structure TS to define an area where the through-holes 210 are to be formed, And etching the thin film structure (TS) using the second mask pattern as an etching mask. The second mask pattern may be formed of a material having etch selectivity with respect to the sacrifice films 151 and the insulating films 110. During the etching process, the top surface of the substrate 100 may be over-etched. Accordingly, the upper surface of the substrate 100 can be recessed.

The through holes 210 may be formed to expose the sacrificial layers 151 and the sidewalls of the insulating layers 110. From the plan viewpoint, the through-holes 210 may also have different widths depending on the vertical height from the substrate 100 by the anisotropic etching process.

Referring to FIGS. 3A, 4F and 5A, recessed regions 215 may be formed by selectively removing the sacrificial layers 151 exposed by the through holes 210. For example, the sacrificial layers 151 may be removed through the etchant introduced through the through holes 210. The recess regions 215 may be a gap region extending horizontally from the through holes 210 of the trenches 220 and may be formed to expose the sidewalls of the vertical insulators 140. [ have. In addition, the recessed regions 215 may be formed to expose top surfaces and bottom surfaces of the insulating films 110.

Further, gate dielectric layers 180 may be formed on the recessed regions 215. The gate dielectric layers 180 may be formed to cover the inner walls of the recessed regions 215. On the gate dielectric layers 180, gate films 153 (e.g., a metal film) filling the remaining portions of the recessed regions 215 may be formed. Specifically, the gate dielectric layers 180 and the gate dielectric layers 180 may be formed by depositing the deposition gases through the through holes 210.

The gate dielectric layers 180 may comprise an information storage layer. The gate dielectric layers 180 may be formed of one thin film or a plurality of thin films, similar to the vertical insulators 140. According to one example, the gate dielectric layers 180 may comprise a blocking dielectric layer of a charge trapped non-volatile memory device.

3A, 4G and 5B, the gate films 153 exposed by the through holes 210 are partially etched selectively to form the first gate electrodes 155a and the second gate electrodes 155b may be formed. Specifically, the gate films 153 may be isotropically etched through the through holes 210 through the etchant introduced through the through holes 210. Thus, the gate films 153 can be separated into the first and second gate electrodes 155a and 155b, and the first and second gate electrodes 155a and 155b can be separated from the second direction D2. ≪ / RTI > Further, the first gate electrodes 155a may be formed with first recessed sidewalls 155as adjacent to the through-holes 210, and the second gate electrodes 155b may have through-holes 210 And adjacent second sidewall sidewalls 155bs may be formed. The first protruding sidewalls 155ap may be formed between the adjacent through-holes 210 in the first gate electrodes 155a and the second protruding sidewalls 155ap may be formed in the second gate electrodes 155b. Second protruding sidewalls 155bp may be formed between the through-holes 210.

After the first and second gate electrodes 155a and 155b are formed, the common source regions 120 may be formed in the substrate 100. FIG. The common source regions 120 may be formed through the ion implantation process and may be formed in the substrate 100 exposed by the through holes 210. The common source regions 120 may form a PN junction with the substrate 100. According to one example of the present invention for a flash memory device, each of the common source regions 120 may be connected to each other and be in an equipotential state. According to another example, each of the common source regions 120 may be electrically isolated so as to have different potentials. According to another example, the common source regions 120 may constitute a plurality of independent source groups including a plurality of different common source regions 120, and each of the source groups may be different And can be electrically separated to have a potential.

Referring again to FIGS. 3A to 3C, spacer films 175 may be formed on the common source regions 120 to fill a portion of the through holes 210. The spacer films 175 may cover the sidewalls of the first and second gate electrodes 155a and 155b and the upper surfaces and the bottom surfaces of the exposed insulating films 110. [ The spacer films 175 may include a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, or a silicon nitride film.

Contacts 170 connecting the common source regions 120 may be formed in the through holes 210 while penetrating the spacer films 175. The contacts 170 may be spaced apart from each other in the second direction D2 while being arranged along the first direction D1. Through the spacer films 175, the first and second gate electrodes 155a and 155b and the contacts 170 can be electrically isolated from each other.

In addition, conductive pads 160 connected to the first channel structures CS1 and the second channel structures CS2 may be formed. The conductive pads 160 may be formed by recessing the upper region of the first and second channel structures CS1 and CS2 and then filling the recessed region with a conductive material. In addition, the conductive pads 160 may be formed by doping impurities having a conductivity type different from that of the first and second channel structures CS1 and CS2 located under the conductive pads 160. [

Subsequently, common source lines (CSL) connected to the contacts 170 may be formed. The common source lines CSL may extend in the first direction D1 and may be spaced apart from each other along the second direction D2. The common source lines CSL may be conductive patterns (e.g., metal lines).

A first interlayer insulating film 190 covering the common source lines CSL may be formed. Bit line plugs (BPLG) that electrically connect to the conductive pads 160 through the first interlayer insulating layer 190 may be formed. On the first interlayer insulating layer 190, bit lines BL connected to the bit line plugs BPLG may be formed. The bit lines BL may extend in the second direction D2 and may be spaced apart from each other along the first direction D1. The bit lines BL may intersect the common source lines CSL while being vertically spaced from the common source lines CSL.

Example  2

6A is a plan view showing the cell region CR of the three-dimensional semiconductor memory device according to another embodiment of the present invention, which is an enlarged view of the region M in FIG. 6B is a cross-sectional view taken along line I-I 'of FIG. 6A, and FIG. 6C is a cross-sectional view taken along line II-II' of FIG. 6A. In this example, the detailed description of the technical features overlapping with those described with reference to Figs. 3A to 3C will be omitted, and the differences will be described in detail. The same reference numerals as those of the semiconductor device according to the embodiment of the present invention described above can be provided with the same reference numerals.

Referring to FIGS. 6A to 6C, the substrate 100 may include a pocket-well impurity layer 100p of the first conductivity type. The substrate 100 may include an impurity-doped well pick-up region 125 in the pocket-well impurity layer 100p. In this embodiment, the well pickup region 125 is not only disposed in the pocket-well impurity layer 100p around the channel structures CS1 and CS2 (see FIG. 2) May also be disposed in the pocket-well impurity layer (100p) between the channel structures (CS1, CS2).

A well contact 172 connecting to the well pickup region 125 between the first and second channel structures CS1 and CS2 may be disposed in the through hole 210. [ The well contact 172 may pass through the insulating films 110 and may be disposed between the first and second gate electrode structures ES1 and ES2. In this embodiment, only one of the well contacts 172 is illustrated, but in another example, the plurality of the well contacts 172 may be provided.

A well conductive line PCL crossing the stacked structures SS is formed on the stacked structures SS including the first and second gate electrode structures ES1 and ES2 and the insulating films 110. [ Can be arranged. The well conductive line PCL may be disposed on the first interlayer insulating film 190. The well conductive lines PCL may extend in the first direction D1 and may be provided between the common source lines CSL. The well conductive line PCL may be a conductive pattern (e.g., a metal line) vertically spaced from the top surface of the substrate 100. The well conductive line PCL may be spaced apart from the common source lines CSL through the first interlayer insulating layer 190. [

The well conductive line PCL may be formed on the well contact 172 and electrically connected to the well contact 172. A well contact plug (PCT) may be disposed between the well conductive line PCL and the well contact 172 to electrically connect the well conductive line PCL and the well contact 172 via the well contact plug PCT, 172 may be electrically connected to each other. A voltage may be applied to the well pickup region 125 connected to the well contact 172 via the well conductive line PCL spaced apart from the substrate 100. [

A second interlayer insulating film 195 covering the well conductive line PCL may be disposed. The first bit line plug BPLG1 may be electrically connected to the conductive pad 160 through the first interlayer insulating film 190 and the second bit line plug BPLG2 may be electrically connected to the second interlayer insulating film 195, And may be connected to the first bit line plug BPLG1.

The bit lines BL across the stacked structures SS may be disposed on the second interlayer insulating film 195. [ The bit lines BL may extend in the second direction D2 and may be spaced apart from each other along the first direction D1. The bit lines BL may intersect the common source lines CSL while being vertically spaced from the common source lines CSL and the well conductive lines PCL. The bit lines BL may be connected to the plurality of conductive pads 160 through a plurality of the first and second bit line plugs BPLG1 and BPLG2.

The three-dimensional semiconductor memory device according to the embodiment of the present invention is characterized in that the well pickup region 125 is also located between the first and second channel structures CS1 and CS2, -Well impurity layer 100p can be placed in a uniform equipotential state. In addition, by using the well conductive line PCL and the well contact 172, a voltage can be effectively applied to the well pick-up region 125.

Example  3

FIG. 7A is a plan view showing the cell region CR of the three-dimensional semiconductor memory device according to still another embodiment of the present invention, which is an enlarged view of the M region of FIG. 2. FIG. 7B is a cross-sectional view taken along the line I-I 'in FIG. 7A. In this example, the detailed description of the technical features overlapping with those described with reference to Figs. 3A to 3C will be omitted, and the differences will be described in detail. The same reference numerals as those of the semiconductor device according to the embodiment of the present invention described above can be provided with the same reference numerals.

7A and 7B, a first stacked structure SS1 in which first gate electrodes 155a and first insulating films 110a are alternately and repeatedly stacked is disposed on a substrate 100 . On the substrate 100, a second stacked structure SS2 in which second gate electrodes 155b and second insulating films 110b are alternately and repeatedly stacked may be disposed. The planar shape of the first insulating films 110a may correspond to the planar shape of the first gate electrodes 155a, and the second insulating films 110b may be formed in the same plane shape as the first gate electrodes 155a, May correspond to the planar shape of the second gate electrodes 155b. Although the first and second stacked structures SS1 and SS2 as well as other stacked structures may be disposed apart from each other, the first and second stacked structures SS1 and SS2 may be alternatively disposed in the present embodiment. For example.

The first and second lamination structures SS1 and SS2 may have a line shape extending in the first direction D1 from a plan viewpoint. The shapes of the first and second stacked structures SS1 and SS2 will be described later in more detail. Common source regions 120 may be disposed on both sides of the first and second stacked structures SS1 and SS2.

The first channel structures CS1 may pass through the first laminate structure SS1 and the second channel structures CS2 may penetrate through the second laminate structure SS2. The first and second stacked structures SS1 and SS2 are spaced apart from each other along the second direction D2 so that the first and second channel structures CS1 and CS2 are also aligned in the second direction D2, As shown in FIG. The first channel structures CS1 may be arranged in a zigzag manner along the first direction D1. The second channel structures CS2 may be arranged in a zigzag manner along the first direction D1.

Trenches 220 may be formed between the first and second stacked structures SS1 and SS2. The trenches 220 may extend in a zigzag fashion in the first direction D1 to separate the first and second stacked structures SS1 and SS2 from each other. In the embodiment described with reference to FIGS. 3A to 3C, the insulating film 110 is integrally formed, and the first gate electrode 155a and the second gate electrode 155b on the insulating film 110 are separated from each other I could. However, in the case of this embodiment, not only the gate electrode but also the insulating film can be separated into the first insulating film 110a and the second insulating film 110b by the trenches 220. [

Contact lines 174 connecting to the common source regions 120 may be disposed in the trenches 220. At least one of the contact lines 174 may pass between the first and second stacked structures SS1 and SS2. In other words, the first laminated structure SS1 and the second laminated structure SS2 may be spaced apart from each other in the second direction D2 with the contact line 174 therebetween. The contact lines 174 may extend in a zigzag fashion along the first direction D1 and may be spaced apart from each other in the second direction D2. The contact lines 174 may be conductive patterns (e.g., metal lines) that connect to the top surface of the substrate 100.

Spacer films 175 may be interposed between the contact lines 174 and the first and second stacked structures SS1 and SS2. Through the spacer films 175, the first and second gate electrodes 155a and 155b and the contact lines 174 can be electrically isolated from each other. The spacer films 175 may include a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, or a silicon nitride film.

Common source lines (CSL) may be disposed on the contact lines (174). The common source lines CSL may be electrically connected to the contact lines 174 while overlapping the contact lines 174 vertically. A voltage may be applied to the common source regions 120 connected to the contact lines 174 through the common source lines CSL disposed apart from the substrate 100. [

The first and second laminated structures SS1 and SS2 according to the present embodiment will be described in more detail.

Referring again to FIG. 7A, the first and second lamination structures SS1 and SS2 may be in the form of a line extending in a zigzag manner in the first direction D1. The first gate electrodes 155a of the first laminated structure SS1 may include first depressed sidewalls 155as and first protruding sidewalls 155ap. The second gate electrodes 155b of the second stacked structure SS2 may include second recessed sidewalls 155bs and second projected sidewalls 155bp. The first and second insulating films 110a and 110b may have a shape corresponding to the first and second gate electrodes 155a and 155b, respectively, as described above.

From a plan viewpoint, the first depressed sidewalls 155as and the first depressed sidewalls 155ap may correspond to the zigzagged profile of the first channel structures CS1. For example, a first protruding sidewall 155ap may be adjacent to a first channel structure CS1 protruding further in the second direction D2 from the center of the first laminated structure SS1. Another first protruding sidewall 155ap may be adjacent to another first channel structure CS1 further projecting from the center of the first laminated structure SS1 in the second direction D2. A first depressed sidewall 155as may be disposed between the first protruding sidewall 155ap and the first protruding sidewall 155ap. The second recessed sidewalls 155bs and the second protruded sidewalls 155bp may be the same as those described in the first recessed sidewalls 155as and the second protruded sidewalls 155bp.

The three-dimensional semiconductor memory device according to the present embodiment can be improved in structural stability. This is because the first and second lamination structures SS1 and SS2 are in the form of a line extending in a staggered manner in the first direction D1 so that the first and second lamination structures The surface area of the sidewalls of the first and second electrodes SS1 and SS2 may be wider. That is, the pressure due to the stacking of the gate electrodes and the insulating films can be effectively dispersed. Therefore, when the first and second stacked structures SS1 and SS2 are stacked in a high layer, the problem of collapsing the first and second stacked structures SS1 and SS2 can be significantly improved.

Further, since the common source lines CSL may be formed of conductive patterns (for example, metal lines) spaced apart from the substrate 100, the contact lines 174 and the common source lines Such as seam inside the CSL. Thus, even if the lengths of the contact lines 174 and the common source lines CSL are increased, the problem of resistance increase can be solved.

8A to 8C are cross-sectional views illustrating a method for fabricating a three-dimensional semiconductor memory device according to another embodiment of the present invention. Figs. 8A to 8C are cross-sectional views corresponding to line I-I 'in Fig. 7A. In the manufacturing method of the present embodiment, the detailed description of the technical features overlapping with the manufacturing method of the embodiment described with reference to FIGS. 4A to 4G, 5A and 5B will be omitted, and the differences will be described in detail.

Referring to FIGS. 7A and 8A, on the result of FIG. 4D, trenches 220 may be formed to pattern the thin film structure TS to expose the substrate 100. The trenches 220 may be formed on both sides of the rows in which the first and second channel holes 200a and 200b are arranged in the first direction D1.

The formation of the trenches 220 may include forming a second mask pattern (not shown) defining a planar location on the thin film structure TS where the trenches 220 are to be formed, And etching the thin film structure (TS) using the mask pattern as an etching mask. The trenches 220 may be formed to expose the sidewalls of the sacrificial films 151 and the insulating films 110. [ From a plan viewpoint, the trenches 220 may be in the form of a line extending in a staggered manner in the first direction D1, and in a vertical depth, the trenches 220 may expose the top surface of the substrate 100 As shown in FIG. In addition, the trenches 220 may have different widths depending on the vertical height from the substrate 100 by the anisotropic etching process.

By using the second mask patterns, pattern shapes of the first and second stacked structures SS1 and SS2 can be formed. The pattern shapes of the first and second lamination structures SS1 and SS2 are as described above with reference to FIGS. 7A and 7B.

Referring to FIG. 8B, recessed regions 215 may be formed by selectively removing the sacrificial layers 151 exposed by the trenches 220. The recessed regions 215 may be a gap region extending horizontally from the trenches 220 and may be formed to expose the sidewalls of the vertical insulators 140.

Further, gate dielectric layers 180 may be formed on the recessed regions 215. The gate dielectric layers 180 may be formed to cover the inner walls of the recessed regions. First gate electrodes 155a and second gate electrodes 155b may be formed on the gate dielectric layers 180 to fill the remaining portion of the recessed regions 215. [ The formation of the gate dielectric layers 180 and the first and second gate electrodes 155a and 155b may include forming a dielectric layer (not shown) and a gate layer (not shown) that sequentially fill the recessed regions 215, (E. G., A metal film), and then removing the dielectric film and the gate film within the trenches 220. In some embodiments,

In this embodiment, the thin film structure TS may be etched to form a zigzag pattern. Thereby, the horizontal film and the gate film can be filled in the recessed regions 215 without forming seams or voids. Therefore, problems such as pattern deformation of the first and second gate electrodes 155a and 155b can be significantly improved.

The first gate electrodes 155a and the first insulating films 110a sequentially stacked may be defined as a first laminated structure SS1 and the second gate electrodes 155b and the second insulating films The second laminate structure SS1 may be defined as a second laminate structure SS2.

Referring to FIGS. 7A and 8C, common source regions 120 may be formed in the substrate 100 after the first and second gate electrodes 155a and 155b are formed.

Referring again to FIGS. 7A and 7B, spacer films 175 filling a portion of the trenches 220 may be formed on the common source regions 120.

In the trenches 220, contact lines 174 connecting to the common source regions 120 through the spacer films 175 may be formed. The contact lines 174 may extend along the first direction D1 and may be spaced apart from each other in the second direction D2. Through the spacer films 175, the first and second gate electrodes 155a and 155b and the contact lines 174 can be electrically isolated from each other.

In addition, conductive pads 160 connected to the first channel structures CS1 and the second channel structures CS2 may be formed. Subsequently, common source lines (CSL) connected to the contact lines 174 may be formed. A first interlayer insulating film 190 covering the common source lines CSL may be formed. Bit line plugs (BPLG) that electrically connect to the conductive pads 160 through the first interlayer insulating layer 190 may be formed. On the first interlayer insulating layer 190, bit lines BL connected to the bit line plugs BPLG may be formed.

9 is a schematic block diagram illustrating an example of a memory system including a three-dimensional semiconductor memory device according to embodiments of the present invention.

9, memory system 1100 may be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, A memory card, or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes an input / output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions executed by the controller. The input / output device 1120 may receive data or signals from outside the system 1100, or may output data or signals outside the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

The memory 1130 includes a three-dimensional semiconductor memory device according to embodiments of the present invention. Memory 1130 may also include other types of memory, volatile memory that may be accessed at any time, and various other types of memory.

The interface 1140 serves to transmit data to and receive data from the communication network.

Further, the three-dimensional semiconductor memory device or memory system according to the present invention can be mounted in various types of packages. For example, the three-dimensional semiconductor memory device or the memory system according to the present invention can be used as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package A wafer-level stacked package (WSP) or the like.

10 is a schematic block diagram showing an example of a memory card having a three-dimensional semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 10, a memory card 1200 for supporting a high capacity data storage capability mounts a flash memory device 1210. The flash memory device 1210 includes a three-dimensional semiconductor memory device according to embodiments of the present invention described above. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 has a data exchange protocol of a host connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs all control operations for data exchange of the memory controller 1220. Although it is not shown in the drawing, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned.

11 is a schematic block diagram showing an example of an information processing system for mounting a three-dimensional semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 11, a flash memory device 1210 is mounted in an information processing system such as a mobile device or a desktop computer. The flash memory device 1210 includes a three-dimensional semiconductor memory device according to embodiments of the present invention described above. An information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, a user interface 1350, . The flash memory system 1310 will be configured substantially the same as the memory system or flash memory system mentioned above. The flash memory system 1310 stores data processed by the central processing unit 1330 or externally input data. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention can be provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. It is clear to those who have learned.

Claims (10)

An insulating film provided on the substrate in one body;
A first gate electrode and a second gate electrode disposed on the insulating film and extending in a first direction parallel to an upper surface of the substrate;
A first channel structure connected to the substrate through the insulating film and the first gate electrode;
A second channel structure connected to the substrate through the insulating film and the second gate electrode; And
And a contact disposed between the first gate electrode and the second gate electrode and connected to a common source region of the first conductivity type in the substrate,
Wherein the first gate electrode and the second gate electrode are spaced apart from each other in a second direction that is parallel to the upper surface of the substrate and crosses the first direction at a vertically same level.
The method according to claim 1,
The insulating film, the first gate electrode, and the second gate electrode form a unit structure,
Wherein the unit structures are provided in a plurality, and are repeatedly stacked on the substrate,
The first gate electrodes alternately stacked with the insulating films define a first gate electrode structure,
The second gate electrodes alternately stacked with the insulating films define a second gate electrode structure,
Wherein the first gate electrode structure and the second gate electrode structure are spaced apart from each other in the second direction with the contact therebetween.
The method according to claim 1,
Wherein each of the first gate electrode and the second gate electrode includes a depressed sidewall,
The depressed sidewalls adjacent the contact,
From a plan viewpoint, the contact is surrounded by the depression sidewalls.
The method of claim 3,
The distance between the inner wall of the insulating film adjacent to the contact and the contact,
And the distance between each of the depressed sidewalls and the contact is shorter than the distance between each of the depressed sidewalls and the contact.
The method according to claim 1,
Wherein the insulating film supports both the first and second gate electrodes,
Wherein the insulating film includes a through hole in a region between the first and second gate electrodes,
And the contact is provided in the through hole.
The method according to claim 1,
Said contacts being provided in a plurality of locations and being spaced apart from each other along said first direction,
Wherein each of the first gate electrode and the second gate electrode comprises a projecting sidewall,
Wherein the projecting sidewalls are located between the contacts adjacent to each other.
The method according to claim 6,
And a common source line extending in the first direction,
Wherein the common source line is disposed on the contacts and is electrically connected to the contacts.
The method according to claim 1,
Said contacts being provided in a plurality of locations and being spaced apart from each other along said first direction,
And at least one of the contacts is connected to a well pickup region of a second conductivity type in the substrate.
The method according to claim 1,
Further comprising gate dielectric layers covering the top and bottom surfaces of each of the first and second gate electrodes and interposed between the first and second gate electrodes and the first and second channel structures,
And the gate dielectric layers extend to cover the upper surface and the inner wall of the insulating film.
The method according to claim 1,
Wherein the first channel structure is provided in a plurality of locations and is spaced apart from each other along the first direction,
Wherein the second channel structures are provided in a plurality and are arranged apart from each other along the first direction,
Wherein the plurality of contacts are provided so as to be spaced apart from each other along the first direction between the first channel structures and the second channel structures,
Wherein the insulating film surrounds the sidewalls of the first channel structures, the sidewalls of the second channel structures, and the sidewalls of the contacts.

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