KR101818675B1 - Semiconductor memory device and method of forming the same - Google Patents

Abstract

Forming a stacked structure including sacrificial films and a selective gate film on a substrate, forming a penetration region through the stacked structure, forming a selective gate insulating film on the sidewall of the selective gate film exposed by the penetration region Forming an active pattern in the penetration area, removing the sacrificial layers to expose a part of the side wall of the active pattern, and forming an information storage layer on a part of the side wall of the exposed active pattern.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor memory device and a method of forming the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor memory device and a manufacturing method thereof.

As the electronics industry develops, the degree of integration of semiconductor memory devices is increasing. The degree of integration of semiconductor memory devices is an important factor in determining the price of a product. That is, as the degree of integration increases, the product price of the semiconductor memory device may decrease. As a result, there is a growing demand for improvement in the degree of integration of semiconductor memory devices. Generally, the degree of integration of the semiconductor memory device is largely influenced by the level of the fine pattern forming technique, since it is mainly determined by the planar area occupied by the unit memory cell. However, miniaturization of patterns is becoming more and more limited due to expensive equipment and / or difficulties of the semiconductor manufacturing process.

In order to overcome these limitations, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass-produce a three-dimensional semiconductor memory device, a process technology capable of reducing the manufacturing cost per bit of the two-dimensional semiconductor memory device and realizing a reliable product characteristic is required.

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device having improved electrical characteristics and a method of manufacturing the same.

It is another object of the present invention to provide a semiconductor device optimized for high integration and a manufacturing method thereof.

The present invention also provides a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device, comprising: forming a laminated structure including sacrificial films and a selective gate film on a substrate; forming a penetration region through the laminated structure; forming a selective gate insulating film on the sidewall of the selective gate film exposed by the penetration region Forming an active pattern in the penetration area; removing the sacrificial layers to expose a portion of the sidewalls of the active pattern; and forming an information storage layer on a portion of the sidewalls of the exposed active pattern ≪ / RTI >

In one embodiment, forming the stacked structure may further comprise forming insulating films between the sacrificial films and between the sacrificial films and the select gate film.

In one embodiment, the select gate film may be formed of polysilicon.

In one embodiment, the formation of the select gate insulating film may be performed by a thermal oxidation process.

In one embodiment, forming the information storage layer may include forming a tunnel insulating layer, a charge storage layer, and a blocking layer sequentially on a portion of the sidewall of the exposed active pattern.

In one embodiment, after forming the information storage layer, forming the cell gate layers filling the space formed by removing the sacrificial layers may be performed.

In one embodiment, forming the select gate film may include forming a lower select gate film between the sacrificial films and the substrate, and forming an upper select gate film on the sacrificial films.

In one embodiment, the selection gate insulating film is formed before formation of the active pattern, and the information storage film is formed after formation of the active pattern.

In one embodiment, the method may further include forming a buffer insulating layer between the substrate and the stacked structure.

In one embodiment, forming the penetrating region includes exposing the buffer insulating layer. After forming the select gate insulating layer, the buffer insulating layer exposed by the penetrating region is removed to expose the substrate. Quot;

In one embodiment, forming the penetrating region includes exposing the substrate through the buffer insulating layer, forming the select gate insulating layer by a thermal oxidation process, And removing the thermal oxide film.

In one embodiment, the removal of the substrate thermally oxidized film may be performed using a plasma having a strong linearity.

In one embodiment, the method may further include the step of recessing the sidewall of the selective gate film exposed by the through region before forming the select gate insulating film.

A semiconductor device is provided to achieve the above-described object. The device comprising: an active pattern extending upwardly from the substrate; cell gates and select gates provided on the sidewalls of the active pattern; horizontally extending between the cell gates and the active pattern, And a select gate insulating film between the select gate and the active pattern, and the cell gates and the select gate may be different materials.

In one embodiment, the cell gates include at least one selected from a metal, a metal silicide, and a conductive metal nitride, and the select gate may comprise polysilicon.

In one embodiment, the select gate insulating layer is a silicon oxide layer, and the information storage layer may include a material having a bandgap smaller than that of the silicon oxide layer.

In one embodiment, the information storage layer includes a tunnel insulating layer, a charge storage layer, and a blocking layer that are sequentially stacked on the active pattern, and the charge storage layer includes a material having a band gap smaller than that of the tunnel insulating layer and the blocking layer can do.

In one embodiment, the select gate insulating layer may be locally disposed between the select gate and the sidewalls of the active pattern.

In one embodiment, the device further comprises an insulating film between the cell gates and between the cell gates and the select gate, wherein the select gate is in direct contact with the insulating film, And may be spaced apart from the insulating film.

In one embodiment, the active pattern may further include an extension protruding from the side walls of the active pattern toward the selection gate films.

The gate insulating film of the select gate and the information storage film of the cell gate can be formed in different structures. Accordingly, it is possible to prevent the threshold voltage of the selection transistor from becoming unstable by the hot carrier. The material of the select gate and the cell gate can be formed differently. Further, the gate length of the select gate can be more easily adjusted than the case of forming the select gate and the cell gate together.

1 is a circuit diagram of a semiconductor device according to embodiments of the present invention.
2 is a perspective view of a semiconductor device according to a first embodiment of the present invention.
3 is an enlarged view of region A in Fig.
4 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
13 to 16 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a modification of the first embodiment.
17 to 19 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to another modification of the first embodiment.
20 to 21 are sectional views for explaining a method of manufacturing a semiconductor device according to still another modification of the first embodiment.
22 is a perspective view of a semiconductor device according to a second embodiment of the present invention.
23 to 30 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
31 is a schematic block diagram illustrating an example of a memory system including a semiconductor device formed in accordance with embodiments of the present invention.
32 is a schematic block diagram showing an example of a memory card having a semiconductor device according to the embodiments of the present invention.
33 is a schematic block diagram showing an example of an information processing system for mounting a semiconductor device according to the embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate, or a third film (Or layer) may be interposed. In the drawings, the sizes and thicknesses of the structures and the like are exaggerated for the sake of clarity. It should also be understood that although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., It should not be. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Like numbers refer to like elements throughout the specification.

1 is a circuit diagram of a semiconductor memory device according to embodiments of the present invention.

1, a three-dimensional semiconductor memory device according to embodiments includes a common source line CSL0-CSL2, a plurality of bit lines BL0, BL1, BL2, a common source line CSL0-CSL2, And a plurality of cell strings CSTR disposed between the plurality of cell strings BL0-BL2.

The bit lines BL0-BL2 are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines BL0-BL2. Cell strings CSTR may be connected in common to the common source lines CSL0-CSL2. That is, a plurality of cell strings CSTR may be disposed between a plurality of bit lines BL0-BL2 and one common source line CSL0, CSL1, or CSL2. According to one embodiment, a plurality of common source lines CSL0-CSL2 may be two-dimensionally arranged. Here, electrically the same voltage may be applied to the common source lines CSL0 to CSL2, or each common source line may be electrically controlled.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source lines CSL0 to CSL2, a string selection transistor SST connected to the bit lines BL0 to BL2, And a plurality of memory cell transistors MCT arranged between the first and second memory cells GST and SST. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source lines CSL0-CSL2 may be connected in common to the sources of the ground selection transistors GST. In addition, the ground selection lines GSL0-GSL2, the plurality of word lines WL0-WL3 and the plurality of string selection lines GSL0-GSL2, which are disposed between the common source lines CSL0-CSL2 and the bit lines BL- SSL0-SSL2 may be used as the gate electrodes of the ground selection transistor GST, the memory cell transistors MCT and the string selection transistors SST, respectively. In addition, each of the memory cell transistors MCT includes an information storage body.

Since one cell string CSTR is composed of a plurality of memory cell transistors MCT having different distances from the common source lines CSL0 to CSL2, the common source lines CSL0 to CSL2 and the bit lines BL0 -BL2) are arranged between the word lines WL0-WL3.

The gate electrodes of the plurality of memory cell transistors MCT, which are disposed at substantially the same distance from the common source lines CSL0 to CSL2, may be connected in common to one of the word lines WL0 to WL3 to be in an equipotential state have. Alternatively, although the gate electrodes of the memory cell transistors MCT are disposed at substantially the same distance from the common source lines CSL0-CSL2, the gate electrodes arranged in different rows or columns can be independently controlled.

2 and 3, a semiconductor device according to a first embodiment of the present invention is described. FIG. 2 is a perspective view of a semiconductor device according to a first embodiment of the present invention, and FIG. 3 is an enlarged view of a portion A in FIG.

Referring to Figures 2 and 3, a substrate 100 is provided. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may be of a structure doped with a first type dopant. The plurality of gate films on the substrate 100 and the insulating films 121 to 126: 120 may be provided in the spaced spaces between the plurality of gate films. The insulating films 120 may be an oxide film. The plurality of gate films may include select gate films and cell gate films 161 to 164 (160). The select gate films may include a lower select gate film 111 provided under the cell gate films 160 and an upper select gate film 112 provided over the cell gate films 160. The select gate films 111 and 112 may be thicker than the cell gate films 160. The top and / or bottom surfaces of the select gate films 111 and 112 may be in direct contact with the insulating films 120. A buffer insulating layer 105 may be provided between the substrate 100 and the lower selection gate layer 111. [ The buffer insulating layer 105 may be a silicon oxide layer.

The gate films and the insulating films 120 may extend in a direction parallel to the upper surface of the substrate 100, for example, in the y direction. Only four of the cell gate films 160 are shown, but this is for the sake of simplicity of description, and a greater number of cell gate films can be arranged. Although the selection gate films 111 and 112 are shown one by one, a plurality of the selection gate films 111 and 112 may be provided.

The cell gate films 160 and the select gate films 111 and 112 may be different materials. The cell gate films 160 may include at least one selected from a metal, a metal silicide, a conductive metal nitride, and a doped semiconductor material. The select gate films 111 and 112 may include polysilicon.

An active pattern 159 extending upward from the substrate 100 and passing through the gate films and the insulating films 120 may be provided. The cross-sectional area of the active pattern 159 at the intersection of the active pattern 159 and the select gate films 111 and 112 is set such that the active pattern 159 crosses the cell gate films 160 Sectional area of the active pattern 159 at the point. The active pattern 159 may be in the form of a macaroni including a channel pattern 151 and a buried layer 155 filling the interior of the channel pattern 151. The active pattern 159 may include an inner wall portion and a bottom portion. The top surface of the bottom portion may be adjacent to the substrate 100 above the top surface of the select gate film 141. 2, the active pattern 159 may be in a form that does not include the buried film 155. [ The channel pattern 151 may be a silicon film. The channel pattern 151 may have an intrinsic state. The active pattern 159 may be circular, elliptical or polygonal in plan view.

The active patterns 159 arranged in the first direction (x-axis direction) form one row and the active patterns 159 arranged in the second direction (y-axis direction) form one row. Hereinafter, throughout the present specification, the first direction may be referred to as an x-axis direction in Fig. 2, the second direction may be referred to as a y-axis direction, and the third direction may be referred to as a z-axis direction. A plurality of rows and a plurality of columns may be arranged on the substrate 100. An electrode separation pattern 175 may be disposed between a pair of adjacent columns. That is, the electrode separation pattern 175 may extend in the second direction. The electrode separation pattern 175 may include an insulating material. For example, the electrode separation pattern 175 may be a high density plasma oxide layer, a SOG layer (Spin On Glass layer), and / or a CVD oxide layer. A common source region 102 may be provided in the substrate 100 below the bottom of the electrode isolation pattern 175. The common source region 102 may be in the form of a line extending in the second direction (y-axis direction). The common source region 102 may be a region doped with a second type dopant. The second type may be a different conductivity type than the first type.

A select gate insulating layer 141 may be provided between the select gate layers 111 and 112 and the active pattern 159. The select gate insulating layer 141 may be a thermal oxide layer formed through a thermal oxidation process. For example, when the select gate films 111 and 112 are polysilicon, the select gate insulating film 141 may be a silicon oxide film obtained by thermally oxidizing the select gate films 111 and 112. The select gate insulating layer 141 may be in direct contact with the select gate layers 111 and 112 and the active pattern 159. The select gate insulating film 141 may be locally disposed between the select gate films 111 and 112 and the sidewalls of the active pattern 159.

An information storage layer 170 may be provided between the cell gate layers 160 and the active pattern 159. The information storage layer 170 may extend horizontally between the cell gate layers 160 and the active patterns 159 to cover the top and bottom surfaces of the cell gate layers 160. That is, the cell gate films 160 may be separated from the insulating films 120 by the information storage film 170. The information storage layer 170 may have a multi-layer structure including a material having a smaller bandgap than a silicon oxide layer. For example, the information storage layer 170 may include a charge storage layer 172 for storing a charge. The information storage layer 170 may include a tunnel insulating layer 171 between the charge storage layer 172 and the active pattern 159 and a tunnel insulating layer 171 between the charge storage layer 172 and the cell gate layers 160. [ And a blocking film 173 between the barrier film 173 and the barrier film 173. The charge storage layer 172 may include a material having a smaller band gap than the tunnel insulating layer 171 and the blocking layer 173. The charge storage layer 172 may be formed of a material having traps for storing charges. For example, the charge storage layer 172 may include at least one of a silicon nitride layer, a metal nitride layer, a metal oxynitride layer, a metal silicon oxide layer, a metal silicon oxynitride layer, and nano dots. The blocking layer 173 may include at least one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric layer. The high-dielectric-constant layer may include at least one selected from a metal oxide layer, a metal nitride layer, and a metal oxynitride layer. The high-k dielectric may include at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), lanthanum (La), cerium (Ce), and praseodymium (Pr). The dielectric constant of the blocking layer 173 may be greater than the dielectric constant of the tunnel insulating layer 171. Unlike the select gate insulating film 141, the tunnel insulating film 171 may not be a thermal oxide film.

A drain region D may be provided in the channel pattern 151 adjacent to the uppermost insulating film 126 on the upper select gate film 112. (BL) extending in parallel to the gate films (for example, x direction) and electrically connected to the drain region (D). The bit lines BL may include a conductive material.

4 to 12, a method of manufacturing a semiconductor device according to the first embodiment of the present invention is described.

Referring to Fig. 4, a substrate 100 is prepared. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a compound semiconductor substrate. The substrate 100 may be doped with a first type of dopant.

A stacked structure including sacrificial films (SC1 to SC4: SC) and select gate films 111 and 112 can be formed on the substrate 100. [ The formation of the stacked structure may further include forming insulating films between the sacrificial films (SC) and between the sacrificial films (SC) and the selective gate films (111, 112). The select gate films 111 and 112 may be formed of polysilicon. The sacrificial films SC may be formed of a material having an etch selectivity with respect to the select gate films 111 and 112 and the insulating films 120. For example, the insulating films 120 may be formed of an oxide, and the sacrificial films SC may be formed of a nitride and / or an oxynitride. It is preferable that the sacrificial films SC are formed of the same material. Likewise, the insulating films 120 may be formed of the same material.

The thickness of the select gate films 111 and 112 may be greater than the thickness of the sacrificial films SC. The sacrificial films SC may be formed to have the same thickness. The sacrificial films 121, 125 and 126 in contact with the selective gate films 111 and 112 may be thicker than the sacrificial films 122, 123 and 124 between the sacrificial films SC. The selective gate films 111 and 112, the sacrificial films SC and the insulating films 120 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

A buffer insulating layer 105 may be formed on the substrate 100 before forming the stacked structure. The lower selection gate layer 111 may be formed directly on the buffer insulation layer 105. The buffer insulating layer 105 may be formed of a dielectric material having an etch selectivity with respect to the sacrificial layers SC. For example, the buffer insulating layer 105 may be formed of an oxide, particularly, a thermal oxide.

5, the selective gate films 111 and 112, the insulating films 120 and the sacrificial films SC are continuously patterned to form a through region 131 exposing the buffer insulating film 105 . The through region 131 may be formed using an anisotropic etching process. When the through region 131 is formed, a part of the buffer insulating layer 105 may be etched together. The through region 131 may be in the form of a hole. The through regions 131 may be two-dimensionally arranged along a first direction and a second direction perpendicular to the first direction. The first direction and the second direction are parallel to the upper surface of the substrate 100. The through region 131 may be circular, elliptical or polygonal in plan view.

Referring to FIG. 6, a select gate insulating layer 141 may be formed on the sidewalls of the select gate layers 111 and 112 exposed by the penetration regions 131. The select gate insulating layer 141 may be formed by a thermal oxidation process.

Referring to FIG. 7, the buffer insulating layer 105 exposed by the penetration region 131 may be removed to expose the substrate 100. When the buffer insulating layer 105 is removed, a part of the substrate 100 may be recessed together. For example, the removal of the buffer insulating layer 105 may be performed by dry etching using a plasma having a strong directivity.

Referring to FIG. 8, a channel pattern 151 may be formed along the sidewalls and the bottom of the through region 131. The channel pattern 151 may be formed of silicon. The channel pattern 151 may be bent by the select gate insulating layer 141. That is, the portion of the channel pattern 151 provided on the sidewalls of the select gate films 111 and 112 may protrude from the portion of the channel pattern 151 provided on the sidewalls of the sacrificial films SC .

Referring to FIG. 9, a buried layer 155 filling the penetration area 131 may be formed on the channel pattern 151. The buried film 155 may be a nitride film or a nitride oxide film. The channel pattern 151 and the buried layer 155 may constitute an active pattern 159. The channel pattern 151 and the buried layer 155 may be formed through CVD or ALD.

 10, the channel pattern 151, the embedded film 155, the select gate films 111 and 112, the insulating films 120 and the sacrificial films SC are successively patterned to form trenches 135 ) Can be formed. The formation of the trenches 135 may be performed by an anisotropic etching process. The trench 135 may extend in the second direction. Thus, the select gate films 111 and 112, the insulating films 120, and the sacrificial films SC may be in the form of a line extending in parallel in the second direction. The substrate 100 may be exposed to the bottom of the trench 135. A portion of the substrate 100 may be panned together when the trench 135 is formed. Alternatively, the buffer insulating layer 105 may be exposed to the bottom of the trench 135. Hereinafter, the substrate 100 is exposed on the bottom surface of the trench 135 for convenience of explanation.

Referring to FIG. 11, the sacrificial layers SC exposed to the trenches 135 may be removed by a selective etching process to form the recessed regions 150. The selective etching process may be isotropic etching. The selective etching process may be performed by wet etching and / or isotropic dry etching. The etch rate of the sacrificial films SC by the selective etching process may be greater than the etch rates of the insulating films 120, the select gate films 111 and 112, and the channel patterns 151. Accordingly, after the selective etching process, the insulating films 120, the selective gate films 111 and 112, and the active patterns 159 may remain. The recessed regions 150 may expose portions of the sidewalls of the channel pattern 151 that are in contact with the sacrificial layers SC.

12 and FIGS. 2 to 3, the information storage layer 170 may be formed on the substrate 100 after the recessed regions 150 are formed. The information storage film 170 may be formed using a deposition technique (e.g., CVD or ALD) capable of providing excellent step coverage. Accordingly, the information storage layer 170 may be formed substantially conformally. The information storage layer 170 may be formed to have a substantially uniform thickness along the inner surfaces of the recessed regions 150. The information storage layer 170 may fill a portion of the recessed regions 150. A method of forming the information storage film 170 will be described. 3, forming the information storage layer 170 may include forming a tunnel insulating layer 171, a charge storage layer 172, and a blocking layer 173 in this order. The selection gate insulating layer 141 may be formed before the active pattern 159 is formed while the information storage layer 170 may be formed after the active pattern 159 is formed.

The tunnel insulating layer 171 may be formed to cover a part of the side wall of the channel pattern 151. The tunnel insulating layer 171 may be a single layer or a multilayer. For example, the tunnel insulating layer 171 may include at least one selected from a silicon oxynitride layer, a silicon nitride layer, a silicon oxide layer, and a metal oxide layer.

The charge storage layer 172 may be spaced apart from the active pattern 159 by the tunnel insulating layer 171. The charge storage layer 172 may include charge trap sites capable of storing charge. For example, the charge storage layer 172 may include at least one of a silicon nitride layer, a metal nitride layer, a metal oxynitride layer, a metal silicon oxide layer, a metal silicon oxynitride layer, and nano dots.

The blocking layer 173 may cover the charge storage layer 172. The blocking layer 173 may include at least one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric layer. The high-dielectric-constant layer may include at least one selected from a metal oxide layer, a metal nitride layer, and a metal oxynitride layer. The high-k dielectric may include at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), lanthanum (La), cerium (Ce), and praseodymium (Pr). The dielectric constant of the blocking layer 173 may be greater than the dielectric constant of the tunnel insulating layer 171.

Cell gate films 161 to 164: 160 filling the recessed regions 150 may be formed. After the information storage layer 170 is formed, a gate conductive layer (not shown) may be formed on the substrate 100. The gate conductive layer may fill the recessed regions 150. The gate conductive layer may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer chemical vapor deposition (ALD). The gate conductive film may include at least one selected from a metal, a metal silicide, a conductive metal nitride, and a doped semiconductor material. The planarization process may be performed to expose the uppermost insulating film 126. [

After the formation of the gate conductive layer, the gate conductive layer located outside the recessed regions 150 may be removed to form the cell gate layers 160 in the recessed regions 150. The formation of the cell gate films 160 may include removing the gate conductive film in the trenches 135 to leave the gate conductive film in the recessed regions 150. [ When the cell gate films 160 are formed, a part of the information storage layer 170 formed outside the recessed regions 150 may be removed together. Removal of a portion of the gate conductive layer and a portion of the information storage layer 170 may be performed by a wet and / or dry etch process. The cell gate films 161 to 164 located on different layers vertically from the upper surface of the substrate 100 by the etching process can be separated from each other.

A common source region 102 may be formed in the substrate 100 below the bottom surface of the trench 135. The common source region 102 may be in the form of a line extending in the second direction. The common source region 102 is a doped region of the second type dopant. The common source region 102 may be formed by implanting a second type of dopant ions into the substrate 100. At this time, the uppermost insulating film 126 may be used as an ion implantation mask.

A drain region D may be formed on the channel pattern 151. The drain region (D) may be doped with the second type of dopant. The lower surface of the drain region D may be higher than the upper surface of the upper select gate film 112. Alternatively, the lower surface of the drain region D may be a height close to the upper surface of the upper select gate film 112. The drain region D may be formed simultaneously with the common source region 102. Alternatively, the drain region D may be formed before or after the common source region 102 is formed.

An electrode separation pattern 175 filling the trench 135 may be formed. The electrode separation pattern 175 may be formed by forming an electrode separation pattern filling the trench 135 on the substrate 100 and performing a planarization process until the uppermost insulation layer 126 is exposed ≪ / RTI > The electrode separation pattern 175 may include an insulating material. For example, the electrode separation pattern 175 may be formed of a high-density plasma oxide layer, a SOG layer (Spin On Glass layer), and / or a CVD oxide layer.

Referring again to FIG. 2, a bit line BL electrically connected to the drain region D may be formed. The bit line BL may extend in the first direction. The bit line BL may be formed on the uppermost insulating layer 126 and the electrode isolation pattern 175. Alternatively, an interlayer dielectric layer covering the uppermost insulating layer 126 and the electrode isolation pattern 175 may be formed, and the bit line BL may be formed on the interlayer dielectric layer. In this case, the bit line BL may be electrically connected to the drain region D via a contact plug passing through the interlayer dielectric film.

Although it has been described with reference to FIGS. 2 to 12 that both the upper and lower selection gate films 111 and 112 are formed before formation of the cell gate films 160, one of the upper and lower selection gate films 111 and 112 And may be formed in the same manner as the cell gate films 160.

According to the first embodiment of the present invention, the insulating film of the select gate and the cell gate can be formed of different materials. That is, the tunnel insulating film of the selection gate may not include the charge storage film. Accordingly, it is possible to prevent the threshold voltage of the selection transistor from becoming unstable by the hot carrier. In addition, the material of the select gate and the cell gate can be formed differently. Also, the gate length of the select gate can be more easily controlled than the case of forming the select gate and the cell gate together. That is, when the select gate is formed through gate replacement, the conductive film can be conformally formed along the recess region without increasing the recess region when the gate length of the select gate is increased. According to the first embodiment of the present invention, such a problem can be solved.

13 to 16, a method of manufacturing a semiconductor device according to a modification of the first embodiment will be described. Some structures and forming methods of this embodiment are similar to those of the first embodiment. Thus, for brevity's sake, a description of overlapping technical features may be omitted below.

Referring to FIG. 13, the selective gate films 111 and 112, the sacrificial films SC, the insulating films 120, and the buffer insulating film 105 of FIG. 4 are successively patterned to form through regions (132) may be formed. The through regions 132 may be formed using an anisotropic etching process. At the time of forming the through regions 132, a part of the substrate 100 may be etched together.

Referring to FIG. 14, a select gate insulating film 141 may be formed on the sidewalls of the select gate films 111 and 112 exposed by the penetration regions 132. The select gate insulating layer 141 may be formed by a thermal oxidation process. During the thermal oxidation process, a substrate thermal oxidation film 142 may be formed on the exposed substrate 100. The substrate thermal oxide film 142 may be thinner than the select gate insulating film 141. That is, when the select gate films 111 and 112 are polysilicon and the substrate 100 is monocrystalline silicon, an oxide film formed by a thermal oxidation process may be formed thicker on the polysilicon selective gate films 111 and 112 .

Referring to FIG. 15, the lower surface of the substrate thermally-oxidized film 142 can be removed. The removal of the lower surface of the substrate thermally-oxidized film 142 can be performed by dry etching using a plasma having high linearity. The side wall portion of the substrate thermally-oxidized film 142 may remain.

16, a semiconductor device according to a modification of the first embodiment is provided. The structure of Fig. 16 can be achieved by performing the processes described with reference to Figs. 8 to 12 on the structure of Fig. 12, a side wall portion of the substrate thermally-oxidized film 142 may remain on the substrate 100. Referring to FIG.

17 to 19, a method of manufacturing a semiconductor device according to another modification of the first embodiment will be described. For brevity's sake, the description of redundant technical features may be omitted.

17 shows another method of removing the bottom surface of the substrate thermally-oxidized film 142 described in Fig. Spacers 154 may be formed on the sidewalls of the through regions 132. The spacers 154 may be formed of polysilicon. A part of the lower surface of the substrate thermally-oxidized film 142 can be removed using the spacer 154 as an etching mask. When the lower surface of the substrate thermally-oxidized film 142 is removed, a part of the substrate 100 may be removed together. The etching process may be a dry and / or wet etching process.

Referring to FIG. 18, a channel pattern 151 may be formed on the spacer 154. A buried layer 155 filling the penetration region 132 may be formed in the channel pattern 151.

Referring to Fig. 19, a semiconductor device according to another modification of the first embodiment is provided. The structure of Fig. 19 can be achieved by performing the processes described with reference to Figs. 10 to 12 on the structure of Fig. The spacer 154 and the channel pattern 151 may form an active region together. Alternatively, if the spacer 154 is formed of an insulating film, it may be removed before the channel pattern 151 is formed. A part of the substrate thermally-oxidized film 142 may remain on the lower surface of the active pattern 159.

20 to 21, a method of manufacturing a semiconductor device according to still another modification of the first embodiment will be described. For brevity's sake, the description of redundant technical features may be omitted.

Fig. 20 shows the result of removing the substrate thermally-oxidized film 142 from the structure of Fig. As shown in FIG. 14, the substrate thermal oxide film 142 may be thinner than the select gate insulating film 141. That is, when the select gate films 111 and 112 are polysilicon and the substrate 100 is monocrystalline silicon, an oxide film formed by a thermal oxidation process may be formed thicker on the polysilicon selective gate films 111 and 112 . Therefore, when the selective gate insulating film 141 and the substrate thermal oxidation film 142 are etched together, the selective gate insulating film 141 may remain. The select gate insulating layer 141 may be thinner than before the etching. During the etching process, the sidewalls of the insulating films 120 may be etched together. The etching process may be performed with an etchant having etch selectivity to the oxide film. The sidewall of the through region 132 may be irregularly formed by the selective etching process.

Referring to Fig. 21, there is provided a semiconductor device according to still another modification of the first embodiment. The structure of Fig. 21 can be achieved by performing the processes described with reference to Figs. 8 to 12 on the structure of Fig.

22, a semiconductor device according to a second embodiment of the present invention is provided. For brevity's sake, the description of redundant technical features may be omitted.

The active pattern 159 may further include an extension E protruding from the sidewall of the active pattern 159 toward the select gate films 111 and 112. In the second embodiment, the penetration area 133 may be in the form of a trench extending in the second direction. The active pattern 159 may include a channel pattern 151 formed along sidewalls of the through region 133 and a buried layer 155 filling the through region 133. The active patterns 159 arranged in the second direction may be separated from each other by the buried pillars 176.

23 to 30, a method of manufacturing a semiconductor device according to a second embodiment of the present invention is described.

Referring to Fig. 23, the sidewalls of the select gate films 111 and 112 described in Fig. 4 can be recessed. That is, the sidewalls of the select gate films 111 and 112 exposed by the penetration region 133 can be etched. The etching process may be performed with an etchant having selectivity to silicon.

Referring to FIG. 24, a selective gate insulating film 141 may be formed on the sidewalls of the select gate films 111 and 112 exposed by the penetration regions 133. The select gate insulating layer 141 may be formed by a thermal oxidation process.

Referring to FIG. 25, the buffer insulating layer 105 exposed by the penetration region 133 may be removed to expose the substrate 100. When the buffer insulating layer 105 is removed, a part of the substrate 100 may be recessed together. For example, the removal of the buffer insulating layer 105 may be performed by dry etching using a plasma having a strong directivity.

Referring to FIG. 26, a channel pattern 151 may be formed along the side wall and the bottom of the through region 133. The channel pattern 151 may be formed of silicon. A portion of the channel pattern 151 provided on the sidewalls of the select gate films 111 and 112 may be recessed than a portion of the channel pattern 151 provided on the sidewalls of the sacrificial films SC.

Referring to FIG. 27, a buried layer 155 filling the penetration region 133 may be formed on the channel pattern 151. The buried film 155 may be a nitride film or a nitride oxide film. The channel pattern 151 and the buried layer 155 may constitute an active pattern 159. The channel pattern 151 and the buried layer 155 may be formed through CVD or ALD.

 28, the channel pattern 151, the embedded film 155, the select gate films 111 and 112, the insulating films 120 and the sacrificial films SC are successively patterned to form the trenches 135 ) Can be formed. The formation of the trenches 135 may be performed by an anisotropic etching process. The trenches 135 may extend in parallel in the second direction. Thus, the select gate films 111 and 112, the insulating films 120, and the sacrificial films SC may be in the form of a line extending in parallel in the second direction. The substrate 100 may be exposed to the bottom of the trench 135. A portion of the substrate 100 may be panned together when the trench 135 is formed.

Referring to FIG. 29, the sacrificial films SC exposed to the trenches 135 may be removed by a selective etching process to form the recessed regions 150. The selective etching process may be isotropic etching. The selective etching process may be performed by wet etching and / or isotropic dry etching. The etch rate of the sacrificial films SC by the selective etching process may be greater than the etch rates of the insulating films 120, the select gate films 111 and 112, and the channel patterns 151. Accordingly, after the selective etching process, the insulating films 120, the selective gate films 111 and 112, and the active patterns 159 may remain. The recessed regions 150 may expose portions of the sidewalls of the channel pattern 151 that are in contact with the sacrificial layers SC.

Referring to FIG. 30, after the recessed regions 150 are formed, the information storage layer 170 may be formed on the substrate 100. The information storage film 170 may be formed using a deposition technique (e.g., CVD or ALD) capable of providing excellent step coverage. Cell gate films 161 to 164: 160 filling the recessed regions 150 may be formed. After the information storage layer 170 is formed, a gate conductive layer (not shown) may be formed on the substrate 100. After the formation of the gate conductive layer, the gate conductive layer located outside the recessed regions 150 may be removed to form the cell gate layers 160 in the recessed regions 150. The cell gate films 161 to 164 located on different layers vertically from the upper surface of the substrate 100 by the etching process can be separated from each other.

A common source region 102 may be formed in the substrate 100 below the bottom surface of the trench 135. The common source region 102 may be in the form of a line extending in the second direction. The common source region 102 is a doped region of the second type dopant. The common source region 102 may be formed by implanting a second type of dopant ions into the substrate 100. At this time, the uppermost insulating film 126 may be used as an ion implantation mask.

A drain region D may be formed on the channel pattern 151. The drain region (D) may be doped with the second type of dopant. The lower surface of the drain region D may be higher than the upper surface of the upper select gate film 112. Alternatively, the lower surface of the drain region D may be a height close to the upper surface of the upper select gate film 112. The drain region D may be formed simultaneously with the common source region 102. Alternatively, the drain region D may be formed before or after the common source region 102 is formed.

An electrode separation pattern 175 filling the trench 135 may be formed. The electrode separation pattern 175 may be formed by forming an electrode separation pattern filling the trench 135 on the substrate 100 and performing a planarization process until the uppermost insulation layer 126 is exposed ≪ / RTI > The electrode separation pattern 175 may include an insulating material. For example, the electrode separation pattern 175 may be formed of a high-density plasma oxide layer, a SOG layer (Spin On Glass layer), and / or a CVD oxide layer.

The second embodiment can be modified as the modifications of the first embodiment described with reference to Figs.

31 is a schematic block diagram showing an example of a memory system including a semiconductor memory device manufactured according to the manufacturing method of the embodiments of the present invention.

31, the memory system 1100 may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, A memory card, or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes an input / output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions executed by the controller. The input / output device 1120 may receive data or signals from outside the system 1100, or may output data or signals outside the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

Memory 1130 includes a non-volatile memory device in accordance with embodiments of the present invention. Memory 1130 may also include other types of memory, volatile memory that may be accessed at any time, and various other types of memory.

The interface 1140 serves to transmit data to and receive data from the communication network.

32 is a schematic block diagram showing an example of a memory card having a semiconductor memory device manufactured according to the manufacturing method of the embodiments of the present invention.

Referring to FIG. 32, a memory card 1200 for supporting a high capacity data storage capability mounts a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 has a data exchange protocol of a host connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs all control operations for data exchange of the memory controller 1220. Although it is not shown in the drawing, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned.

33 is a schematic block diagram showing an example of an information processing system for mounting a semiconductor memory device manufactured according to the manufacturing method of the embodiments of the present invention.

Referring to FIG. 33, the flash memory system 1310 of the present invention is installed in an information processing system such as a mobile device or a desktop computer. An information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, a user interface 1350, . The flash memory system 1310 will be configured substantially the same as the memory system or flash memory system mentioned above. The flash memory system 1310 stores data processed by the central processing unit 1330 or externally input data. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention can be provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. It is clear to those who have learned.

Further, the flash memory device or memory system according to the present invention can be mounted in various types of packages. For example, the flash memory device or the memory system according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

100, 200: substrate 105, 205: buffer insulating film
111, 112: selection gate film 120: insulating film
141: select gate insulating film 142: substrate thermal oxide film
159: active pattern 160: cell gate film
170: Information storage film

Claims (10)

Forming a stacked structure including sacrificial films and a selective gate film on a substrate;
Forming a through region through the laminated structure;
Forming a selective gate insulating film on a sidewall of the select gate film exposed by the through region;
Forming an active pattern in the through region;
Removing the sacrificial layers to expose a portion of the sidewalls of the active pattern; And
And forming an information storage film on a part of the side wall of the exposed active pattern. The method of manufacturing a semiconductor device according to claim 1, wherein the select gate insulating film is formed before formation of the active pattern, and the information storage film is formed after formation of the active pattern. The method of manufacturing a semiconductor device according to claim 1, wherein the select gate film is formed of polysilicon. The method of manufacturing a semiconductor device according to claim 1, wherein forming the select gate insulating film is performed by a thermal oxidation process. The method of claim 1, wherein forming the select gate film comprises:
Forming a lower selection gate film between the sacrificial films and the substrate; And
And forming an upper select gate film on the sacrificial films. The method according to claim 1, further comprising forming a buffer insulating film between the substrate and the laminated structure. 7. The semiconductor memory device according to claim 6, wherein forming the penetrating region includes exposing the buffer insulating film,
Further comprising removing the buffer insulating layer exposed by the through region after the formation of the select gate insulating layer to expose the substrate. The method of manufacturing a semiconductor device according to claim 1, further comprising, before formation of the select gate insulating film, recessing a sidewall of the select gate film exposed by the penetration region. An active pattern vertically disposed on a substrate;
A first select gate layer and a second select gate layer disposed on the substrate;
A plurality of cell gate layers vertically stacked with insulating layers between the first select gate layer and the second select gate layer;
A selective gate insulating film disposed between the active pattern and the first select gate layer;
A tunnel insulating layer disposed between the active pattern and the cell gate layers; And
And blocking insulating films respectively disposed between the tunnel insulating film and the cell gate layers,
Wherein the first and second select gate layers and the cell gate layers comprise a conductive material,
The lower surfaces and upper surfaces of the first and second select gate layers are in direct contact with the insulating layers,
The blocking insulating films extending between upper surfaces of the cell gate layers and between the insulating layers and between the lower surfaces of the cell gate layers and the insulating layers between the sidewalls of the cell gate layers and the tunnel insulating film,
The sidewall of the first select gate layer is recessed in a horizontal direction parallel to the upper surface of the substrate, as compared to the sidewall of the cell gate layer,
Wherein the active pattern comprises an extension protruding toward the sidewall of the first select gate layer,
Wherein the select gate insulating film is thicker than the tunnel insulating film in a direction parallel to the upper surface of the substrate. 10. The method of claim 9,
In a direction perpendicular to the top surface of the substrate, the first select gate layer is thicker than the cell gate layers,
Wherein the cell gate layers comprise at least one of a metal, a metal suicide, and a conductive metal nitride, and wherein the first and second select gate layers comprise polysilicon.

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