CN107579072B - Method for forming channel layer in 3D NAND device and wafer box structure - Google Patents
Method for forming channel layer in 3D NAND device and wafer box structure Download PDFInfo
- Publication number
- CN107579072B CN107579072B CN201710772366.4A CN201710772366A CN107579072B CN 107579072 B CN107579072 B CN 107579072B CN 201710772366 A CN201710772366 A CN 201710772366A CN 107579072 B CN107579072 B CN 107579072B
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- channel
- inert gas
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The embodiment of the invention provides a method for forming a channel layer in a 3D NAND device, which comprises the following steps: providing a substrate, wherein a stack layer, a channel hole in the stack layer and a charge trapping layer on the inner wall of the channel hole are formed on the substrate, the stack layer is formed by alternately laminating a silicon nitride layer and a silicon oxide layer, a first polycrystalline silicon layer is formed on the side wall of the channel hole, the substrate with the first polycrystalline silicon layer is placed in an inert gas environment or a nitrogen environment, and a second polycrystalline silicon layer is formed in the channel hole. In the method, after the first polycrystalline silicon layer is formed and before the second polycrystalline silicon layer is formed, the substrate is placed in an inert gas or nitrogen environment, so that the natural oxidation of the first polycrystalline silicon layer in the waiting process before the second polycrystalline silicon layer is grown can be effectively inhibited, the ratio of silicon oxide in the channel layer is reduced, the channel resistance is reduced, and the performance of the device is improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a method for forming a channel layer in a 3D NAND device and a wafer box structure.
Background
With the continuous progress of informatization, people have higher requirements on information storage, and a flash memory is a long-life nonvolatile memory and is widely applied to electronic products. At present, the NAND flash memory with a planar structure is near the limit of practical expansion, and in order to further improve the storage capacity and reduce the storage cost per bit, the NAND flash memory with a 3D structure is provided.
in the 3D NAND memory structure, a stacked 3D NAND memory structure is realized by vertically stacking a plurality of layers of data storage units. In forming the 3D NAND memory, first, a stacked layer of a silicon nitride (SiN) layer and a silicon oxide (SiO2) layer is formed on a substrate; then, a Channel hole (tunnel hole) for forming a storage region including a charge trap layer of ONO (Oxide-Nitride-Oxide) and a Channel layer of polysilicon is formed in the stacked layers.
In the traditional method for forming the polysilicon channel layer, the channel resistance is large, and the overall performance of the device is influenced.
Disclosure of Invention
The invention provides a method for forming a channel layer in a 3D NAND device and a wafer box structure, which reduce channel resistance and optimize the performance of the device.
The invention provides a method for forming a channel layer in a 3D NAND device, which comprises the following steps:
Providing a substrate, wherein a stacking layer, a channel hole in the stacking layer and a charge trapping layer on the inner wall of the channel hole are formed on the substrate; the stacked layer is formed by alternately stacking silicon nitride layers and silicon oxide layers;
Forming a first polysilicon layer on the side wall of the channel hole;
placing the substrate with the first polycrystalline silicon layer in an inert gas or nitrogen environment;
And forming a second polysilicon layer in the channel hole.
optionally, the inert gas in a nitrogen environment or the oxygen content in a nitrogen environment is less than or equal to 50 ppm.
Optionally, the nitrogen environment is provided by a wafer box, and an inert gas or nitrogen atmosphere is provided in the wafer box.
Optionally, an air inlet pipe and an air outlet pipe are arranged on the wafer box, and inert gas or nitrogen is transmitted through the air inlet pipe and the air outlet pipe, so that the wafer box is filled with the inert gas or nitrogen.
Optionally, the gas flow range during nitrogen gas transmission is as follows: 10-100 SLM.
The application also provides a wafer box structure, wafer box structure includes:
a wafer cassette cavity for: placing a substrate formed with a first polysilicon layer;
A wafer chamber door to: isolating the outside air;
an intake duct for: introducing nitrogen or inert gas into the wafer box;
The outlet duct is used for: the gas in the wafer box is led out of the box.
optionally, an inert gas or nitrogen atmosphere is set in the wafer box cavity.
Optionally, the cavity of the wafer box is provided with a groove for placing a substrate.
According to the method for forming the channel layer in the 3D NAND device and the wafer box structure provided by the embodiment of the invention, the substrate is provided, the stack layer, the channel hole in the stack layer and the charge trapping layer on the inner wall of the channel hole are formed on the substrate, the stack layer is formed by alternately laminating a silicon nitride layer and a silicon oxide layer, the first polycrystalline silicon layer is formed on the side wall of the channel hole, the substrate formed with the first polycrystalline silicon layer is placed in an inert gas or nitrogen environment, and the second polycrystalline silicon layer is formed in the channel hole. In the method, after the first polycrystalline silicon layer is formed and before the second polycrystalline silicon layer is formed, the substrate is placed in an inert gas or nitrogen environment, so that the natural oxidation of the first polycrystalline silicon layer in the waiting process before the second polycrystalline silicon layer is grown can be effectively inhibited, the ratio of silicon oxide in the channel layer is reduced, the channel resistance is reduced, and the performance of the device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1 shows a cross-sectional structure diagram of a channel layer in a 3D NAND memory in the prior art;
FIG. 2 shows a flow chart of a method of forming a channel layer in a 3D NAND memory according to an embodiment of the present application;
FIGS. 3a to 3c are schematic diagrams illustrating a process of forming a channel layer in a 3D NAND memory;
FIG. 4 shows a schematic cross-sectional structure of a channel layer in a 3D NAND memory according to an embodiment of the application;
Fig. 5 shows a schematic structural diagram of a wafer cassette according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
First, in the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and it will be apparent to those skilled in the art that the present invention may be practiced without departing from the spirit and scope of the invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
Next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
A channel layer of polysilicon is formed in the channel hole, typically using two depositions. The reaction gas for the first deposition may be disilane (Si)2H6) The reaction gas is thermally decomposed to produce a first polysilicon layer having a high hydrogen content. In the second deposition process, the reactant gas is typically Silane (SiH)4) The gas can be used for producing polysilicon with low hydrogen content through thermal decomposition reaction, and is easy to be useda thicker and uniform second polysilicon layer is grown.
the applicant finds that in the prior art, after the first deposition of polysilicon is performed, the wafer is usually placed in a wafer box to wait for the second deposition of polysilicon, and because the sealing performance of the wafer box door is poor, moisture and oxygen in the atmosphere can diffuse into the wafer box cavity, so that the surface of the first polysilicon is easily oxidized naturally, a silicon oxide film is formed, and the channel resistance is increased. The longer the wafer is left in the cassette, the thicker the resulting silicon oxide film, which is typically about 10 angstroms thick in 2 hours, and after more than 10 hours, the silicon oxide layer can reach a thickness of more than 50 angstroms, as shown in fig. 1. Such a silicon oxide layer increases channel resistance, affecting the performance of the device.
In order to solve this problem, the present application proposes a method of forming a channel layer in a 3D NAND device, as shown in fig. 2, the method of forming including:
Step 101, providing a substrate, wherein a stack layer, a channel hole in the stack layer and a charge trapping layer on the inner wall of the channel hole are formed on the substrate; the stacked layer is formed by alternately stacking silicon nitride layers and silicon oxide layers.
in the embodiments of the present application, the substrate is a semiconductor substrate, which is a base for forming a transistor or other semiconductor devices. On one hand, the substrate provides support for devices thereon, and as most of the devices thereon are devices made of thin films, the substrate is required to be used as mechanical support; on the other hand, the substrate is used to form part of the structure of the device, such as a well region or a source drain region in the substrate. .
In the embodiment of the present application, the substrate may be a semiconductor substrate such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator). In other embodiments, the semiconductor substrate may also be a substrate of other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like. In this particular embodiment, the substrate is a silicon substrate.
in the present embodiment, as shown in fig. 3a, stacked layers 110 are formed by alternately stacking silicon nitride layers 1102 and silicon oxide layers 1101 on a substrate 100, the number of stacked layers is determined according to the number of memory cells to be formed in the vertical direction, the number of stacked layers may be, for example, 8, 32, or 64, and the higher the number of stacked layers, the higher the device integration. The stacked layers may be formed by alternately depositing silicon nitride and silicon oxide in sequence using chemical vapor deposition, atomic layer deposition, or other suitable deposition methods.
The channel hole in the stacked layer is a through hole in the stacked layer, and the stacked layer may be etched by using an etching technique, such as a RIE (reactive ion etching) method, until the surface of the substrate is exposed, or a portion of the substrate is over-etched, thereby forming the channel hole. After the channel hole is formed, an Epitaxial structure 122, which serves to connect the memory regions in the channel hole, is grown in situ at the bottom of the channel hole, typically by Selective Epitaxial Growth (Selective Epitaxial Growth). After the epitaxial silicon structure is formed, a charge trapping layer 124, which in this embodiment is a stack of ONO (Oxide-nitride-Oxide), i.e., a stack of Oxide, nitride and Oxide, may be formed in the channel hole by atomic deposition.
Step 102, a first polysilicon layer is formed on the sidewall of the channel hole.
The first polysilicon is formed by a first deposition, and the reaction gas may be disilane (Si)2H6) The reaction gas is thermally decomposed to produce polycrystalline silicon having a high hydrogen content. After the first deposition, the polysilicon layer 1301 in fig. 3a is formed, the formed first polysilicon layer is etched back, and a portion of the polysilicon is etched away to form the first polysilicon layer 1301 with a suitable thickness, as shown in fig. 3 b. The first deposition process forms polysilicon with uniform film thickness and high hydrogen content, and the hydrogen is helpful for enabling the polysilicon to have larger crystal grains during crystallization in the subsequent thermal annealing, but is not easy to form a thicker layer.
And 103, placing the substrate with the first polycrystalline silicon layer in an inert gas or nitrogen environment.
The substrate with the first polysilicon layer formed thereon is placed in an inert gas or nitrogen environment, which may be selected as needed, and in a preferred embodiment, the inert gas or nitrogen environment is provided by a wafer box, specifically: and placing the substrate with the first polycrystalline silicon layer in a wafer box, wherein the wafer box is in an inert gas or nitrogen atmosphere, and the oxygen content range is less than or equal to 50 ppm. Can set up intake pipe and outlet duct on the wafer box, the one end of intake pipe can be connected with the air supply of inert gas or nitrogen gas, the air supply can be the gas cylinder for example, also can be the pipeline of inert gas or nitrogen gas, the other end is connected with the wafer box for carry inert gas or nitrogen gas in to the wafer box, the one end of outlet duct is connected with the wafer box, the other end is connected with exhaust gas pipeline or quiet arrange in the atmosphere, be arranged in with the gaseous output in the wafer box outside the wafer box, atmospheric pressure in the balanced box simultaneously. The air inlet pipe can be further provided with a flow control valve for controlling the air inlet flow of the nitrogen, and the transmission flow range of the nitrogen is as follows: 10-100 SLM.
In the embodiment of the application, the inert gas or the nitrogen gas is used as the protective gas of the first polysilicon to isolate the first polysilicon from oxygen and moisture, so that the natural oxidation of the first polysilicon is avoided. This is because the silicon oxide generated by natural oxidation has a larger resistance than the polysilicon layer, which is the channel layer of the memory device, and the existence of the thick silicon oxide layer increases the overall resistance of the channel layer, which affects the device performance.
Typically at room temperature with little moisture, the growth rate of silicon oxide is between 5 and 10 angstroms per hour, and in the presence of moisture, the oxidation rate can even be up to 10 times the dry oxygen oxidation rate, so that if the deposition of the second polysilicon layer is not carried out within two hours, a relatively thick silicon oxide layer is formed, and the effect on the channel layer resistance will be significant. In the inert gas or nitrogen environment in the embodiment of the application, the moisture content and the oxygen content are relatively low, and the growth rate of silicon oxide can be effectively reduced, so that the placing time of the first polysilicon can be correspondingly prolonged, the original maximum 2 hours is prolonged to 2-12 hours, the placing time can be prolonged even infinitely under the condition of extremely low oxygen, the operation is easier in the preparation process of a 3D NAND device, and meanwhile, the resistance of a channel layer is reduced, and the performance of the device is improved.
After step 103, an etch may also be performed to remove the charge trapping layer 124 on the epitaxial structure and the first polysilicon layer 1301, as shown in fig. 3 b. Since the channel layer needs to be in contact with the epitaxial structure at the bottom of the channel hole, an opening needs to be formed at the bottom of the channel to remove the charge trapping layer and the polysilicon layer on the epitaxial structure, so that a second polysilicon layer deposited later can be in contact with the epitaxial silicon structure.
Before the bottom is etched and opened, a silicon oxide protective layer may be deposited to protect the first polysilicon layer, and then the first polysilicon layer plays a role in protecting the charge trapping layer during the etching and opening process by dry etching, for example, an etching method such as RIE. And etching to remove the first polysilicon layer and the charge trapping layer at the bottom of the channel hole so as to expose the epitaxial silicon structure at the bottom of the channel hole, and then removing the silicon oxide protective layer, so that the second polysilicon layer can be in direct contact with the epitaxial silicon structure after the subsequent deposition of the second polysilicon layer.
The step of removing the charge trapping layer 124 and the first polysilicon layer 1301 in the epitaxial structure by etching may be performed between step 103 and step 104, or may be performed between step 102 and step 103, and does not affect the implementation of the present application.
Step 104, forming a second polysilicon layer in the channel hole.
In the deposition of the second polysilicon, the reaction gas is Silane (SiH)4) The gas can be thermally decomposed to produce polycrystalline silicon having a low hydrogen content, and thick and uniform polycrystalline silicon can be easily produced. After the second deposition, a polysilicon layer 1302 is formed, and a second polysilicon layer of suitable thickness is formed by etching back a portion of the thickness of the polysilicon, as shown in fig. 3 c. After the first and second depositions, a thermal anneal is also typically performed to crystallize the polysilicon.
As shown in fig. 4, which is a condition of the channel layer after the channel layer forming method of the present application is applied, the total thickness of the first polysilicon and the second polysilicon in fig. 4 is 10.82nm, and there is no significant intermediate silicon oxide layer. Whereas the total thickness of the first polysilicon and the second polysilicon in fig. 1 is 15.57nm, it is apparent that an oxide film is formed therebetween. Obviously, the method for forming the channel layer in the 3DNAND device provided by the application obviously inhibits the formation of the oxide film.
According to the method for forming the channel layer in the 3D NAND device, provided by the embodiment of the invention, the substrate is provided, the stack layer, the channel hole in the stack layer and the charge trapping layer on the inner wall of the channel hole are formed on the substrate, the stack layer is formed by alternately laminating the silicon nitride layer and the silicon oxide layer, the first polycrystalline silicon layer is formed on the side wall of the channel hole, the substrate with the first polycrystalline silicon layer is placed in an inert gas environment or a nitrogen environment, and the second polycrystalline silicon layer is formed in the channel hole. The method inhibits the growth of an oxide film in the process of waiting for the deposition of the second polysilicon layer after the first polysilicon layer is formed, reduces the channel resistance and improves the performance of the device.
the present application further provides a wafer box structure, as shown in fig. 5, the wafer box structure includes a wafer box cavity 200, an air inlet pipe 210, an air outlet pipe 220, wherein:
A wafer cassette cavity 200 for: placing the wafer;
An intake pipe 210 for: introducing inert gas or nitrogen into the wafer box;
an outlet duct 220 for: the gas in the wafer box is led out of the box.
And an inert gas or nitrogen atmosphere is arranged in the wafer box cavity.
the wafer box cavity is provided with a groove for placing the substrate.
the working principle of the wafer box structure is as follows: and placing the substrate with the first polycrystalline silicon layer in a cavity of the wafer box, and conveying inert gas or nitrogen through the gas inlet pipe and the gas outlet pipe to realize the atmosphere of the inert gas or nitrogen in the cavity of the wafer box and reduce the growth rate of the oxide on the surface of the first polycrystalline silicon layer so as to form a second polycrystalline silicon layer in the channel hole.
By using the wafer box structure, the waiting time of the wafer in the wafer box structure is prolonged, the natural oxidation of the first polycrystalline silicon layer in the waiting process before the growth of the second polycrystalline silicon layer is inhibited, the channel resistance is reduced, and the performance of the device is improved.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, they are described in a relatively simple manner, and reference may be made to some descriptions of method embodiments for relevant points. The above-described system embodiments are merely illustrative, wherein the modules or units described as separate parts may or may not be physically separate, and the parts displayed as modules or units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Claims (4)
1. A method for forming a channel layer in a 3D NAND device, comprising:
Providing a substrate, wherein a stacking layer, a channel hole in the stacking layer and a charge trapping layer on the inner wall of the channel hole are formed on the substrate; the stacked layer is formed by alternately stacking silicon nitride layers and silicon oxide layers;
Forming a first polysilicon layer on the side wall of the channel hole;
Placing the substrate with the first polycrystalline silicon layer in an inert gas or nitrogen environment; the inert gas or nitrogen environment is provided by the wafer box;
And forming a second polysilicon layer in the channel hole.
2. The method of claim 1, wherein the oxygen content in the inert gas or nitrogen environment is less than or equal to 50 ppm.
3. the method of claim 1, wherein the wafer box is provided with an inlet pipe and an outlet pipe, and inert gas or nitrogen is transmitted through the inlet pipe and the outlet pipe, so that the inside of the wafer box is in an inert gas or nitrogen atmosphere.
4. The method of claim 3, wherein the inert gas or nitrogen is delivered at a gas flow rate in the range of: 10-100 SLM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710772366.4A CN107579072B (en) | 2017-08-31 | 2017-08-31 | Method for forming channel layer in 3D NAND device and wafer box structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710772366.4A CN107579072B (en) | 2017-08-31 | 2017-08-31 | Method for forming channel layer in 3D NAND device and wafer box structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107579072A CN107579072A (en) | 2018-01-12 |
| CN107579072B true CN107579072B (en) | 2019-12-13 |
Family
ID=61030724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710772366.4A Active CN107579072B (en) | 2017-08-31 | 2017-08-31 | Method for forming channel layer in 3D NAND device and wafer box structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107579072B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110444496A (en) * | 2018-05-06 | 2019-11-12 | 长鑫存储技术有限公司 | The diffusion generation method and equipment of conductive polycrystalline silicone tip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203774266U (en) * | 2014-03-24 | 2014-08-13 | 上海华力微电子有限公司 | Silicon wafer box nitrogen filling cabinet |
| CN105374824A (en) * | 2014-08-14 | 2016-03-02 | 三星电子株式会社 | Semiconductor device |
| US9478495B1 (en) * | 2015-10-26 | 2016-10-25 | Sandisk Technologies Llc | Three dimensional memory device containing aluminum source contact via structure and method of making thereof |
| CN106941088A (en) * | 2016-01-05 | 2017-07-11 | 台湾积体电路制造股份有限公司 | Wafer holder |
-
2017
- 2017-08-31 CN CN201710772366.4A patent/CN107579072B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203774266U (en) * | 2014-03-24 | 2014-08-13 | 上海华力微电子有限公司 | Silicon wafer box nitrogen filling cabinet |
| CN105374824A (en) * | 2014-08-14 | 2016-03-02 | 三星电子株式会社 | Semiconductor device |
| US9478495B1 (en) * | 2015-10-26 | 2016-10-25 | Sandisk Technologies Llc | Three dimensional memory device containing aluminum source contact via structure and method of making thereof |
| CN106941088A (en) * | 2016-01-05 | 2017-07-11 | 台湾积体电路制造股份有限公司 | Wafer holder |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107579072A (en) | 2018-01-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI811348B (en) | Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures | |
| US10269571B2 (en) | Methods for fabricating nanowire for semiconductor applications | |
| US9165940B2 (en) | Three dimensional NAND device with silicide containing floating gates and method of making thereof | |
| KR20050031455A (en) | Method of forming nanocrystals | |
| CN108649034B (en) | Semiconductor structure and forming method thereof | |
| JP2014512669A (en) | Low temperature selective epitaxy method | |
| CN112997272B (en) | Epitaxial layer and forming method and annealing equipment of 3D NAND memory | |
| US20200051994A1 (en) | Memory device improvement | |
| CN101436533A (en) | Modulating the stress of poly-crystaline silicon films and surrounding layers through the use of dopants and multi-layer silicon films with controlled crystal structure | |
| TW202008471A (en) | Method of forming semiconductor device | |
| CN110211960A (en) | A kind of 3D nand memory part and its manufacturing method | |
| CN107579072B (en) | Method for forming channel layer in 3D NAND device and wafer box structure | |
| CN108962903B (en) | Semiconductor structure | |
| US20140145305A1 (en) | Capacitor and Method of Forming a Capacitor | |
| CN110265402A (en) | A kind of 3D nand memory part and its manufacturing method | |
| CN110265403A (en) | A kind of 3D nand memory part and its manufacturing method | |
| TWI233650B (en) | Method of manufacturing semiconductor device | |
| US20230163197A1 (en) | Semiconductor Device and Method of Manufacture | |
| US20200098861A1 (en) | High density nanotubes and nanotube devices | |
| CN107611134B (en) | A kind of forming method of 3D NAND device | |
| CN114023760A (en) | Three-dimensional memory and manufacturing method thereof | |
| KR20230129520A (en) | CD-dependent gap filling and conformal films | |
| KR20210158809A (en) | Method for forming a layer provided with silicon | |
| TWI709174B (en) | Radical oxidation process for fabricating a nonvolatile charge trap memory device | |
| US8324050B2 (en) | Method of manufacturing flash memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |