CN114023760A - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN114023760A CN114023760A CN202111290875.6A CN202111290875A CN114023760A CN 114023760 A CN114023760 A CN 114023760A CN 202111290875 A CN202111290875 A CN 202111290875A CN 114023760 A CN114023760 A CN 114023760A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The present disclosure provides a three-dimensional memory and a method of fabricating the same. The manufacturing method comprises the following steps: providing a semiconductor substrate with a stacked body on the surface, and sequentially etching the stacked body and the semiconductor substrate to form a channel through hole penetrating through the stacked body and a groove located in the semiconductor substrate, wherein the groove is communicated with the channel through hole; performing solid phase epitaxial growth on the inner surface of the groove to form an epitaxial layer in the groove and part of the channel through hole; a channel structure is formed on the epitaxial layer in the channel via. Compared with the process for forming the epitaxial layer by Selective Epitaxial Growth (SEG) in the prior art, the solid phase epitaxy method has lower requirement on the cleanness degree of the substrate interface and can also greatly reduce the thermal budget (thermal budget) of the epitaxial growth, thereby effectively reducing the influence of the overhigh thermal budget on the curvature of the substrate.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.
Background
In the prior art, a Flash Memory (Flash Memory) has a main function of maintaining stored information for a long time without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, so that the Flash Memory is widely applied to electronic products. In order to further improve the Bit Density (Bit Density) of the flash memory and at the same time reduce the Bit Cost (Bit Cost), a 3D NAND memory is further proposed.
In the current 3D NAND memory, a stacked 3D NAND memory structure is generally implemented by vertically stacking multiple layers of data storage units. In order to obtain the stacked 3D NAND memory structure, a stacked structure is formed on a silicon substrate, a trench via is formed by etching the stacked structure, a silicon trench is formed by further etching to penetrate into the substrate, and then a Selective Epitaxial Growth (SEG) of silicon is performed on the surface of the silicon trench to form an epitaxial layer.
In the existing SEG process, a method of vapor deposition on the surface of a substrate to extend on the surface of the silicon is adopted, but the method has high requirements on solid surface cleaning and high thermal budget (thermal budget), which causes high cost, and the too high thermal budget in the SEG process causes large substrate bow (wafer bow) along with the increase of the number of layers of the 3D NAND memory.
Disclosure of Invention
The disclosure provides a three-dimensional memory and a manufacturing method thereof, and aims to solve the problem that a process of forming an epitaxial layer through selective epitaxial growth in a 3D NAND memory in the prior art is prone to causing large substrate curvature.
According to an aspect of the present disclosure, there is provided a method for manufacturing a three-dimensional memory, including the steps of: providing a semiconductor substrate with a stacked body on the surface, and sequentially etching the stacked body and the semiconductor substrate to form a channel through hole penetrating through the stacked body and a groove located in the semiconductor substrate, wherein the groove is communicated with the channel through hole; performing solid phase epitaxial growth on the inner surface of the groove to form an epitaxial layer in the groove and part of the channel through hole; a channel structure is formed on the epitaxial layer in the channel via.
Further, the step of performing solid phase epitaxial growth on the surface of the groove comprises: the step of performing solid phase epitaxial growth on the surface of the groove comprises the following steps: depositing an amorphous semiconductor material in the channel through hole, wherein the amorphous semiconductor material covers the metal layer and the side wall of part of the channel through hole; and annealing the amorphous semiconductor material, wherein the amorphous semiconductor material is diffused to the inner surface of the groove through the metal layer and crystallized to form an epitaxial layer.
Further, the thickness of the metal layer is 10-50 nm.
Further, the metal layer includes Ni and/or Co.
Further, a metal layer is deposited on the inner surface of the groove by adopting a plasma enhanced chemical vapor deposition process.
Further, the semiconductor substrate is a silicon substrate, and the amorphous semiconductor material is amorphous silicon.
Further, annealing the amorphous semiconductor material at 300-500 ℃.
Further, the stacked body includes a plurality of sacrificial layers and a plurality of isolation layers alternately stacked in a direction away from the substrate, and after the step of forming the channel structure, the manufacturing method further includes the steps of: and replacing the sacrificial layer into a control gate structure to form a gate stack structure, forming a plurality of common sources penetrating through the substrate in the gate stack structure, and positioning the channel structure between the adjacent common sources.
According to another aspect of the present disclosure, there is provided a three-dimensional memory including: the semiconductor device comprises a semiconductor substrate, wherein a grid stacking structure is arranged on the semiconductor substrate, a channel through hole penetrating through the semiconductor substrate is formed in the grid stacking structure, a groove communicated with the channel through hole is formed in the semiconductor substrate, and the grid stacking structure comprises a plurality of control grid structures and a plurality of isolation layers which are alternated along the direction far away from the substrate; the epitaxial layer is arranged in the groove and part of the channel through hole, and the epitaxial layer is a crystalline layer formed by solid phase epitaxial growth on the inner surface of the groove; and the channel structure is arranged on the epitaxial layer in the channel through hole.
Furthermore, the semiconductor substrate is a silicon substrate, and the crystallization layer is a polysilicon layer.
Further, the three-dimensional memory further includes: and the common source is arranged in the grid stacking structure and penetrates through the substrate, and the channel structure is positioned between the adjacent common sources.
Compared with the process for forming the epitaxial layer by Selective Epitaxial Growth (SEG) in the prior art, the method adopting the solid phase epitaxy has lower requirement on the cleanness degree of the substrate interface and can also greatly reduce the thermal budget (thermal budget) of the epitaxial growth, thereby effectively reducing the influence of the overhigh thermal budget on the curvature of the substrate.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and are not to limit the disclosure. In the drawings:
fig. 1 is a schematic flow chart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram showing a cross-sectional structure of a base after sequentially etching a stacked body and a semiconductor substrate to form a trench via penetrating through the stacked body and a groove in the semiconductor substrate in a method for manufacturing a three-dimensional memory provided in an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of the substrate after a metal layer is deposited on the inner surface of the recess shown in FIG. 2;
FIG. 4 is a cross-sectional view of the substrate after depositing an amorphous semiconductor material in the trench via shown in FIG. 3, wherein the amorphous semiconductor material covers the metal layer and the sidewalls of a portion of the trench via;
FIG. 5 is a schematic cross-sectional view of the substrate after annealing the amorphous semiconductor material of FIG. 4, the amorphous semiconductor material diffusing through the metal layer to the inner surface of the recess and crystallizing to form an epitaxial layer;
FIG. 6 is a schematic cross-sectional view of the substrate after forming a channel structure on the epitaxial layer in the channel via shown in FIG. 5;
FIG. 7 is a schematic cross-sectional view of the substrate after the sacrificial layer of FIG. 6 is replaced with a gate structure;
fig. 8 shows a schematic cross-sectional view of the substrate after common source formation in the gate spacer of fig. 7.
Wherein the figures include the following reference numerals:
10. a semiconductor substrate; 101. a trench via; 102. a groove; 20. a stack; 210. a sacrificial layer; 220. an isolation layer; 230. a gate structure; 30. a metal layer; 40. an amorphous semiconductor material; 50. an epitaxial layer; 60. a channel structure; 610. a functional layer; 620. a channel layer; 630. a dielectric fill layer; 70. a gate spacer; 80. a doped region; 90. selecting a gate dielectric layer; 100. an insulating material; 110. a common source.
Detailed Description
It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the technical solutions of the present disclosure better understood by those skilled in the art, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure may be described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, in order to obtain the stacked 3D NAND memory structure, it is necessary to form a stacked structure on a silicon substrate, etch the stacked structure to form a trench via, further etch the stacked structure to penetrate into the substrate to form a silicon trench, and then perform Selective Epitaxial Growth (SEG) of silicon on the surface of the silicon trench to form an epitaxial layer, while in the existing SEG process, a method of depositing a vapor phase on the surface of the substrate to perform epitaxy on the surface of the silicon is adopted, but this method requires high requirements for cleaning the solid surface and high thermal budget (thermal budget), which results in high cost, and as the number of layers of the 3D NAND memory increases, the high thermal budget in the SEG process results in large substrate bow (wafer bow).
The inventor of the present disclosure has studied the above problem and proposed a method for manufacturing a three-dimensional memory, as shown in fig. 1, including the following steps: providing a semiconductor substrate with a stacked body on the surface, and sequentially etching the stacked body and the semiconductor substrate to form a channel through hole penetrating through the stacked body and a groove located in the semiconductor substrate, wherein the groove is communicated with the channel through hole; performing solid phase epitaxial growth on the inner surface of the groove to form an epitaxial layer in the groove and part of the channel through hole; a channel structure is formed on the epitaxial layer in the channel via.
Compared with the process for forming the epitaxial layer by Selective Epitaxial Growth (SEG) in the prior art, the method adopting the solid phase epitaxy has lower requirement on the cleanness degree of the substrate interface and can also greatly reduce the thermal budget (thermal budget) of the epitaxial growth, thereby effectively reducing the influence of the overhigh thermal budget on the curvature of the substrate.
Exemplary embodiments of a method of fabricating a three-dimensional memory provided according to the present disclosure will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, a semiconductor substrate 10 having a stack 20 on a surface thereof is provided, and the stack 20 and the semiconductor substrate 10 are sequentially etched to form a channel via 101 penetrating the stack 20 and a groove 102 in the semiconductor substrate 10, the groove 102 communicating with the channel via 101, as shown in fig. 2.
The material of the semiconductor substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.
The stacked body 20 may include a plurality of sacrificial layers 210 and a plurality of isolation layers 220 alternately stacked in a direction away from the substrate, and the sacrificial layers 210 and the isolation layers 220 may be formed by a conventional deposition process of the related art, such as a chemical vapor deposition process. The number of the sacrificial layer 210 and the isolation layer 220 can be set by those skilled in the art according to practical requirements, and the isolation layer 220 can be SiO2The sacrificial layer 210 may be SiN, but is not limited to the above type, and those skilled in the art can reasonably select the types of the sacrificial layer 210 and the isolation layer 220 according to the prior art.
After the step of forming the channel via 101 penetrating the stack 20 and the groove 102 in the semiconductor substrate 10, solid phase epitaxial growth is performed on the inner surface of the groove 102 to form the epitaxial layer 50 in the groove 102 and a portion of the channel via 101, as shown in fig. 3 to 5.
In a preferred embodiment, the step of performing solid phase epitaxial growth on the surface of the recess 102 comprises: depositing a metal layer 30 on the inner surface of the recess 102, as shown in fig. 3; depositing an amorphous semiconductor material 40 in the trench via 101, the amorphous semiconductor material 40 covering the metal layer 30 and a portion of the sidewalls of the trench via 101, as shown in fig. 4; the amorphous semiconductor material 40 is annealed and the amorphous semiconductor material 40 diffuses through the metal layer 30 to the inner surface of the recess 102 and crystallizes to form the epitaxial layer 50, as shown in fig. 5.
In the above embodiment, the metal layer 30 is deposited on the inner surface of the recess 102 in the semiconductor substrate 10, and a layer of amorphous semiconductor material 40 is deposited on the metal layer 30, so as to form a semiconductor (amorphous) -metal-semiconductor (amorphous) structure, and the amorphous semiconductor of the structure tends to dissolve and diffuse through the metal layer due to its high free energy when the annealing process is performed, and is crystallized by epitaxial growth on the inner surface of the recess 102.
In the step of depositing the metal layer 30, in order to make the amorphous semiconductor material 40 covered subsequently diffuse to the surface of the groove 102 more effectively through the metal layer 30, more preferably, the thickness of the metal layer 30 is 10 to 50 nm; also, preferably, the material deposited to form the metal layer 30 includes Ni and/or Co.
In order to improve the deposition efficiency, the present application may use a Plasma Enhanced Chemical Vapor Deposition (PECVD) process to deposit the metal layer 30 on the inner surface of the recess 102, but the present application is not limited to the above-mentioned deposition method, and those skilled in the art can reasonably select the method from the prior art.
In the step of depositing the amorphous semiconductor material 40, in order to more effectively diffuse the amorphous semiconductor material 40 through the metal layer 30 and crystallize the amorphous semiconductor material 40 on the surface of the recess 102 in an epitaxial growth manner, it is more preferable that the semiconductor substrate 10 is a silicon substrate and the amorphous semiconductor material 40 is amorphous silicon. But is not limited to the above preferred species and other types of amorphous semiconductor materials 40 known in the art may be used, such as amorphous silicon germanium, amorphous silicon carbide, amorphous silicon nitride, amorphous silicon oxide, amorphous silicon oxycarbide, and the like.
The process of depositing the amorphous semiconductor material 40 may be a conventional deposition process in the prior art, and the thickness of the deposited amorphous semiconductor material 40 is reasonably set according to the depth of the recess 102 and the required thickness of the epitaxial layer 50, which is not specifically limited in the present application.
In the step of annealing the amorphous semiconductor material 40, in order to improve the crystallization efficiency and avoid the influence of an excessively high temperature on the crystallization effect and the substrate, it is more preferable to anneal the amorphous semiconductor material 40 at 300 to 500 ℃.
After the step of forming the epitaxial layer 50 in the recess 102 and in a portion of the channel via 101, a channel structure 60 is formed on the epitaxial layer 50 located in the channel via 101, as shown in fig. 6.
In a preferred embodiment, the step of forming the channel structure 60 on the epitaxial layer 50 located in the channel via 101 comprises: a functional layer 610 and a channel layer 620 are sequentially deposited and formed on the sidewall of the channel via 101, a dielectric filling layer 630 is formed in the channel via 101, and the dielectric filling layer 630 sequentially penetrates through the channel layer 620 and the functional layer 610 at the bottom of the channel via 101 and contacts with the epitaxial layer 50, so that a channel structure 60 penetrating to the substrate is obtained, as shown in fig. 6.
The step of forming the functional layer 610 may include: a charge blocking layer, an electron trapping layer, and a tunneling layer are sequentially formed on the sidewall of the trench via 101.
The material of each functional layer 610 and the channel layer 620 in the channel structure 60 can be reasonably selected by those skilled in the art according to the prior art, for example, the material of the charge blocking layer can be SiO2The charge trapping layer may be SiN and the tunneling layer may be SiO2The material of the channel layer 620 may be polysilicon. Moreover, the channel structure 60 can be formed by a deposition process that is conventional in the art, and will not be described herein.
The stacked body 20 includes a plurality of sacrificial layers 210 and a plurality of isolation layers 220 alternately stacked in a direction away from the substrate, and after the step of forming the channel structure 60 on the epitaxial layer 50 located in the channel via 101, the manufacturing method of the present disclosure further includes the steps of: the sacrificial layer 210 is replaced with a control gate structure to form a gate stack structure in which a plurality of common sources 110 penetrating to the substrate are formed, and the channel structure 60 is located between the adjacent common sources 110, as shown in fig. 7 and 8.
In a preferred embodiment, the step of forming the plurality of common sources 110 penetrating to the substrate in the gate stack structure includes: forming gate spacers 70 penetrating to the semiconductor substrate 10 in the stacked body 20, and removing the sacrificial layer 210; forming a gate structure 230 at a position corresponding to the sacrificial layer 210, as shown in fig. 7; a common source 110 is formed in the gate spacer 70 as shown in fig. 8.
Before the step of forming the common source 110 in the gate spacer 70, a doped region 80 may also be formed in the semiconductor substrate 10 in a region communicating with the gate spacer 70, as shown in fig. 7, the doped region 80 being of the opposite doping type to the semiconductor substrate 10; after the step of forming the doped region 80, a select gate dielectric layer 90 may also be formed on the doped region 80, as shown in fig. 7.
In the preferred embodiment, the gate isolation trench 70 is formed to allow the sacrificial layer 210 to have an exposed end surface, so that the sacrificial layer 210 can be wet-etched by using an etching solution from the exposed end surface to remove the sacrificial layer 210; moreover, by removing the sacrificial layer 210, a channel extending in the lateral direction can be formed at the position where the sacrificial layer 210 is removed, and the gate material can be deposited by using the channel as a deposition channel to obtain the gate structure 230, where the deposition process can be Atomic Layer Deposition (ALD); the material forming the gate structure 230 is generally a metal, and may be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
In a preferred embodiment, the step of forming the common source 110 in the gate spacer 70 comprises: etching back the gate structure 230 to form an etching back channel in communication with the gate spacer 70, as shown in FIG. 7; filling the etching-back channel and the gate isolation groove 70 with an insulating material 100, and etching the insulating material 100 in the gate isolation groove 70 to form an etching channel; a common source 110 is formed in the etched channel as shown in fig. 8.
The following will further illustrate the method for fabricating the above three-dimensional memory provided by the present disclosure with reference to examples and comparative examples.
Example 1
The embodiment provides a method for manufacturing an epitaxial layer in a three-dimensional memory, which comprises the following steps:
providing a monocrystalline silicon substrate with a stacked body on the surface, and sequentially etching the stacked body and the semiconductor substrate to form a channel through hole penetrating through the stacked body and a groove located in the semiconductor substrate, wherein the groove is communicated with the channel through hole;
and depositing a metal Ni layer with the thickness of 30nm on the inner surface of the groove, depositing amorphous silicon in the channel through hole, wherein the amorphous silicon covers the metal Ni layer and the side wall of part of the channel through hole, carrying out annealing treatment on the amorphous silicon at 300 ℃, and diffusing the amorphous silicon to the inner surface of the groove through the metal Ni layer and crystallizing to form an epitaxial layer.
Example 2
The present embodiment provides a method for manufacturing an epitaxial layer in a three-dimensional memory, which is different from embodiment 1 in that:
amorphous silicon is annealed at 400 ℃.
Example 3
The present embodiment provides a method for manufacturing an epitaxial layer in a three-dimensional memory, which is different from embodiment 1 in that:
amorphous silicon is annealed at 500 ℃.
Comparative example 1
An epitaxial layer is formed by a conventional Selective Epitaxial Growth (SEG) process in the prior art, wherein the temperature of the SEG process is 800 ℃.
The substrate having the epitaxial layer formed thereon in examples 1 to 3 and comparative example 1 was subjected to a bending test, which proved that: the semiconductor substrate in examples 1 to 3 had a bow of 336 to 369 μm, and the semiconductor substrate in comparative example 1 had a bow of 692 μm.
According to another aspect of the present disclosure, there is also provided a three-dimensional memory, as shown in fig. 8, including a semiconductor substrate 10, an epitaxial layer 50 and a channel structure 60, the semiconductor substrate 10 having thereon a gate stack structure having therein a channel via 101 penetrating to the semiconductor substrate 10, the semiconductor substrate 10 having therein a recess 102 communicating with the channel via 101, the gate stack structure including a plurality of control gate structures and a plurality of isolation layers 220 alternating in a direction away from the substrate; the epitaxial layer 50 is disposed in the groove 102 and a portion of the trench via 101, and the epitaxial layer 50 is a crystalline layer formed by solid phase epitaxial growth on the inner surface of the groove 102; the channel structure 60 is disposed on the epitaxial layer 50 in the channel via 101.
In the three-dimensional memory of the present disclosure, since the epitaxial layer 50 is a crystalline layer formed by solid phase epitaxial growth on the inner surface of the groove 102, compared with a process of forming the epitaxial layer 50 by Selective Epitaxial Growth (SEG) in the prior art, the method using solid phase epitaxy not only has a lower requirement on the cleanness of the substrate interface, but also can greatly reduce the thermal budget (thermal budget) of epitaxial growth, thereby effectively reducing the influence of an excessively high thermal budget on the curvature of the substrate.
In order to make the amorphous semiconductor material 40 more effectively diffuse to the surface of the recess 102 through the metal layer 30 in the process of forming the epitaxial layer 50, more preferably, the thickness of the metal layer 30 is 10 to 50 nm; also, preferably, the material deposited to form the metal layer 30 includes Ni and/or Co.
In the above three-dimensional memory of the present disclosure, the gate stack structure may further include a gate isolation trench 70 penetrating through the semiconductor substrate 10, and the common source 110 is disposed in the gate isolation trench 70, as shown in fig. 8.
In the above-described three-dimensional memory of the present disclosure, the channel structure 60 sequentially covers the functional layer 610 and the channel layer 620 on the sidewall of the channel via 101, and the dielectric filling layer 630 surrounded by the channel layer 620, and the functional layer 610 may include a charge blocking layer, a charge trapping layer, and a tunneling layer sequentially stacked in a direction away from the sidewall of the channel via 101.
The material of each functional layer 610 and the channel layer 620 in the channel structure 60 can be reasonably selected by those skilled in the art according to the prior art, for example, the material of the charge blocking layer can be SiO2The charge trapping layer may be SiN and the tunneling layer may be SiO2The material of the channel layer 620 may be polysilicon. Moreover, the channel structure 60 can be formed by a deposition process that is conventional in the art, and will not be described herein.
From the above description, it can be seen that the above-described embodiments of the present disclosure achieve the following technical effects:
compared with the process for forming the epitaxial layer by Selective Epitaxial Growth (SEG) in the prior art, the method adopting the solid phase epitaxy has lower requirement on the cleanness degree of the substrate interface and can also greatly reduce the thermal budget (thermal budget) of the epitaxial growth, thereby effectively reducing the influence of the overhigh thermal budget on the bending degree of the substrate.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Claims (11)
1. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
providing a semiconductor substrate with a stacked body on the surface, and sequentially etching the stacked body and the semiconductor substrate to form a channel through hole penetrating through the stacked body and a groove located in the semiconductor substrate, wherein the groove is communicated with the channel through hole;
carrying out solid phase epitaxial growth on the inner surface of the groove to form an epitaxial layer in the groove and part of the channel through hole;
and forming a channel structure on the epitaxial layer in the channel through hole.
2. The method of claim 1, wherein the step of performing solid phase epitaxial growth on the surface of the recess comprises:
depositing a metal layer on the inner surface of the groove;
depositing an amorphous semiconductor material in the channel via, the amorphous semiconductor material covering the metal layer and a portion of a sidewall of the channel via;
and annealing the amorphous semiconductor material, wherein the amorphous semiconductor material is diffused to the inner surface of the groove through the metal layer and crystallized to form the epitaxial layer.
3. The method according to claim 2, wherein the metal layer has a thickness of 10 to 50 nm.
4. The method of claim 2, wherein the metal layer comprises Ni and/or Co.
5. The method of claim 2, wherein the metal layer is deposited on the inner surface of the recess by a plasma enhanced chemical vapor deposition process.
6. The method of claim 2, wherein the semiconductor substrate is a silicon substrate and the amorphous semiconductor material is amorphous silicon.
7. The method according to claim 2, wherein the amorphous semiconductor material is annealed at 300 to 500 ℃.
8. The production method according to any one of claims 1 to 7, wherein the stack includes a plurality of sacrificial layers and a plurality of isolation layers alternately stacked in a direction away from the substrate, and after the step of forming the channel structure, the production method further includes the steps of:
and replacing the sacrificial layer into a control gate structure to form a gate stack structure, forming a plurality of common sources penetrating through the substrate in the gate stack structure, wherein the channel structure is positioned between the adjacent common sources.
9. A three-dimensional memory, comprising:
the semiconductor device comprises a semiconductor substrate, a grid stacking structure is arranged on the semiconductor substrate, a channel through hole penetrating through the grid stacking structure to the semiconductor substrate is formed in the grid stacking structure, a groove communicated with the channel through hole is formed in the semiconductor substrate, and the grid stacking structure comprises a plurality of control grid structures and a plurality of isolation layers which alternate along the direction far away from the substrate;
the epitaxial layer is arranged in the groove and part of the channel through hole, and the epitaxial layer is a crystalline layer formed by solid phase epitaxial growth on the inner surface of the groove;
and the channel structure is arranged on the epitaxial layer in the channel through hole.
10. The three-dimensional memory according to claim 9, wherein the semiconductor substrate is a silicon substrate and the crystallization layer is a polysilicon layer.
11. The three-dimensional memory according to claim 9, further comprising:
and the common source is arranged in the grid stacking structure and penetrates through the substrate, and the channel structure is positioned between the adjacent common sources.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114078781A (en) * | 2020-08-21 | 2022-02-22 | 长鑫存储技术有限公司 | Preparation method of semiconductor memory and semiconductor memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114078781A (en) * | 2020-08-21 | 2022-02-22 | 长鑫存储技术有限公司 | Preparation method of semiconductor memory and semiconductor memory |
| CN114078781B (en) * | 2020-08-21 | 2023-04-28 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor memory and semiconductor memory |
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