CN113725228B - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN113725228B CN113725228B CN202110991370.6A CN202110991370A CN113725228B CN 113725228 B CN113725228 B CN 113725228B CN 202110991370 A CN202110991370 A CN 202110991370A CN 113725228 B CN113725228 B CN 113725228B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a three-dimensional memory and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate having a stack body on a surface thereof, the stack body including sacrificial layers and isolation layers alternately stacked in a direction away from the substrate, forming a trench via penetrating to the substrate in the stack body, the trench via having a first sidewall; sequentially forming a functional layer and a channel layer which cover the first side wall, wherein the channel layer is positioned on one side of the functional layer far away from the first side wall; and forming a protective layer covering the top of the first side wall, and depositing a dielectric material in the channel through hole in an atomic layer manner to form a dielectric filling layer, wherein the channel layer and the functional layer sequentially encircle the dielectric filling layer to form a channel structure. Before the atomic layer deposition of the dielectric material, a protective layer covering the top of the first side wall is formed, so that the influence of the inhibiting gas on the top of the channel side wall in the atomic layer deposition process can be prevented through the protective layer, the channel layer and the functional layer positioned on the top of the side wall are prevented from being damaged, and the performance of the device is further ensured.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.
Background
In the current 3D NAND memory, a stacked 3D NAND memory structure is generally implemented by vertically stacking multiple layers of data storage units. In order to obtain the above-mentioned stacked 3D NAND memory structure, after forming a Channel hole (Channel hole) penetrating through the stack, it is necessary to sequentially cover a functional layer and a Channel layer on sidewalls of the Channel hole and form a dielectric filling layer in the Channel hole to obtain the Channel structure.
In the process of forming the trench structure in the trench through hole, the filling amount of the dielectric material can be adjusted according to different requirements. In many cases an Air Gap (Air Gap) will remain in the trench-through hole in its lower portion, but with the changing requirements of new architecture or other aspects, it may be desirable to make the entire trench-through hole void free.
Meanwhile, with the increasing number of stacked layers of the 3D NAND, deep hole filling is more difficult, and due to the large Aspect ratio (Aspect ratio) of the required trench through hole, an atomic layer deposition process is generally adopted to prepare a dielectric filling layer in the current deep hole filling technology, so that in order to enable the inhibiting gas (inhibiting gas) to reach the bottom of the trench through hole, the flow rate or time of the inhibiting gas needs to be increased, and even the radio frequency power (RF power) needs to be increased, so that the functional layer and the trench layer on the top of the sidewall of the trench through hole are damaged, thereby influencing the performance of the device.
Disclosure of Invention
The invention mainly aims to provide a three-dimensional memory and a manufacturing method thereof, which are used for solving the problem that the process of forming a dielectric filling layer in the three-dimensional memory in the prior art is easy to cause the influence on the performance of a device.
In order to achieve the above object, according to one aspect of the present invention, there is provided a method for manufacturing a three-dimensional memory, comprising the steps of: providing a substrate having a stack body on a surface thereof, the stack body including sacrificial layers and isolation layers alternately stacked in a direction away from the substrate, forming a trench via penetrating to the substrate in the stack body, the trench via having a first sidewall; sequentially forming a functional layer and a channel layer which cover the first side wall, wherein the channel layer is positioned on one side of the functional layer far away from the first side wall; and forming a protective layer covering the top of the first side wall, and depositing a dielectric material in the channel through hole in an atomic layer manner to form a dielectric filling layer, wherein the channel layer and the functional layer sequentially encircle the dielectric filling layer to form a channel structure.
Further, forming a protective layer covering the top of the first sidewall and atomic layer depositing a dielectric material in the trench via, comprising: step S11, forming a first protection layer covering the top of the first side wall; and S12, forming a dielectric filling layer in the channel through hole by adopting an atomic layer deposition process.
Further, the first protective layer has a thickness H 1 ，10＜H 1 ＜50nm。
Further, a chemical vapor deposition process is adopted, TEOS and O are adopted 3 As a precursor, a silicon oxide film is formed to cover the top of the first sidewall as a first protective layer.
Further, forming a protective layer covering the top of the first sidewall and atomic layer depositing a dielectric material in the trench via, comprising: step S21, forming a second protective layer covering the top of the first side wall; step S22, depositing dielectric materials in the channel through holes by adopting an atomic layer deposition process; step S23, repeating step S21 and step S23 to form a dielectric filling layer.
Further, the thickness of the second protective layer is H 2 ，0＜H 2 ＜10nm。
Further, a silicon dioxide film covering the top of the first side wall is formed by adopting a plasma enhanced chemical vapor deposition process to serve as a second protective layer.
Further, the top of the first side wall corresponds to at least five groups of sacrificial layers and isolation layers.
Further, after the step of forming the channel structure in the channel via, the manufacturing method further includes the steps of: replacing the sacrificial layer with a control gate structure to form a gate stack structure; common sources penetrating through the substrate are formed in the gate stack structure, and the channel structure is located between adjacent common sources.
According to another aspect of the present invention, there is provided a three-dimensional memory fabricated by the fabrication method described above.
By applying the technical scheme of the invention, the method for manufacturing the three-dimensional memory is provided, the stacked body with the through channel through hole is provided, the channel through hole is provided with the first side wall, then the functional layer and the channel layer which cover the first side wall are sequentially formed, the channel layer is positioned on one side of the functional layer which is far away from the first side wall, the protective layer which covers the top of the first side wall is formed, the dielectric material is deposited in the channel through hole in an atomic layer mode to form a dielectric filling layer, and the channel layer and the functional layer sequentially encircle the dielectric filling layer.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
fig. 1 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a substrate after forming a trench through-hole penetrating to a substrate in a stacked body in a method for manufacturing a three-dimensional memory according to an embodiment of the present application, where the trench through-hole has a first sidewall;
FIG. 3 is a schematic cross-sectional view of a substrate after sequentially forming a functional layer and a channel layer covering the first sidewall shown in FIG. 2, wherein the channel layer is located on a side of the functional layer remote from the first sidewall;
FIG. 4 is a schematic view showing a cross-sectional structure of a substrate after forming a first protective layer covering the top of the first sidewall shown in FIG. 3;
FIG. 5 is a schematic diagram showing a cross-sectional structure of a substrate after depositing a dielectric material on the stack and trench vias shown in FIG. 4 using an atomic layer deposition process;
FIG. 6 is a schematic view showing a cross-sectional structure of a substrate after forming a second protective layer covering the top of the first sidewall shown in FIG. 3;
FIG. 7 is a schematic diagram showing a cross-sectional structure of a substrate after depositing a dielectric material on the stack and trench vias shown in FIG. 6 using an atomic layer deposition process;
FIG. 8 is a schematic diagram showing a cross-sectional structure of a substrate after forming a dielectric fill layer in the trench via hole shown in FIG. 5 or FIG. 7, wherein the trench layer and the functional layer sequentially surround the dielectric fill layer to form a trench structure;
FIG. 9 is a schematic diagram showing a cross-sectional structure of a substrate after replacing the sacrificial layer shown in FIG. 8 with a gate structure;
fig. 10 is a schematic diagram showing a cross-sectional structure of a body after forming a common source penetrating to a substrate in the gate stack structure shown in fig. 9.
Wherein the above figures include the following reference numerals:
10. a substrate; 101. a trench through hole; 20. a stack; 210. a sacrificial layer; 220. an isolation layer; 230. a gate structure; 30. an epitaxial layer; 40. a functional layer; 50. a channel layer; 610. a first protective layer; 620. a second protective layer; 70. a dielectric filling layer; 710. a dielectric material; 80. grid isolation grooves; 90. a doped region; 100. a select gate dielectric layer; 110. an insulating material; 120. and a common source.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, with the increasing number of stacked layers of 3D NAND, deep hole filling is more difficult, and as the Aspect ratio (Aspect ratio) of the required trench through hole is large, an atomic layer deposition process is generally used to prepare a dielectric filling layer in the deep hole filling technology at present, in order to enable the suppressing gas (suppressing gas) to reach the bottom of the trench through hole, the flow rate or time of the suppressing gas needs to be increased, and even the radio frequency power (RF power) needs to be increased, which may cause the functional layer and the trench layer on the top of the sidewall of the trench through hole to be damaged, thereby affecting the device performance.
The inventors of the present invention studied to solve the above problems and have proposed a method for manufacturing a three-dimensional memory, as shown in fig. 1, comprising the steps of:
providing a substrate having a stack body on a surface thereof, the stack body including sacrificial layers and isolation layers alternately stacked in a direction away from the substrate, forming a trench via penetrating to the substrate in the stack body, the trench via having a first sidewall;
sequentially forming a functional layer and a channel layer which cover the first side wall, wherein the channel layer is positioned on one side of the functional layer far away from the first side wall;
and forming a protective layer covering the top of the first side wall, and depositing a dielectric material in the channel through hole in an atomic layer manner to form a dielectric filling layer, wherein the channel layer and the functional layer sequentially encircle the dielectric filling layer to form a channel structure.
By adopting the manufacturing method, the protective layer covering the top of the first side wall is formed before the atomic layer deposition of the dielectric material, so that the influence of gas on the top of the side wall of the channel can be prevented by the protective layer in the atomic layer deposition process, the channel layer and the functional layer positioned on the top of the side wall are prevented from being damaged, and the performance of the device is further ensured.
Exemplary embodiments of a method of fabricating a three-dimensional memory provided according to the present invention will be described in more detail below with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be appreciated that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, a substrate 10 having a stack 20 on a surface thereof is provided, the stack 20 including sacrificial layers 210 and isolation layers 220 alternately stacked in a direction away from the substrate 10, a trench via 101 penetrating to the substrate 10 is formed in the stack 20, the trench via 101 having a first sidewall, as shown in fig. 2.
The material of the substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide.
The isolation layer 220 and the sacrificial layer 210 may be formed using conventional deposition processes of the prior art, such as a chemical vapor deposition process. The number of layers of the sacrificial layer 210 and the isolation layer 220 can be set reasonably by a person skilled in the art according to actual requirements, and the types of the isolation layer 220 and the sacrificial layer 210 can be selected reasonably by a person skilled in the art according to the prior art, wherein the isolation layer 220 can be SiO 2 The sacrificial layer 210 may be SiN.
The portion of the substrate 10 located in the trench through hole 101 is a first recess, and the method of manufacturing the present invention may further include a step of forming an epitaxial layer 30 in the first recess, as shown in fig. 2.
After the step of forming the trench through-hole 101 penetrating to the substrate 10 in the stacked body 20, the functional layer 40 and the channel layer 50, which are stacked, are sequentially formed on the inner surface and the first surface of the trench through-hole 101, as shown in fig. 3.
When the channel structure to be formed is a charge trap channel structure, the step of forming the functional layer 40 may include: a stacked charge blocking layer, charge trapping layer, and tunneling layer are sequentially formed on the sidewalls of the channel via 101.
The materials of the functional layer 40 and the channel layer 50 can be reasonably selected by those skilled in the art according to the prior art, for example, the material of the charge blocking layer can be SiO 2 The material of the charge trapping layer can be SiN, and the material of the tunneling layer can be SiO 2 The material of the channel layer 50 may be polysilicon. Moreover, the functional layer 40 and the channel layer 50 may be formed by a deposition process that is conventional in the art, and will not be described in detail herein.
The portion of the substrate 10 located in the trench through-hole 101 is a first recess in which the epitaxial layer 30 may be formed, and after the step of forming the functional layer 40 and the channel layer 50, the subsequently formed dielectric filling layer 70 may be connected to the epitaxial layer 30 by opening the portion of the functional layer 40 and the channel layer 50 located at the bottom of the trench through-hole 101.
After the step of forming the functional layer 40 and the channel layer 50 covering the first sidewall, a protective layer covering the top of the first sidewall is formed, and a dielectric material 710 is deposited in the atomic layer in the channel via 101 to form the dielectric fill layer 70, and the channel layer 50 and the functional layer 40 sequentially surround the dielectric fill layer 70 to form a channel structure, as shown in fig. 4 to 8.
In the step of depositing the dielectric material 710 in the atomic layer in the trench via 101, the protective layer (the first protective layer 610 or the second protective layer 620) covering the top of the first sidewall may be removed by the suppressing gas in the atomic layer deposition process, so that the deposited dielectric material 710 covers the top of the first sidewall, as shown in fig. 5 and 7.
Preferably, the first sidewall tops correspond to at least five sets of sacrificial layers 210 and isolation layers 220. At this time, the protective layer may cover the end surfaces of at least five sets of the sacrificial layer 210 and the isolation layer 220, so that the influence of the suppression gas on the top of the channel sidewall in the atomic layer deposition process can be more effectively prevented by the protective layer.
In order to form the dielectric filling layer 70 described above in the trench via 101, the dielectric material 710 may be directly filled in the trench via 101 through one deposition process. At this time, in a preferred embodiment, a protective layer is formed to cover the top of the first sidewall and a dielectric material 710 is deposited in the channel via 101 in an atomic layer, comprising: step S11, forming a first protection layer 610 covering the top of the first sidewall, as shown in fig. 4; in step S12, a dielectric fill layer 70 is formed in the trench via 101 using an atomic layer deposition process, as shown in fig. 5 and 8.
In the preferred embodiment, since the dielectric filling layer 70 is formed by filling the dielectric material 710 in the trench through hole 101 in one deposition process, the one deposition process has a longer deposition time, and the more so, in order to avoid the influence of the suppression gas on the top of the first sidewall of the trench through hole 101 in the atomic layer deposition processPreferably, the thickness of the first protective layer 610 is H 1 ，10＜H 1 ＜50nm。
In the above preferred embodiment, a chemical vapor deposition process may be employed with TEOS and O 3 As a precursor, a silicon oxide film covering the top of the first sidewall is formed as the first protective layer 610. The deposition process has excellent deposition efficiency and higher film compactness.
In order to form the dielectric fill layer 70 described above in the trench via 101, the trench via 101 may also be filled with a dielectric material 710 through a multiple deposition process. At this time, in another preferred embodiment, a protective layer is formed to cover the top of the first sidewall and a dielectric material 710 is deposited in the channel via 101 in an atomic layer, comprising: step S21, forming a second protection layer 620 covering the top of the first sidewall, as shown in fig. 6; step S22, depositing a dielectric material 710 in the trench via 101 using an atomic layer deposition process, as shown in fig. 7; step S23, step S21 and step S23 are repeatedly performed to form the dielectric filling layer 70, as shown in fig. 8.
In the preferred embodiment, since the dielectric filling layer 70 is formed by filling the dielectric material 710 into the trench through hole 101 in a plurality of deposition processes, the one deposition process can have a shorter deposition time, and more preferably, the second protective layer 620 has a thickness H in order to avoid the influence of the suppressing gas on the top of the first sidewall of the trench through hole 101 in the atomic layer deposition process 2 ，0＜H 2 ＜10nm。
In the above preferred embodiment, a silicon oxide film covering the top of the first sidewall may be formed as the second protective layer 620 using a plasma enhanced chemical vapor deposition process. The deposition process has excellent deposition efficiency and higher film compactness.
After the step of forming the channel structure in the channel via 101, the above-described fabrication method of the present invention may further include the steps of: the functional layer 40 and the channel layer 50 located on the first surface are removed. The step of removing the functional layer 40 and the channel layer 50 on the first surface may be performed before the step of forming the dielectric filling layer 70, or may be performed after the step of forming the dielectric filling layer 70, together with the dielectric material 710 on the first surface, which is not particularly limited in the present invention.
After the step of forming the channel structure in the channel via 101, the above-described fabrication method of the present invention may further include the steps of: replacement of the sacrificial layer 210 with the gate structure 230 to form a gate stack structure, as shown in fig. 9; common sources 120 penetrating to the substrate 10 are formed in the gate stack structure, and the channel structure is located between adjacent common sources 120, as shown in fig. 10.
In a preferred embodiment, the step of replacing the sacrificial layer 210 with the gate structure 230 includes: forming a gate spacer 80 penetrating to the substrate 10 in the stack 20, and removing the sacrificial layer 210; a gate structure 230 is formed at a position corresponding to the sacrificial layer 210.
In the preferred embodiment, the gate spacer 80 is formed, so that the sacrificial layer 210 can have an exposed end surface, and thus the sacrificial layer 210 can be wet etched by using an etching solution from the exposed end surface, so as to remove the sacrificial layer 210; and, by removing the sacrificial layer 210, a channel extending from the lateral direction can be formed at a position where the sacrificial layer 210 is removed, and a gate material is deposited using the channel as a deposition channel to obtain a gate structure 230, and the deposition process may be Atomic Layer Deposition (ALD); the material forming the gate structure 230 is typically metal, and may be selected from one or more of W, al, cu, ti, ag, au, pt and Ni.
After the step of forming the gate spacer 80 penetrating to the substrate 10 in the stack 20, a doped region 90 may be formed in the substrate 10 in communication with the gate spacer 80, the doped region 90 being of an opposite doping type to the substrate 10; after the step of forming the doped region 90, a select gate dielectric layer 100 may also be formed on the doped region 90, as shown in fig. 9.
In a preferred embodiment, after the step of forming gate spacers 80 in the stack 20 through to the substrate 10, the gate structure 230 is etched back to form an etched back channel in communication with the gate spacers 80, as shown in fig. 9; filling insulating material 110 in the etch-back channel and the gate spacer 80, etching the insulating material 110 in the gate spacer 80 to form an etched channel; a common source 120 is formed in the etched channel as shown in fig. 10.
According to another aspect of the present invention, there is also provided a three-dimensional memory, as shown in fig. 10, which is manufactured by the above manufacturing method.
From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:
before the atomic layer deposition of the dielectric material, a protective layer covering the top of the first side wall is formed, so that the influence of the inhibiting gas on the top of the channel side wall in the atomic layer deposition process can be prevented through the protective layer, the channel layer and the functional layer positioned on the top of the side wall are prevented from being damaged, and the performance of the device is further ensured.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The manufacturing method of the three-dimensional memory is characterized by comprising the following steps of:
providing a substrate having a stack body on a surface thereof, the stack body including sacrificial layers and isolation layers alternately stacked in a direction away from the substrate, forming a channel via hole penetrating to the substrate in the stack body, the channel via hole having a first sidewall;
sequentially forming a functional layer and a channel layer which cover the first side wall, wherein the channel layer is positioned on one side of the functional layer away from the first side wall;
and forming a protective layer covering the top of the first side wall, and depositing a dielectric material in the channel through hole in an atomic layer manner to form a dielectric filling layer, wherein the channel layer and the functional layer sequentially encircle the dielectric filling layer to form a channel structure.
2. The method of claim 1, wherein forming a protective layer overlying the top of the first sidewall and atomic layer depositing a dielectric material in the trench via comprises:
step S11, forming a first protection layer covering the top of the first side wall;
and step S12, forming the dielectric filling layer in the channel through hole by adopting an atomic layer deposition process.
3. The method of claim 2, wherein the first protective layer has a thickness of H 1 ，10＜H 1 ＜50nm。
4. The method of claim 2, wherein the chemical vapor deposition process is performed with TEOS and O 3 And forming a silicon dioxide film covering the top of the first side wall as the first protective layer for the precursor.
5. The method of claim 1, wherein forming a protective layer overlying the top of the first sidewall and atomic layer depositing a dielectric material in the trench via comprises:
step S21, forming a second protective layer covering the top of the first side wall;
step S22, depositing dielectric materials in the channel through holes by adopting an atomic layer deposition process;
and step S23, repeatedly executing the step S21 and the step S23 to form the dielectric filling layer.
6. The method of claim 5, wherein the second protective layer has a thickness H 2 ，0＜H 2 ＜10nm。
7. The method of claim 5, wherein a silicon dioxide film is formed to cover the top of the first sidewall by a plasma enhanced chemical vapor deposition process as the second protective layer.
8. The method of any one of claims 1 to 7, wherein the first sidewall top corresponds to at least five sets of the sacrificial layer and the spacer layer.
9. The manufacturing method according to any one of claims 1 to 7, characterized in that after the step of forming the channel structure in the channel via hole, the manufacturing method further comprises the step of:
replacing the sacrificial layer with a control gate structure to form a gate stack structure;
common sources penetrating through to the substrate are formed in the gate stack structure, and the channel structure is located between adjacent common sources.
10. A three-dimensional memory fabricated by the fabrication method of any one of claims 1 to 9.
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| CN112992910A (en) * | 2021-03-24 | 2021-06-18 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN113161363A (en) * | 2021-03-31 | 2021-07-23 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
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