CN112289805A - Manufacturing method of groove structure, three-dimensional NAND memory and manufacturing method thereof - Google Patents
Manufacturing method of groove structure, three-dimensional NAND memory and manufacturing method thereof Download PDFInfo
- Publication number
- CN112289805A CN112289805A CN202011182410.4A CN202011182410A CN112289805A CN 112289805 A CN112289805 A CN 112289805A CN 202011182410 A CN202011182410 A CN 202011182410A CN 112289805 A CN112289805 A CN 112289805A
- Authority
- CN
- China
- Prior art keywords
- mask layer
- hole
- layer
- etching
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a manufacturing method of a groove structure, a three-dimensional NAND memory and a manufacturing method of the three-dimensional NAND memory. The manufacturing method comprises the following steps: sequentially forming a first mask layer and a second mask layer which are stacked on one side of the stacked body far away from the substrate; etching the second mask layer and the first mask layer to form a first through hole, wherein the part of the first through hole, which is positioned in the first mask layer, is a first through hole section, the part of the first through hole, which is positioned in the second mask layer, is a second through hole section, one end of the first through hole section is communicated with the stacked body, and the other end of the first through hole section is communicated with the second through hole section; etching the first mask layer through the first through hole section to enable the first through hole section to expand transversely to form a third through hole section so as to form a second through hole; and etching the stacked body by using the processed first mask layer and the processed second mask layer to form a third through hole, wherein the third through hole penetrates through the substrate. The method reduces the difficulty of filling the material in the second through hole by increasing the size of the top of the second through hole.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a groove structure, a three-dimensional NAND memory and a manufacturing method of the three-dimensional NAND memory.
Background
In the prior art, a Flash Memory (Flash Memory) has a main function of maintaining stored information for a long time without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, so that the Flash Memory is widely applied to electronic products. In order to further improve the Bit Density (Bit Density) of the flash memory and at the same time reduce the Bit Cost (Bit Cost), a 3D NAND memory is further proposed.
In the current 3D NAND memory, a stacked 3D NAND memory structure is generally implemented by vertically stacking multiple layers of data storage units. In order to obtain the stacked 3D NAND memory structure, a stacked structure is formed on a silicon substrate, a trench via is formed by etching the stacked structure, a trench structure covering the inner wall of the trench via is further deposited and etched, and then a semiconductor layer is filled to form a memory structure in the trench via.
Along with the gradual increase of the number of layers of the vertical stack, the thickness accuracy and the uniformity of the stack structure are difficult to ensure, the etching difficulty of the channel through hole with the high depth-to-width ratio is gradually improved, the bottom and the top of the channel through hole are easy to cause to be smaller than the size of the middle part, so that the difficulty of material filling in the channel through hole is increased, the filled material is easy to cause to be blocked at the top, the middle part of the channel through hole is easy to have an unfilled area, and the influence of a device is influenced.
Disclosure of Invention
The invention mainly aims to provide a manufacturing method of a groove structure, a three-dimensional NAND memory and a manufacturing method of the three-dimensional NAND memory, and aims to solve the problem that the etching process of the groove structure in the prior art easily causes material filling difficulty.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method for manufacturing a groove structure, including the steps of: s1, providing a substrate with a stacked body on the surface, and sequentially forming a first mask layer and a second mask layer which are stacked on one side of the stacked body far away from the substrate; s2, etching the second mask layer and the first mask layer to form a first through hole, wherein the part of the first through hole, which is located in the first mask layer, is a first through hole section, the part of the first through hole, which is located in the second mask layer, is a second through hole section, one end of the first through hole section is communicated with the stacked body, and the other end of the first through hole section is communicated with the second through hole section; s3, etching the first mask layer through the first through hole section to enable the first through hole section to expand transversely to form a third through hole section so as to enable the first through hole to form a second through hole; and S4, etching the stacked body by using the first mask layer and the second mask layer processed in the steps S2 and S3 to form a third through hole, wherein the third through hole penetrates through the substrate.
Further, after the step of forming the second mask layer and before the step of etching the second mask layer and the first mask layer, the step S2 further includes the steps of: and forming a third mask layer on the surface of the second mask layer, wherein the third mask layer is preferably formed from SiON.
Further, in step S3, the first mask layer is wet etched or gas etched using the second mask layer with the second via segment as a mask to laterally expand the first via segment.
Further, wet etching is performed on the first mask layer by using etching liquid, wherein the first mask layer is silicon dioxide, and the etching liquid is hydrofluoric acid.
Further, etching gas is adopted to perform gas etching on the first mask layer, the first mask layer is silicon dioxide, and the etching gas comprises fluorine-containing gas.
Further, the etching gas is tetrafluoroethylene.
Furthermore, the depth of the first through hole section in the transverse extension is 50-200 nm.
According to another aspect of the present invention, there is provided a method for manufacturing a three-dimensional NAND memory, comprising the steps of: providing a substrate with a stacked body on the surface, wherein the stacked body comprises a sacrificial layer and an isolation layer which are alternately stacked along the direction far away from the substrate, and forming a channel through hole in the stacked body by adopting the manufacturing method; forming a storage structure in the trench via; the sacrificial layer is replaced with a gate structure such that the gate structure is in contact with the memory structure.
Further, the step of forming the memory structure includes: and sequentially forming a charge blocking layer, a charge trapping layer, a tunneling layer and a channel layer which are stacked on the side wall of the channel through hole, wherein the charge blocking layer, the charge trapping layer, the tunneling layer and the channel layer form a storage structure.
Further, the step of replacing the sacrificial layer with a gate structure comprises: forming grid isolation grooves penetrating to the substrate in the stacked body, and removing the sacrificial layer; forming a grid structure at the position corresponding to the sacrificial layer; a conductive channel is formed in the gate spacer.
According to another aspect of the present invention, there is also provided a three-dimensional NAND memory, comprising: the device comprises a substrate, a first substrate and a second substrate, wherein one side surface of the substrate is provided with a stacked body, and a channel through hole penetrating to the substrate is formed in the stacked body; and the storage structure is arranged in the channel through hole, wherein the channel through hole is formed by adopting the manufacturing method.
The invention provides a manufacturing method of a groove structure, which comprises the steps of firstly providing a substrate with a stacked body on the surface, sequentially forming a first mask layer and a second mask layer which are stacked on one side of the stacked body far away from the substrate, and forming a first through hole which sequentially penetrates through the second mask layer and the first mask layer, wherein the first through hole is provided with a first through hole section and a second through hole section, the first through hole section is positioned in the first mask layer and penetrates to the stacked body, the second through hole section is positioned in the second mask layer and is communicated with the first through hole section, then transversely expanding the first through hole section to form a third through hole section, so that when the stacked body close to the stacked body is etched through the first mask layer, the second through hole section which is taken as a hollow part in the first mask layer has a larger cross-sectional area, the size of the top of the third through hole formed by the stacked body in the subsequent etching can be favorably expanded, and then through the size at increase third through hole top, reduced the degree of difficulty that the material was filled in the third through hole.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional structure diagram of a stacked body after a first mask layer and a second mask layer are sequentially formed on a side of the stacked body away from a substrate in a method for manufacturing a groove structure provided in an embodiment of the present application;
fig. 2 shows a schematic cross-sectional structure of the stack after forming a first via sequentially penetrating the second mask layer and the first mask layer shown in fig. 1, wherein the first via has a first via segment and a second via segment;
FIG. 3 shows a schematic cross-sectional structure view of the stack after laterally expanding the first via segment shown in FIG. 2 to form a third via segment;
fig. 4 is a schematic cross-sectional structure view of the stacked body after etching the stacked body to form a groove structure having a third via hole, using the first mask layer and the second mask layer processed in steps S2 and S3 shown in fig. 3 as masks;
FIG. 5 shows a schematic cross-sectional view of the stack after depositing a functional layer material on the substrate shown in FIG. 4 such that at least a portion of the functional layer material is located in the trench via;
figure 6 shows a schematic cross-sectional view of the stack after planarization of the deposited functional layer material of figure 5 to form a memory structure in the trench via.
Wherein the figures include the following reference numerals:
10. a substrate; 20. a stack; 210. a sacrificial layer; 220. an isolation layer; 30. a first mask layer; 40. a second mask layer; 50. patterning the photoresist; 60. a first through hole; 601. a second through hole; 610. a first via section; 620. a second via section; 630. a third through-hole section; 70. a third through hole; 80. a storage structure; 810. a functional layer material; 90. and a third mask layer.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As introduced in the background art, in the current 3D NAND memory, with the gradual increase of the number of vertical stacking layers, it is difficult to ensure the thickness accuracy and uniformity of the stacking structure, and the difficulty of etching the high aspect ratio trench via is gradually increased, which easily causes the bottom and top of the trench via to be smaller than the middle, thereby increasing the difficulty of filling the material in the trench via, easily causing the filled material to be blocked at the top, thereby causing the unfilled region in the middle of the trench via, and affecting the influence of the device.
The inventor of the present invention has studied the above problems and proposed a method for manufacturing a groove structure, comprising the steps of: s1, providing a substrate with a stacked body on the surface, and sequentially forming a first mask layer and a second mask layer which are stacked on one side of the stacked body far away from the substrate; s2, etching the second mask layer and the first mask layer to form a first through hole, wherein the part of the first through hole, which is located in the first mask layer, is a first through hole section, the part of the first through hole, which is located in the second mask layer, is a second through hole section, one end of the first through hole section is communicated with the stacked body, and the other end of the first through hole section is communicated with the second through hole section; s3, etching the first mask layer through the first through hole section to enable the first through hole section to expand transversely to form a third through hole section so as to enable the first through hole to form a second through hole; and S4, etching the stacked body by using the first mask layer and the second mask layer processed in the steps S2 and S3 to form a third through hole, wherein the third through hole penetrates through the substrate.
By adopting the manufacturing method, the size of the second through hole section close to the stacked body is enlarged, so that when the stacked body below is etched through the first mask layer, the second through hole section serving as the hollow part in the first mask layer has a larger cross section area, the enlargement of the size of the top of the second through hole formed by subsequently etching the stacked body can be facilitated, and the difficulty of material filling in the second through hole is reduced by enlarging the size of the top of the second through hole.
An exemplary embodiment of a method of fabricating a recess structure provided according to the present invention will be described in more detail below with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, step S1 is executed: a substrate 10 having a stacked body on a surface thereof is provided, and a stacked first mask layer 30 and a stacked second mask layer 40 are sequentially formed on a side of the stacked body away from the substrate 10, as shown in fig. 1.
The material of the substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In the present embodiment, the semiconductor substrate 10 is a P-type Si substrate 10.
The method for manufacturing a recess structure according to the present invention may be used in manufacturing processes of different semiconductor devices, where the semiconductor device may be a three-dimensional NAND memory, and at this time, the stack 20 in step S1 may be formed by stacking the sacrificial layer 210 and the isolation layer 220, as shown in fig. 1, a trench via located in the stack 20 is formed by the method for manufacturing a recess structure according to the present invention, a storage structure is formed in the trench via, and the sacrificial layer needs to be removed in a subsequent manufacturing process, and a gate structure in contact with the storage structure is formed in a region where the sacrificial layer is removed.
In the above step S1, the isolation layer 220 and the sacrificial layer 210 can be formed by a conventional deposition process in the prior art, such as a chemical vapor deposition process. The number of the sacrificial layer 210 and the isolation layer 220 can be set by those skilled in the art according to practical requirements, and the isolation layer 220 can be SiO2The sacrificial layer 210 may be SiN, but is not limited to the above type, and those skilled in the art can reasonably select the types of the isolation layer 220 and the sacrificial layer 210 according to the prior art.
The first mask layer 30 and the second mask layer 40 may also be formed by a conventional deposition process, such as a chemical vapor deposition process. In order to realize the subsequent lateral extension of the first via segment 610, the materials of the first mask layer 30 and the second mask layer 40 are different, and those skilled in the art can reasonably select the materials of the first mask layer 30 and the second mask layer 40 according to the prior art. For example, the material forming the first mask layer 30 may be SiO2The material forming the second mask layer 40 may be carbon (C) or aluminum oxide (Al)2O3)。
After the step of forming the first mask layer 30 and the second mask layer 40, step S2 is performed: the second mask layer 40 and the first mask layer 30 are etched to form a first via hole 60, a portion of the first via hole 60 located in the first mask layer 30 is a first via section 610, a portion of the first via hole 60 located in the second mask layer 40 is a second via section 620, one end of the first via section 610 communicates with the stacked body, and the other end of the first via section 610 communicates with the second via section 620, as shown in fig. 2.
In order to form the first via 60 sequentially penetrating through the second mask layer 40 and the first mask layer 30, in step S2, a layer of photoresist may be firstly covered on a side of the second mask layer 40 away from the first mask layer 30, a pattern in the mask may be transferred into the photoresist through a photolithography process, and then the second mask layer 40 and the first mask layer 30 may be sequentially etched using the patterned photoresist 50 as a mask to obtain the first via 60, where the photolithography process is preferably a dry etching process.
When the material of the second mask layer 40 is C, since the etching selection ratio of the photoresist material to C is small, the difficulty of etching is easily high, at this time, before the step of covering the photoresist, the third mask layer 90 may be deposited on the surface of the second mask layer 40, and a material having a larger etching selection ratio to the photoresist, such as SiON, is preferably used.
After the step of forming the first through hole 60 described above, step S3 is performed: the first mask layer 30 is etched through the first via segment 610, such that the first via segment 610 in the first via 60 is laterally expanded to form a third via segment 630, so as to form a second via 601 from the first via, as shown in fig. 3.
In order to laterally expand the first via segment 610, it is preferable that in step S3, the first mask layer 30 is wet-etched or gas-etched using the second mask layer 40 with the second via segment 620 as a mask to laterally expand the first via segment 610.
In a preferred embodiment, the first mask layer is wet etched with an etching solution, and the first mask layer is SiO2And the etching liquid is hydrofluoric acid.
In another preferred embodiment, the first mask layer is etched by gas using an etching gas, and the first mask layer 30 is SiO2And the etching gas comprises fluorine-containing gas, more preferably C2F4。
In order to ensure that the third via section 630 can make the top of the subsequently formed third via 70 have a sufficiently large size, the first via section 610 is preferably laterally expanded to a depth a of 50-200 nm in the above step S3, as shown in fig. 3, by laterally expanding the region of the first via 60 close to the stack into the third via section 630, which facilitates the enlargement of the size of the top of the third via 70 formed by the subsequent etching of the stack, and thus facilitates the enlargement of the size of the top of the third via 70.
After the step of forming the third through-hole section 630 described above, step S4 is performed: the stack 20 is etched using the first and second mask layers 30 and 40 processed through steps S2 and S3 to form a third via 70, and the third via 70 penetrates through the substrate 10, as shown in fig. 4.
In the step S4, the third through hole 70 may be formed by using a dry etching process, and those skilled in the art can reasonably set the process conditions of the dry etching process according to the prior art, which is not described herein again.
After the step of forming the third via 70, the manufacturing method of the present invention may further include a step of removing the second mask layer 40, and optionally, may further remove the first mask layer 30, and a person skilled in the art may reasonably select an etching process according to the specific types of the first mask layer 30 and the second mask layer 40. It is noted that the first masking layer 30 may be removed together with the second masking layer 40, may be removed after the formation of the storage structure 80 in the third via 70, or may remain on the stack.
According to another aspect of the present invention, there is also provided a method for manufacturing a three-dimensional NAND memory, as shown in fig. 1 to 6, including the following steps: providing a substrate 10 with a stacked body 20 on the surface, wherein the stacked body 20 comprises a sacrificial layer 210 and an isolation layer 220 which are alternately stacked along the direction far away from the substrate 10, and forming a channel through hole (namely, a third through hole 70) in the stacked body 20 by adopting the manufacturing method of the groove structure; forming a memory structure 80 in the trench via; sacrificial layer 210 is replaced with a gate structure such that the gate structure is in contact with memory structure 80.
In the manufacturing method of the three-dimensional NAND memory, the channel through hole is formed by adopting the manufacturing method of the groove structure, and the enlargement of the size of the second through hole section close to the stacked body is beneficial to the enlargement of the size of the top of the channel through hole formed by the subsequent etching of the stacked body, so that the difficulty of material filling in the channel through hole is reduced by enlarging the size of the top of the channel through hole, the formation of a storage structure in the channel through hole is ensured, and the performance of a device is further ensured.
The step of forming the memory structure 80 in the trench via may include: depositing a functional layer material 810 on the substrate 10 such that at least a portion of the functional layer material 810 is located in the trench via, as shown in fig. 5; the functional layer material 810 outside the trench via is then removed by a planarization process such that the remaining functional layer material 810 constitutes the memory structure 80, as shown in fig. 6.
The memory structure 80 may be a charge trap type memory structure, and in this case, the step of forming the memory structure 80 includes: and sequentially forming a charge blocking layer, a charge trapping layer, a tunneling layer and a channel layer which are stacked on the side wall of the channel through hole, wherein the charge blocking layer covers the side wall of the channel through hole. The memory structure may further include a fill oxide layer overlying an inner surface of the channel layer. The above-mentioned filling oxide layer is usually SiO2The channel layer may be deposited using an Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process in order to cover the channel layer.
It is understood that the embodiment of the present application takes the fabrication of the through hole (the third through hole 70) on the substrate as an example, but the fabrication method of the groove structure provided in the embodiment of the present application does not limit the applied scenario. The manufacturing method of the groove structure provided by the embodiment of the application can also be applied to manufacturing other groove or through hole structures, such as contact holes and the like.
The material of each functional layer in the memory structure 80 can be reasonably selected by one skilled in the art according to the prior art, for example, the material of the charge blocking layer can be SiO2The charge trapping layer may be SiN and the tunneling layer may be SiO2The material of the channel layer may be polysilicon. Moreover, the memory structure 80 can be formed by a deposition process that is conventional in the art, and will not be described in detail herein.
The step of replacing the sacrificial layer 210 with a gate structure includes: forming gate spacers penetrating to the substrate in the stacked body 20, and removing the sacrificial layer 210; forming a gate structure at a position corresponding to the sacrificial layer 210; a conductive channel is formed in the gate spacer.
According to another aspect of the present invention, there is also provided a three-dimensional NAND memory, as shown in fig. 6, which includes a substrate 10 and a storage structure 80, wherein one side surface of the substrate 10 has a stacked body, the stacked body has a trench via penetrating through to the substrate, and the storage structure is disposed in the trench via, wherein the trench via is formed by using the above-mentioned method for forming a recess structure.
In the three-dimensional NAND memory, the channel through hole is formed by the groove structure manufacturing method, and the enlargement of the size of the second through hole section close to the stacked body is beneficial to the enlargement of the size of the top of the channel through hole formed by the subsequent etching of the stacked body, so that the difficulty of material filling in the channel through hole is reduced by enlarging the size of the top of the channel through hole, the formation of a storage structure in the channel through hole is ensured, and the performance of a device is further ensured.
In the three-dimensional NAND memory of the present invention, the memory structure 80 may be a charge trap type memory structure, and specifically, may include a charge blocking layer, a charge trapping layer, a tunneling layer and a channel layer sequentially stacked on a sidewall of the trench via, and the memory structure 80 may further include a filling oxide layer covering an inner surface of the channel layer. The above-mentioned filling oxide layer is usually SiO2The purpose is to cover the channel layer.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
1. by enlarging the size of the second through hole section close to the stacked body, when the stacked body below is etched through the first mask layer, the second through hole section serving as the hollow part in the first mask layer has a larger cross section area, so that the enlargement of the size of the top of a third through hole formed by subsequently etching the stacked body can be facilitated, and the difficulty of material filling in the third through hole is reduced by increasing the size of the top of the third through hole;
2. the manufacturing method of the groove structure is applied to the manufacturing method of the three-dimensional NAND memory, and the difficulty of filling materials in the channel through hole is reduced by increasing the size of the top of the channel through hole, so that the formation of a storage structure in the channel through hole is ensured, and the performance of a device is further ensured.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. The manufacturing method of the groove structure is characterized by comprising the following steps of:
s1, providing a substrate with a stacked body on the surface, and sequentially forming a first mask layer and a second mask layer which are stacked on one side of the stacked body far away from the substrate;
s2, etching the second mask layer and the first mask layer to form a first through hole, wherein the part of the first through hole, which is located in the first mask layer, is a first through hole section, the part of the first through hole, which is located in the second mask layer, is a second through hole section, one end of the first through hole section is communicated with the stacked body, and the other end of the first through hole section is communicated with the second through hole section;
s3, etching the first mask layer through the first through hole section to enable the first through hole section to expand transversely to form a third through hole section so as to enable the first through hole to form a second through hole;
and S4, etching the stacked body by using the first mask layer and the second mask layer processed in the steps S2 and S3 to form a third through hole, wherein the third through hole penetrates through the substrate.
2. The method of claim 1, wherein after the step of forming the second mask layer and before the step of etching the second mask layer and the first mask layer, the step S2 further comprises the steps of:
and forming a third mask layer on the surface of the second mask layer.
3. The method of claim 1, wherein in the step S3, the first mask layer is wet etched or gas etched using the second mask layer with the second via segment as a mask to laterally expand the first via segment.
4. The manufacturing method according to claim 3, wherein the wet etching is performed on the first mask layer by using an etching solution, the first mask layer is silicon dioxide, and the etching solution is hydrofluoric acid.
5. The method of claim 3, wherein the first mask layer is subjected to the gas etching using an etching gas, the first mask layer being silicon dioxide, the etching gas comprising a fluorine-containing gas.
6. The method of claim 5, wherein the etching gas is tetrafluoroethylene.
7. The method of any one of claims 1 to 6, wherein the first via segment is laterally extended to a depth of 50 to 200 nm.
8. A manufacturing method of a three-dimensional NAND memory is characterized by comprising the following steps:
providing a substrate having a stack on a surface thereof, the stack including a sacrificial layer and an isolation layer alternately stacked in a direction away from the substrate, forming a channel via in the stack using the manufacturing method of any one of claims 1 to 7;
forming a storage structure in the trench via;
and replacing the sacrificial layer into a gate structure so that the gate structure is in contact with the storage structure.
9. The method of claim 8, wherein the step of forming the memory structure comprises:
and sequentially forming a charge blocking layer, a charge trapping layer, a tunneling layer and a channel layer which are stacked on the side wall of the channel through hole, wherein the charge blocking layer, the charge trapping layer, the tunneling layer and the channel layer form the storage structure.
10. The method of claim 8, wherein the step of replacing the sacrificial layer with a gate structure comprises:
forming gate spacers penetrating to the substrate in the stacked body, and removing the sacrificial layer;
forming a grid structure at a position corresponding to the sacrificial layer;
a conductive channel is formed in the gate spacer.
11. A three-dimensional NAND memory, the memory comprising:
a substrate having a stacked body on one side surface thereof, the stacked body having a channel via hole penetrating therethrough to the substrate;
a memory structure disposed in the trench via,
wherein the trench via is formed by the manufacturing method of any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011182410.4A CN112289805A (en) | 2020-10-29 | 2020-10-29 | Manufacturing method of groove structure, three-dimensional NAND memory and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011182410.4A CN112289805A (en) | 2020-10-29 | 2020-10-29 | Manufacturing method of groove structure, three-dimensional NAND memory and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112289805A true CN112289805A (en) | 2021-01-29 |
Family
ID=74352466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011182410.4A Pending CN112289805A (en) | 2020-10-29 | 2020-10-29 | Manufacturing method of groove structure, three-dimensional NAND memory and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112289805A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024077728A1 (en) * | 2022-10-11 | 2024-04-18 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, and semiconductor structure |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130109158A1 (en) * | 2011-10-31 | 2013-05-02 | Jinkwan Lee | Methods of Fabricating Semiconductor Devices Using Mask Shrinking |
| CN104425228A (en) * | 2013-08-28 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming polysilicon grid electrode |
| CN110494971A (en) * | 2019-06-27 | 2019-11-22 | 长江存储科技有限责任公司 | Interconnection structure and forming method thereof |
| CN110571219A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | semiconductor device, manufacturing method thereof and mask plate |
| CN111192850A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method for manufacturing isolation structure |
| CN111540752A (en) * | 2020-05-14 | 2020-08-14 | 长江存储科技有限责任公司 | 3D NAND memory and forming method thereof |
| CN111599819A (en) * | 2020-05-29 | 2020-08-28 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN111785725A (en) * | 2020-07-15 | 2020-10-16 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory |
-
2020
- 2020-10-29 CN CN202011182410.4A patent/CN112289805A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130109158A1 (en) * | 2011-10-31 | 2013-05-02 | Jinkwan Lee | Methods of Fabricating Semiconductor Devices Using Mask Shrinking |
| CN104425228A (en) * | 2013-08-28 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming polysilicon grid electrode |
| CN110571219A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | semiconductor device, manufacturing method thereof and mask plate |
| CN111192850A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method for manufacturing isolation structure |
| CN110494971A (en) * | 2019-06-27 | 2019-11-22 | 长江存储科技有限责任公司 | Interconnection structure and forming method thereof |
| CN111540752A (en) * | 2020-05-14 | 2020-08-14 | 长江存储科技有限责任公司 | 3D NAND memory and forming method thereof |
| CN111599819A (en) * | 2020-05-29 | 2020-08-28 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN111785725A (en) * | 2020-07-15 | 2020-10-16 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory |
Non-Patent Citations (2)
| Title |
|---|
| 奥列格•库侬楚克，阮碧艳 著: "《绝缘体上硅（SOI）技术 制造及应用》", 30 September 2018 * |
| 田民波，刘德令编译: "《薄膜科学与技术手册 上》", 31 March 1991 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024077728A1 (en) * | 2022-10-11 | 2024-04-18 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, and semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9786681B1 (en) | Multilevel memory stack structure employing stacks of a support pedestal structure and a support pillar structure | |
| US9853043B2 (en) | Method of making a multilevel memory stack structure using a cavity containing a sacrificial fill material | |
| US9443866B1 (en) | Mid-tunneling dielectric band gap modification for enhanced data retention in a three-dimensional semiconductor device | |
| US9530785B1 (en) | Three-dimensional memory devices having a single layer channel and methods of making thereof | |
| CN109755252B (en) | Memory device and manufacturing method thereof | |
| CN110600422B (en) | 3D NAND flash memory and preparation method thereof | |
| US11751395B2 (en) | Vertical semiconductor device and method for fabricating the vertical semiconductor device | |
| WO2020040835A1 (en) | Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same | |
| EP2455967B1 (en) | A method for forming a buried dielectric layer underneath a semiconductor fin | |
| CN109935547B (en) | 3D NAND memory device and manufacturing method thereof | |
| CN112614846B (en) | Manufacturing method of channel hole, memory and manufacturing method of memory | |
| CN112289805A (en) | Manufacturing method of groove structure, three-dimensional NAND memory and manufacturing method thereof | |
| CN111199875B (en) | Preparation method of graphical hard mask layer, capacitor array structure and preparation method thereof | |
| CN111599819A (en) | Three-dimensional memory and manufacturing method thereof | |
| CN111244098A (en) | Three-dimensional memory and preparation method thereof | |
| CN112992910B (en) | Three-dimensional memory and preparation method thereof | |
| CN111863826B (en) | Manufacturing method of graphical mask and manufacturing method of three-dimensional NAND memory | |
| WO2021203886A1 (en) | Semiconductor structure and method for manufacturing same | |
| CN110797346A (en) | Three-dimensional memory and manufacturing method thereof | |
| CN111463218A (en) | 3D NAND memory device and manufacturing method thereof | |
| CN112786612A (en) | Three-dimensional memory and manufacturing method thereof | |
| CN113725228B (en) | Three-dimensional memory and manufacturing method thereof | |
| CN112909014A (en) | Three-dimensional memory and manufacturing method thereof | |
| WO2023029036A1 (en) | Three-dimensional memory and manufacturing method therefor | |
| CN108447869B (en) | Memory structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210129 |