CN110571219A - semiconductor device, manufacturing method thereof and mask plate - Google Patents
semiconductor device, manufacturing method thereof and mask plate Download PDFInfo
- Publication number
- CN110571219A CN110571219A CN201810577992.2A CN201810577992A CN110571219A CN 110571219 A CN110571219 A CN 110571219A CN 201810577992 A CN201810577992 A CN 201810577992A CN 110571219 A CN110571219 A CN 110571219A
- Authority
- CN
- China
- Prior art keywords
- gate
- layer
- grid
- region
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 114
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 239000010410 layer Substances 0.000 claims abstract description 314
- 238000005530 etching Methods 0.000 claims abstract description 78
- 239000012792 core layer Substances 0.000 claims abstract description 39
- 239000011241 protective layer Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 55
- 239000000758 substrate Substances 0.000 claims description 48
- 230000008569 process Effects 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 40
- 239000011229 interlayer Substances 0.000 claims description 34
- 230000015654 memory Effects 0.000 claims description 21
- 239000005368 silicate glass Substances 0.000 claims description 18
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 12
- 238000004380 ashing Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 229920000620 organic polymer Polymers 0.000 claims description 6
- BTBUEUYNUDRHOZ-UHFFFAOYSA-N Borate Chemical compound [O-]B([O-])[O-] BTBUEUYNUDRHOZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910019142 PO4 Inorganic materials 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 5
- 230000036961 partial effect Effects 0.000 claims description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 claims description 5
- 239000010452 phosphate Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 21
- 230000002829 reductive effect Effects 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 238000011068 loading method Methods 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 238000009826 distribution Methods 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000002861 polymer material Substances 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000002159 nanocrystal Substances 0.000 description 2
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000001642 boronic acid derivatives Chemical group 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910000423 chromium oxide Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- RTZKZFJDLAIYFH-UHFFFAOYSA-N ether Substances CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005365 phosphate glass Substances 0.000 description 1
- -1 poly (arylene ether Chemical compound 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a semiconductor device and a manufacturing method and a mask plate thereof, wherein the manufacturing method of the semiconductor device forms a side wall on the side wall of a core after a patterned core layer with the core is formed in a grid dense area and a grid sparse area, so that when a grid layer is etched by taking the side wall as a mask, the etching load effect between the grid dense area and the grid sparse area can be reduced or even completely avoided, the uniformity of the key size of a finally formed first grid is improved, and the shape of the first grid at the edge is ensured; and after the grid layer is etched by taking the side wall as a mask, the bottom of the grid layer is kept connected, then the grid layer in the corresponding area of the second grid in the grid sparse area is protected by a protective layer, the grid layer is further etched to form a first grid in the grid dense area, and second grids are formed in the grid sparse area, wherein each second grid is provided with a base structure and a plurality of separated structures which are arranged on the base structure and are mutually spaced.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor device, a manufacturing method thereof and a mask plate.
Background
At present, with the rapid development of very large scale integrated circuits, the integration level of chips is higher and higher, the circuit design size is smaller and smaller, and the influence of various effects caused by the high density and small size of devices on the semiconductor manufacturing result is more and more prominent, especially in the process below the 28nm technology node, the influence of the change of the Critical Dimension (CD) of the circuit on the device performance is larger and larger.
It is well known that the fabrication of a gate is one of the most critical steps in the fabrication of semiconductor devices, since the gate typically has the smallest physical dimension in a semiconductor fabrication process, and the width of the gate is typically the most important critical dimension on a wafer. However, in most regions of the wafer surface, in order to realize the overall function of the device, these regions include regions with very Dense gates, i.e. regions with high device density, which we refer to as Dense regions (density, abbreviated as D); and includes the region with sparser gate, i.e. lower device density, which we refer to as the sparse region (ISO, abbreviated as I).
In practice, when the gates of the dense region and the sparse region are formed in the same etching process, due to the difference in gate density between the two regions, there is an etching difference (I/D loading, or sparse/dense loading effect) in the Critical Dimension (CD) of the gates in the two regions, and under the influence of the I/D loading, the gate at the edge of the dense region often generates an abnormality in profile and depth, and the abnormal edge gate adversely affects the gate in the middle of the dense region and the gate of the sparse region, thereby affecting the performance of the device. For example, in a NAND flash memory, distribution densities of select gates (SG, i.e., sparse gates) and word lines (word lines, WL, corresponding to control gates, i.e., dense gates) are different, and a distance between a select gate and a nearest word line is greater than a distance between two adjacent word lines, as a critical dimension of the NAND flash memory is increasingly reduced, an increasingly severe etching load effect is generated between the word lines and the select gate, so that critical dimension uniformity (CD uniformity) of the word lines is reduced, and multiple word lines at edges (i.e., multiple word lines close to the select gate) tend to generate profile and depth anomalies, thereby affecting performance of the device.
disclosure of Invention
the invention aims to provide a semiconductor device, a manufacturing method thereof and a mask plate, which can improve the uniformity of the key size of a grid in a grid dense area, ensure the shape of an edge grid in the grid dense area and improve the performance of the device.
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate having a gate dense region and a gate sparse region, sequentially forming a gate layer and a patterned core layer on the surface of the semiconductor substrate, the patterned core layer having a plurality of mutually spaced cores located on the gate dense region and a plurality of mutually spaced cores located on the gate sparse region;
Forming a side wall on the side wall of the core;
removing the patterned core layer, etching the gate layer by taking the side wall as a mask, and stopping etching in the gate layer to form a gate groove;
Forming a protective layer for shielding the grid groove in the area corresponding to the second grid to be formed;
And continuously etching the gate layer to the surface of the semiconductor substrate along the gate trench exposed by the protective layer to form a first gate and a second gate, wherein the second gate comprises a base structure and a plurality of separated structures which are arranged on the base structure and are spaced from each other.
Optionally, the material of the patterned core layer comprises at least one of borate silicate glass, borophosphate silicate glass, phosphate silicate glass, ashed removable dielectric, low-K dielectric, heat removable organic polymer, polysilicon, amorphous silicon, and amorphous carbon.
Optionally, the plurality of cores corresponding to the second gate next to the gate dense region and the plurality of cores on the gate dense region are distributed with equal line width and equal interval.
Optionally, a hard mask layer is further formed between the gate layer and the patterned core layer, and the hard mask layer is of a single-layer structure or a stacked-layer structure; the step of etching the gate layer by using the side wall as a mask comprises the following steps:
patterning the hard mask by using the side wall as a mask through an etching process;
and removing the side wall, etching the gate layer by taking the patterned hard mask layer as a mask, and stopping etching in the gate layer to form a gate groove.
Optionally, after the gate trench is formed and before the protective layer is formed, performing back etching on the patterned hard mask layer, further etching the gate layer in a direction towards the semiconductor substrate while thinning the patterned hard mask layer, and keeping the bottom of the gate layer connected; and after continuously etching the gate layer to the surface of the semiconductor substrate along the gate trench exposed by the protective layer, removing the hard mask layer and the protective layer.
Optionally, the protective layer is filled in the gate trench in the region corresponding to the second gate to be formed and covers the surface of the hard mask layer in the region corresponding to the second gate to be formed.
Optionally, after the forming the first gate and the second gate, the method further includes:
Covering the surfaces of the semiconductor substrate, the first gates and the second gates with an interlayer dielectric layer, wherein the interlayer dielectric layer at least fills the intervals among the adjacent discrete structures, the adjacent first gates, the adjacent second gates and the first gates and the second gates in each second gate;
and carrying out back etching on the interlayer dielectric layer to enable the top surface of the interlayer dielectric layer to be lower than the top surface of the discrete structure.
Optionally, after performing the back etching on the interlayer dielectric layer, the method for manufacturing the semiconductor device further includes: and forming a connecting pad for electrically connecting the tops of the discrete structures in the second grid electrode, wherein the connecting pad covers the surface of the interlayer dielectric layer between the adjacent discrete structures in the second grid electrode and the surface of the discrete structure above the interlayer dielectric layer.
Optionally, the semiconductor device is a floating gate type memory, and the gate layer includes a floating gate layer, an inter-gate dielectric layer, and a control gate layer sequentially stacked on the surface of the semiconductor substrate; etching the gate layer by taking the side wall as a mask, and stopping etching the gate layer on the floating gate layer; the grid electrode dense region is a word line region, the grid electrode sparse region is a selection grid region, the formed first grid electrode is a word line, the formed second grid electrode is a selection grid, and the base structure of the selection grid is a floating grid layer with partial thickness or full thickness.
the present invention also provides a semiconductor device comprising:
A semiconductor substrate having a gate dense region and a gate sparse region;
A plurality of first gates distributed on the gate dense region of the semiconductor substrate;
a plurality of second gates distributed over the gate thinning-out region of the semiconductor substrate, each of the second gates having a base structure and a plurality of spaced apart discrete structures on the base structure.
Optionally, the plurality of discrete structures of the second gate next to the gate dense region and the plurality of first gates on the gate dense region are distributed with equal line width and equal interval.
optionally, the semiconductor device is a floating gate type memory, and the gate layer includes a floating gate layer, an inter-gate dielectric layer, and a control gate layer sequentially stacked on the surface of the semiconductor substrate; the grid electrode dense region is a word line region, the grid electrode sparse region is a selection grid region, the second grid electrode is a selection grid, the first grid electrode is a word line, and the base structure of the selection grid is a floating grid layer with partial thickness or full thickness.
Optionally, the semiconductor device further includes: and the interlayer dielectric layers are filled between the adjacent discrete structures in each second grid electrode, between the adjacent first grid electrodes, between the adjacent second grid electrodes and in the intervals between the first grid electrodes and the second grid electrodes.
Optionally, in the semiconductor device, the top surface of the interlayer dielectric layer is lower than the top surface of the discrete structure, the semiconductor device further includes a connection pad for electrically connecting the top portions of the discrete structures in the second gate, and the connection pad covers the surface of the interlayer dielectric layer between adjacent discrete structures in the second gate and the surface of the discrete structure above the interlayer dielectric layer.
the invention also provides a mask plate for forming the patterned core layer in the manufacturing method of the semiconductor device, or for manufacturing the first grid and the second grid in the semiconductor device.
Optionally, when the semiconductor device is a floating gate memory, the mask is a word line mask. .
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. According to the manufacturing method of the semiconductor device, the patterned core layer with the core in the grid dense area and the core in the grid sparse area is formed on the surface of the grid layer, then the side wall is formed on the side wall of the core, the density distribution difference of the mask patterns for etching the grid layer in the grid sparse area and the grid dense area is reduced, further, when the grid layer is etched by taking the side wall as the mask, the etching load effect between the grid dense area and the grid sparse area can be reduced or even completely avoided, the uniformity of the key size of the first grid formed in the grid dense area finally is improved, the shape of the first grid at the edge is ensured, and the performance of the device is improved; and when the side walls are used as masks to etch the gate layer, the etching is stopped in the gate layer so as to connect the bottom of the gate layer and separate the top of the gate layer, then the bottom connected gate layer in the area corresponding to the second gate in the gate sparse area is protected by the protective layer, and the bottoms of the gate layers in other areas including the gate dense area are completely separated, so that the first gate is formed in the gate dense area, the second gate is formed in the gate sparse area, and each second gate is provided with a base structure and a plurality of separated structures which are positioned on the base structure and are mutually spaced.
2. The semiconductor device provided by the invention is provided with a plurality of first gates distributed on the gate dense region of the semiconductor substrate and a plurality of second gates distributed on the gate sparse region of the semiconductor substrate, each second gate is provided with a base structure and a plurality of separated structures which are arranged on the base structure and are spaced from each other, the uniformity of the critical dimension of the first gates in the gate dense region is higher, and the shape of the first gates close to the edges of the second gates is better, so that the device performance can be improved.
3. The mask plate can be used for manufacturing a semiconductor device with a sparse second grid and a dense first grid, can improve the uniformity of the key size of the formed first grid, ensures the shape of the first grid at the edge and improves the performance of the device.
Drawings
fig. 1A to 1E are schematic cross-sectional views illustrating a method of manufacturing a NAND flash memory device;
FIG. 1F is a transmission electron microscope image of a NAND flash memory device structure;
Fig. 2 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 3A to 3E are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
The adverse effects of the sparse/dense loading effect of the gate on the device performance will be described in detail below by taking a NAND flash memory device as an example. As shown in fig. 1E, a NAND flash memory device may include: a select gate (SG, i.e., a gate of a select transistor whose source or drain is connected to a bit line) 103b and a plurality of Word Lines (WL)103a, SL 103b, (BL), WL103a formed by connecting together control gates (ControlGate, CG) of memory cells on the same active region are arranged outside the select gate SG103b, the SG, WL being arranged in parallel, and a respective charge storage structure may be provided between each WL103a and each active region (ACT) to provide a respective memory cell at each intersection of the WL and the active region (ACT). Generally, SG103b is distributed relatively sparsely, WL103a is distributed relatively densely, each WL103a has substantially the same line width and is distributed uniformly and equally spaced (space), while the line width of SG103b is generally larger than the line width of WL103a, the spacing (space) between two adjacent SG103b is much larger than the spacing between two adjacent WL103a, for example, at least 3 times, and the spacing between SG103b and its adjacent WL103a is generally slightly larger than the spacing between two adjacent WL103a, so that the region where SG103b is located is generally referred to as an ISO region (i.e., a gate sparse region) and the region where WL103a is located is a Dense region (i.e., a gate Dense region).
referring to fig. 1A to 1E, a manufacturing process of the NAND flash memory device includes the following steps:
first, referring to fig. 1A, a Floating Gate (FG) layer 101, an ONO (silicon oxide-silicon nitride-silicon oxide) layer 102, a Control Gate (CG) layer 103, a hard mask layer 104, and a patterned core layer (core)105 for defining each word line are sequentially formed on a semiconductor substrate 100 having a word line region (i.e., a gate dense region) WL and a select gate region (i.e., a gate sparse region) SG, and a sidewall 106 is formed on a sidewall of the patterned core layer 105, wherein the hard mask layer 104 is a stacked structure including a PEOX (enhanced oxide) layer, an ACL (amorphous carbon), and an Etch Stopper (ESL) sequentially covering the control gate layer 103, the patterned core layer 105 is formed by a word line lithography process (CG patterning), the sidewall 106 is formed by a self-aligned double patterning process (self aligned double patterning), a line width of the sidewall 106 is equal to a line width of the word line to be formed, the spacing between adjacent side walls 106 is equal to the spacing of word lines to be formed;
then, referring to fig. 1B, the patterned core layer 105 is removed, and a patterned photoresist layer (PR)107 for defining each select gate is formed on the surface of the hard mask layer 104 through a corresponding photolithography process;
Then, referring to fig. 1B and fig. 1C, with the sidewall 106 and the patterned photoresist layer 107 as masks, the hard mask layer 104 and the control gate layer 103 are sequentially etched until the surface of the ONO layer 102, at this time, the double pattern formed by the sidewall 106 and the patterned photoresist layer 107 is transferred into the control gate layer 103, the remaining control gate layer forms a word line 103a (i.e., a control gate) in the word line region WL, and a select gate 103B in the select gate region SG;
then, referring to fig. 1B to fig. 1D, the patterned photoresist layer 107 and the sidewall 106 are removed, and a certain etch back (HM etch back) is performed on the hard mask layer 104, in which the etch back process thins the hard mask layer 104, opens the ONO layer 102, then etches the floating gate layer 101 with the remaining hard mask layer, the word line 103a, and the select gate 103B as masks, and the etching is stopped on the surface of the semiconductor substrate 100, thereby forming each memory cell (including the word line 103a, the ONO 102, and the floating gate 101a), the floating gate 101a under the control gate 103a, and the floating gate 101B under the select gate 103B.
Referring to fig. 1E, an interlayer dielectric layer 108 is deposited on the surfaces of the semiconductor substrate 300, the word line 103a, the select gate 103b, the ONO 102 and the floating gates 101a and 101b, and the interlayer dielectric layer 108 is etched back to have a top surface lower than the top surface of the word line 103 a.
In the manufacturing process of the NAND flash memory device, because the formed sidewall 106 and the patterned photoresist layer 107 have different line widths and different distribution densities, and thus may generate a sparse/dense loading effect (I/D loading), when the word line 103a and the select gate 103b are formed by etching the control gate layer 103 using the sidewall 106 and the patterned photoresist layer 107 as masks, under the influence of the sparse/dense loading effect, the uniformity of the critical dimension of the word line 103a (i.e., the control gate) in the word line region WL is poor, and the edge word line 103a adjacent to the select gate region SG (i.e., the edge word line shown by the dashed line box in fig. 1F) may generate an abnormal profile and depth, for example, the word line corresponding to the dashed line box shown in fig. 1F is relatively thin and small and the top is relatively recessed, thereby affecting the performance of the device.
based on this, the invention provides a semiconductor device, a manufacturing method thereof and a mask plate, the core idea is that while forming a plurality of cores on a grid dense region, a plurality of cores are also formed on a grid sparse region, the line width of the cores on the grid sparse region is smaller and the distribution density is larger than the line width of the patterned photoresist layer (such as the patterned photoresist layer 107 in fig. 1C) used for forming the second grid, for example, the core distribution density corresponding to the same second grid is equal to the line width and the distribution density of the cores in the grid dense region, so as to reduce the sparse/dense load effect of the mask pattern used for forming the first grid in the grid dense region and the grid sparse region, further reduce or even completely avoid the etching load effect generated between the grid dense region and the grid dense region when etching the grid layer, and improve the uniformity of the key size of the finally formed first grid, the abnormal shape of the first grid at the edge of the grid dense area is avoided, and the performance of the device is improved. And when the side wall is used as a mask to etch the grid layer, the etching is stopped in the grid layer so as to connect the bottom of the grid layer and separate the top of the grid layer to form a grid groove, then a protective layer for shielding the grid groove in the area corresponding to the second grid to be formed is used for protecting the connected grid layer below the grid groove in the area corresponding to the second grid to be formed in the grid sparse area, and the grid layer in other areas including the grid dense area is completely separated, so that a first grid is formed in the grid dense area, a second grid is formed in the grid sparse area, and the second grid comprises a base structure and a plurality of separated structures which are positioned on the base structure and are mutually spaced. The technical scheme of the invention is suitable for manufacturing any semiconductor device with different grid distribution densities, in particular to the manufacturing of floating grid type memories such as NAND flash memories and the like.
The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
Referring to fig. 2, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:
S1, providing a semiconductor substrate having a gate dense region and a gate sparse region, sequentially forming a gate layer and a patterned core layer on the surface of the semiconductor substrate, the patterned core layer having a plurality of mutually spaced cores located on the gate dense region and a plurality of mutually spaced cores located on the gate sparse region;
S2, forming a side wall on the side wall of the core;
s3, removing the patterned core layer, etching the gate layer by taking the side wall as a mask, and stopping etching in the gate layer to form a gate groove;
S4, forming a protective layer for shielding the gate trench in the region corresponding to the second gate to be formed;
And S5, continuing to etch the gate layer to the surface of the semiconductor substrate along the gate trench exposed by the protective layer to form a first gate and a second gate, wherein the second gate comprises a base structure and a plurality of spaced discrete structures on the base structure.
The following describes a method for manufacturing a semiconductor device according to the present invention in detail with reference to fig. 3A to 3E, taking the manufacturing of a NAND flash memory as an example. The grid dense region, i.e. the word line region WL, is used for manufacturing a word line (i.e. a control grid and a first grid), and the grid sparse region, i.e. the selection grid region SG, is used for manufacturing a selection grid (i.e. a second grid).
Referring to fig. 3A, in step S1, the semiconductor substrate 300 is provided to provide a platform for subsequent processes, and may be formed of any semiconductor material known to those skilled in the art, such as silicon, silicon germanium, or the like, which may be bulk silicon (bulk) or silicon-on-insulator (SOI), and the semiconductor substrate 300 may have well, active region (ACT), isolation structure, and the like formed therein. The semiconductor substrate 300 has a word line region WL (i.e., a gate dense region) for a word line (i.e., a control gate, a first gate) of a NAND to be formed and a select gate region SG (i.e., a gate sparse region) for a select gate (i.e., a second gate) of the NAND to be formed. In this embodiment, in order to fabricate a NAND flash memory, a gate layer and a hard mask layer 304 are sequentially formed on a surface of a semiconductor substrate 300, the gate layer includes a gate oxide layer (GOX, not shown), a floating gate layer (FG)301, an inter-gate dielectric layer 302, and a control gate layer (CG)303, which are sequentially stacked on the surface of the semiconductor substrate 300, the gate oxide layer may be formed by a thermal oxidation process or a chemical vapor deposition process, the floating gate layer 301 and the inter-gate dielectric layer 302 constitute a charge storage layer, a storage function is realized under control of a control gate (i.e., a word line) formed in the subsequent control gate layer 303, the floating gate layer 301 is used to fabricate a floating gate, a material of which may be polysilicon, metal nanocrystals, silicon germanium nanocrystals, or other suitable conductive materials, and is formed by a chemical vapor deposition process, the inter-gate dielectric layer 302 may be a silicon oxide-silicon nitride-silicon oxide (ONO, the ONO stacked structure may be formed by sequentially depositing a silicon dioxide layer, a silicon nitride layer, and a silicon dioxide layer on the surface of the floating gate layer 301 through a chemical vapor deposition process, however, the inter-gate dielectric layer 302 may also be other suitable materials, such as a single layer structure of silicon oxide, silicon nitride, or silicon oxynitride, or a structure including stacking two or more layers of silicon oxide, silicon nitride, or silicon oxynitride, and the control gate layer 303 may be undoped polysilicon, doped polysilicon, a metal silicide, polysilicon combined with a metal silicide, or other suitable materials, and may be formed through a chemical vapor deposition process. The hard mask layer (HM)304 may be a stacked structure, for example, including a mask dielectric layer, an advanced patterning film layer (APF), and an etch stop layer, which are sequentially stacked from bottom to top, the mask dielectric layer may include at least one of a plasma enhanced oxide layer (PEOX), silicon nitride, and silicon oxynitride, and may be formed using Plasma Enhanced Chemical Vapor Deposition (PECVD), the APF layer may be amorphous silicon (α -si) and/or Amorphous Carbon (ACL), and the like, and may be formed by a chemical vapor deposition process or a spin coating process, the mask dielectric layer and the APF layer may be used to reduce reflection of light used in exposing an overlying photoresist, to provide a high etch selectivity and a low Line Edge Roughness (LER), and to provide a flat surface. The etching barrier layer is used for providing an etching stop point when the patterned core layer and the side wall are formed and protecting the lower lamination layer, and the material of the etching barrier layer can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or other suitable materials.
with continued reference to fig. 3A, in step S1, a patterned core layer may be formed on the surface of the semiconductor substrate 300 by a new control gate mask (CG mask) and corresponding coating/deposition, photolithography/etching processes, etc., the patterned core layer has a plurality of mutually spaced cores 305a in the word line region WL, the number of cores 305a is equal to half of the number of word lines, and a plurality of mutually spaced cores 305b in the select gate region SG, the number of cores 305b depends on the line width of the select gate to be formed, and the line width of each core may be equal to the spacing between two adjacent word lines (i.e., D11 ═ D21). In this embodiment, a plurality of cores 305b corresponding to a select gate to be formed next to a word line region WL and cores 305a in the word line region WL are distributed with equal intervals and equal line widths, and among these cores, the intervals D12, D22 between two adjacent cores are equal to the line widths of two word lines plus the space between the two word lines (i.e., D12 ═ D22 ═ 2 ═ D13+ D11), that is, the intervals between two adjacent cores in the word line region WL can form two adjacent word lines, and in addition, the material of the patterned core layer is different from the etching barrier layer in the hard mask layer 304 and the subsequently formed side walls 306a, 306b, and has a higher etching selectivity than the etching barrier layer and the side walls 306a, 306b, and the material of the patterned core layer is, for example, Borate Silicate Glass (BSG), borophosphate silicate glass (BPSG), and phosphate glass (PSG), Ashing Removable Dielectric (ARD) materials, low K dielectric materials (dielectric constant K below 2.9), heat removable organic polymer materials, polysilicon, amorphous silicon, amorphous carbon, and the like. In fig. 3A, in order to provide a significant contrast effect with fig. 1A, the cores 305a and 305b are distinguished by different filling colors, which does not mean that the cores 305a and 305b are formed by two mask processes, nor that the cores 305a and 305b are made of different materials, in order to highlight the innovative point of the present invention. Further, in the present embodiment, the plurality of cores 305b for forming a select gate next to the word line region WL and the plurality of cores 305a on the word line region WL are distributed with equal line width and equal interval, but the technical solution of the present invention is not limited thereto, as long as the line width of the plurality of cores 305b for forming a select gate next to the word line region WL is smaller and the distribution density is larger than the patterned photoresist layer 107 in fig. 1A, and therefore, in other embodiments of the present invention, the line widths of the cores 305a and 305b may be different (i.e., D11 ≠ D21), the distance D22 between the two most adjacent cores 305b may not be equal to the distance D12 between the two adjacent cores 305a, because the line width D21 of the cores 305b is only smaller than the line width of the patterned photoresist layer 107 in fig. 1C and the distribution density on the select gate region is larger (i.e., the number is larger), the sparse/dense loading effect between the word line region WL and the select gate region SG can be reduced, and the uniformity of the critical dimension of the subsequently and finally formed word line can be improved.
referring to fig. 3A and 3B, in step S2, the sidewalls 306a and 306B may be formed by a self aligned double patterning (self aligned double patterning) process. Specifically, first, a sidewall material may be deposited on the surfaces of the patterned core layers (i.e., the cores 305a and 305b) and the uncovered etching blocking layer, where the deposited sidewall material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, may be of a single-layer structure, or may be of a stacked structure with two or more layers, and a thickness of the sidewall material on the sidewalls of the cores 305a and 305b is greater than or equal to a line width of a word line (i.e., a first gate) to be formed; and then, etching the deposited side wall material, stopping etching on the surface of the etching barrier layer, and after the etching is finished, only reserving part of the side wall material on the core side wall of the patterned core layer to form side walls 306a and 306b, wherein the line width D13 of the side wall 306a is equal to the line width of a word line to be formed, and the distance D11 between the adjacent side walls 306a is equal to the distance between the word lines to be formed.
Referring to fig. 3B, in step S3, the patterned core layer may be removed (i.e., removing the cores 305a and 305B) by selecting a suitable process according to the material characteristics of the patterned core layer, the patterned core layer may be removed by an ashing process when the patterned core layer is an Ashing Removable Dielectric (ARD) material, the patterned core layer may be decomposed and removed by heating, for example, to 200 ℃ or higher when the patterned core layer is a heating removable organic polymer material, and the patterned core layer may be removed by a dry etching process or a wet etching process when the patterned core layer is Borate Silicate Glass (BSG), borophosphate silicate glass (BPSG), Phosphate Silicate Glass (PSG), low K dielectric material (dielectric constant K is lower than 2.9), polysilicon, amorphous silicon, amorphous carbon, or the like. It should be noted that, in order to form a significant contrast effect with fig. 1A and 1B in fig. 3A and 3B, the innovative point of the present invention is highlighted by using different filling colors to distinguish the sidewalls 306a and 306B, which does not mean that the sidewalls 306a and 306B are formed by different processes, nor that the sidewalls 306a and 306B are made of different materials.
referring to fig. 3B and 3C, in step S3, the hard mask layer 304 may be etched (i.e., etching the etching stop layer, the APF layer, the PEOX, and other mask dielectric layers therein in sequence) by using the sidewalls 306a and 306B as masks, and then the hard mask layer 304 is opened, and the double pattern formed by the sidewalls 306a and 306B is transferred into the hard mask layer 304, thereby forming the patterned hard mask layer 304a with word line patterns (word line patterns). Then, the spacers 306a and 306b may be removed by a suitable process, such as dry etching, wet etching, Chemical Mechanical Planarization (CMP), and the like, so as to avoid the difficulty of the high aspect ratio etching process generated when the spacers 306a and 306b subsequently etch the control gate layer 303 and avoid the additional etching residues generated when the materials of the spacers 306a and 306b subsequently etch the control gate layer 303. Then, the control gate layer 303 is etched by using the patterned hard mask layer 304a as a mask, the etching is stopped on the surface of the ONO layer 302 to form a gate trench 308, and the remaining control gate layer 303a on the word line region WL is separated and used as a word line (i.e. a control gate, a first gate), the remaining control gate layer 303a on the selection gate region SG is used to combine with the subsequent floating gate layer 301 adjacent to the bottom to form a selection gate (i.e. a second gate), since the pattern in the patterned hard mask layer 304a is derived from the double pattern of the combination of the side walls 306a and 306b without abnormal sparse/dense loading effect (i.e. etching difference exceeding the process requirement), the word line obtained by etching the control gate layer 303 by using the patterned hard mask layer 304a as a mask has no abnormal etching loading effect (i.e. etching difference exceeding the process requirement), the profile and depth of the edge word line (i.e., the word line near the select gate region SG) are both satisfactory.
With continued reference to fig. 3B and 3C, in step S3, a certain back Etching (HM Etching back) may be performed on the patterned hard mask layer 304a to reduce the thickness of the patterned hard mask layer 304, so as to reduce the aspect ratio of the subsequent Etching process, on the one hand, the remaining patterned hard mask layer 304a may protect the top of the underlying control gate layer 303a and the like from being damaged, and the back Etching process may open the inter-gate dielectric layer 302(Etching through ONOlayer) and perform a certain Etching on the floating gate layer 301, that is, the gate trench 308 is deeper into the floating gate layer 301 by a certain depth. When the etch-back process of the patterned hard mask layer 304a is finished, the top of the floating gate layer 301 is in a structure which is separated from the control gates 303a in a one-to-one correspondence manner, and the bottom of the floating gate layer 301 is also kept in a structure which is connected integrally, that is, the floating gate layer 301 at this time is in a comb structure, the top of the floating gate layer 301 is equivalent to comb teeth which are separated from each other, and the bottom of the floating gate layer 301 is equivalent to a comb back which connects the comb teeth together.
referring to fig. 3C and 3D, in step S4, first, a deposition process or a coating process may be used to cover the semiconductor substrate 300, the gate trenches, and the surfaces of all the remaining hard mask layers 304a with a protective material such as photoresist, and the protective material at least fills all the gate trenches (i.e., fills the gaps between the gate layers above the floating gate layer 301); next, with the use of a selective gate mask (SG mask), the covered protection material is patterned through a photolithography process, an etching process, and the like to form a patterned protection layer 307, where the protection layer 307 can shield the gate trenches 308 in the region corresponding to each second gate to be formed in the selective gate SL, and expose all the gate trenches in other regions. In this embodiment, the protection layer 307 also extends to cover the top surface of the patterned hard mask layer 304a in the region corresponding to each second gate to be formed in the select gate region SL. In other embodiments of the present invention, the material of the protection layer 307 may further include silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon (α -si), Amorphous Carbon (ACL), Ashed Removable Dielectric (ARD) material, low-K dielectric material (dielectric constant K less than 2.9), heat removable organic polymer material, undoped silicon dioxide based material layer (e.g., silicon dioxide), doped silicon dioxide based material (e.g., fluorinated silicon oxide FSG), organosilicate glass (e.g., borate silicate glass BSG, borophosphate silicate glass BPSG, phosphate silicate glass PSG), porous silicate glass layer, silicon nitride based material, silicon oxynitride based material, silicon carbide based material, low-K dielectric material layer (dielectric constant K less than 2.9), polyimide, organosilicone polymer, poly (arylene ether), titanium dioxide, titanium nitride, titanium oxide, titanium oxynitride, At least one of chromium oxide and an anti-reflective coating (e.g., bottom anti-reflective layer BARC). The protection layer 307 may be a single layer structure or a multi-layer structure, for example, in an embodiment of the present invention, the protection layer 307 includes a patterned photoresist layer and a cap layer located between the patterned photoresist layer and the patterned hard mask layer 304a, the patterned photoresist layer is formed by a photoresist coating, exposing, developing and other photolithography processes (SG Photo), the cap layer may include a material that absorbs or reflects radiation, such as a dielectric anti-reflection layer (DARC), a bottom anti-reflection layer (BARC), amorphous carbon (α -carbon), silicon carbide, titanium nitride (TiN), silicon nitride (SiN), silicon oxynitride (SiON) or a metal coating, when a material used to form the patterned photoresist layer is exposed to a certain wavelength of light radiation (used to generate a high resolution pattern in the photoresist), the cap layer may reduce reflected light and reduce the formation of standing wave patterns in the patterned photoresist layer as the patterned photoresist layer is formed, protecting the underlying stack from optical radiation as the patterned photoresist layer is formed.
Referring to fig. 3D and fig. 3E, in step S5, first, the protection layer 308 and the patterned hard mask layer 304a exposed by the protection layer are used as masks, and the floating gate layer 301(FG etch) at the bottom of the exposed gate trench 308 is etched, and the etching is stopped on the surface of the gate oxide layer or the surface of the semiconductor substrate 300. Since the protective layer 307 is formed by a select gate Mask (SG PH Mask) before etching the floating gate layer 301, this time of floating gate etching process can make the bottom of the floating gate layer 301b in the region corresponding to the select gate remain connected, the bottom of the floating gate layer 301a in the word line region WL is separated, and the floating gate layer in the region between two adjacent select gates is removed, i.e. at this time, the bottom of the floating gate layer 301a in the word line region WL is a completely separated structure (i.e. the bottom is not connected), while the bottom of the floating gate layer 301b in the select gate region SL for forming the same select gate is connected and the top is separated and spaced, thereby forming the word line and the select gate, the select gate includes a base structure (i.e. the floating gate layer 301b whose bottom is connected as a whole) and a plurality of separated structures (i.e. a plurality of separated control gate layers 303a) on the base structure, the word line includes a control gate layer 303 a. And the control gate layer 303a in the word line region WL and the inter-gate dielectric layer 302 and the floating gate layer 301a thereunder constitute one memory cell. Because the side walls 306a and 306b have no abnormal sparse/dense loading effect, the word line formed by etching the gate layer has no abnormal sparse/dense loading effect, and the structure of the edge word line meets the requirements, so that the finally formed profile and depth of each memory cell are basically consistent, and especially the structure (including the profile and the depth) of the edge memory cell on the word line region WL can meet the device manufacturing requirements.
after that, an appropriate process may be selected according to the material of the protection layer 307, and when the protection layer 307 is an Ashing Removable Dielectric (ARD) material, the ashing process may be used to remove the ashing material, when the protection layer 307 is a heating removable organic polymer material, the patterned core layer may be decomposed and removed by heating, for example, to 200 ℃ or higher, and when the protection layer 307 is Borate Silicate Glass (BSG), borophosphate silicate glass (BPSG), Phosphate Silicate Glass (PSG), low K dielectric material (dielectric constant K is lower than 2.9), amorphous silicon, amorphous carbon, or the like, the ashing process may be used to remove the ashing material by a dry etching process or a wet etching process.
Optionally, after the first gate electrode and the second gate electrode are formed, an interlayer dielectric layer and a connection pad for electrically connecting the tops of all the discrete structures (control gate layers) in the select gate may be further formed, and the method specifically includes:
First, an interlayer dielectric layer (not shown) is covered on the surfaces of the semiconductor substrate 300, the word lines and the selection gates, and the interlayer dielectric layer at least fills the space between the adjacent discrete structures in each selection gate, the space between the adjacent word lines, the space between the adjacent selection gates and the space between the word lines and the selection gates (i.e. all the exposed gate trenches 308 after the protective layer is removed);
Then, performing back etching on the interlayer dielectric layer to enable the top surface of the interlayer dielectric layer to be lower than the top surface of the control gate layer 303 a;
Then, a connection material (not shown) such as polysilicon is deposited on the surfaces of the interlayer dielectric layer, the word lines and the select gates, and the connection material on the regions other than the select gates is removed through a connection pad mask (GT pad mask), and the connection material is remained only on the region of each select gate to form connection pads (not shown) for connecting the tops of the control gate layers 303a (i.e., the tops of the discrete structures) in each select gate, wherein the connection pads fill the portions of the gate trenches between the adjacent discrete structures of each select gate above the interlayer dielectric layer and cover the top surfaces of the discrete structures of the select gate.
It should be noted that the NAND flash memory can be finally manufactured by the above-mentioned method for manufacturing a semiconductor device, and when the method for manufacturing a semiconductor device of the present invention is applied to manufacture other semiconductor devices, in step S1, a gate dielectric layer (which may be an OX layer or an ONO layer) and a gate layer with a single-layer structure may be formed on the surface 300 of the semiconductor substrate, and the etching stop point in each subsequent step is adjusted accordingly. Of course, in the embodiments of the present invention, the stacked structure of the hard mask layer 304 formed in step S1 may be increased or decreased as appropriate, or may even be a single-layer structure, the stacked structure of the protective layer 307 in step S4 may also be increased or decreased as appropriate, or may even be a single-layer structure, and the etching stop point in the subsequent steps is adjusted accordingly, which is not limited to the above examples.
In summary, in the manufacturing method of the semiconductor device of the present invention, the core layer with core patterns in the gate dense region and the gate sparse region is formed on the surface of the gate layer, and then the sidewall is formed on the sidewall of each core, so that the density difference (i.e., pattern loading effect) of the mask patterns for subsequently etching the gate layer in the gate sparse region and the gate dense region is reduced, and further, when the gate layer is etched by using the sidewall as a mask, the etching load effect (etch loading effect) between the gate dense region and the gate sparse region can be reduced or even completely avoided, the uniformity of the critical dimension of the first gate formed in the gate dense region is improved, the shape of the first gate at the edge is ensured, and the device performance is improved; and when the side walls are used as masks to etch the gate layer, the etching is stopped in the gate layer so as to connect the bottom of the gate layer and separate the top of the gate layer, then the bottom of the gate layer connected in the region corresponding to the second gate in the gate sparse region is protected by the protective layer, and the bottoms of the gate layer in other regions including the gate dense region are completely separated, so that the first gate is formed in the gate dense region, the second gate is formed in the gate sparse region, and each second gate is provided with a base structure and a plurality of separated structures which are positioned on the base structure and are mutually spaced.
Referring to fig. 3E, the present invention further provides a semiconductor device, including: a semiconductor substrate 300, a plurality of first gates and a plurality of second gates, wherein the semiconductor substrate 300 has a gate-dense region (WL) and a gate-sparse region (SG); the plurality of first gates are distributed on the gate dense region of the semiconductor substrate 300; the plurality of second gates are distributed on the gate dense region of the semiconductor substrate 300, and each of the second gates has a base structure (i.e., floating gate layer 301b in fig. 3E) and a plurality of spaced apart discrete structures (including control gate layer 303a over floating gate layer 301b) on the base structure.
In this embodiment, the plurality of discrete structures of the second gate next to the gate dense region and the plurality of first gates on the gate dense region are distributed with equal line width and equal interval.
when the semiconductor device is a floating gate type memory, the gate layer includes a floating gate layer, an inter-gate dielectric layer, and a control gate layer sequentially stacked on the surface of the semiconductor substrate 300. The grid electrode dense region is a word line region, the grid electrode sparse region is a selection grid region, the second grid electrode is a selection grid, and the first grid electrode is a word line (namely a control grid); and the base structure of the selection gate is a floating gate layer 301b with partial thickness or full thickness. Specifically, the control gate layers are a plurality of discrete structures in both the word line region and the select gate region, and each control gate layer 303a in the word line region is each word line; the floating gate layer 301a is a discrete structure corresponding to the word lines one by one in the word line region, the floating gate layer 301b is a structure with top intervals, one-to-one correspondence with the control gate layer 303a and bottom interconnection in the selection gate region, and the selection gate comprises the floating gate layer 301b with bottom interconnection in the gate sparse region and the control gate layer 303a above the floating gate layer 301 b. And the control gate layer 303a in the select gate adjacent to the word line region (i.e. the discrete structure of the select gate) and all the word lines in the word line region (i.e. the control gate layer 303a in the word line region) form a structure with equal line width and equal spacing distribution. In addition, the semiconductor device further includes an interlayer dielectric layer and a connection pad, the interlayer dielectric layer is located on the surface of the semiconductor substrate 300, the interlayer dielectric layer is filled between the adjacent discrete structures in each second gate, between the adjacent first gates, between the adjacent second gates, and in the space between the first gates and the second gates, and the top surface of the interlayer dielectric layer is lower than the top surface of the control gate layer 303 a; the connecting pads are used for electrically connecting the tops of all the control gate layers 303a in the select gate (i.e., the tops of all the discrete structures), and the connecting pads cover the surface of the interlayer dielectric layer between the adjacent control gate layers 303a in the select gate and the surface of the control gate layer above the interlayer dielectric layer.
The semiconductor device of the invention can be manufactured by adopting the manufacturing method of the semiconductor device of the invention, the semiconductor device of the invention has a plurality of first gates distributed on the gate dense region of the semiconductor substrate and a plurality of second gates distributed on the gate sparse region of the semiconductor substrate, each second gate has a base structure and a plurality of mutually spaced discrete structures positioned on the base structure, the uniformity of the critical dimension of the first gates in the gate dense region is higher, and the shape of the first gates close to the edge of the second gates is better, thereby improving the performance of the device.
since the manufacturing method of the semiconductor device and the structure of the semiconductor device of the present invention are changed from the prior art, a corresponding new mask design is required, and therefore, the present invention also provides a mask for forming the patterned core layer in the manufacturing method of the semiconductor device, or for manufacturing the first gate and the second gate in the semiconductor device. When the semiconductor device is a floating gate type memory, the mask is a word line mask (CG mask, or control gate mask). The mask plate can be used for manufacturing a semiconductor device with a sparse second grid and a dense first grid, can improve the uniformity of the key size of the formed first grid, ensures the shape of the first grid at the edge and improves the performance of the device.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (16)
1. A method of manufacturing a semiconductor device, comprising the steps of:
Providing a semiconductor substrate having a gate dense region and a gate sparse region, sequentially forming a gate layer and a patterned core layer on the surface of the semiconductor substrate, the patterned core layer having a plurality of mutually spaced cores located on the gate dense region and a plurality of mutually spaced cores located on the gate sparse region;
Forming a side wall on the side wall of the core;
Removing the patterned core layer, etching the gate layer by taking the side wall as a mask, and stopping etching in the gate layer to form a gate groove;
forming a protective layer for shielding the grid groove in the area corresponding to the second grid to be formed;
And continuously etching the gate layer to the surface of the semiconductor substrate along the gate trench exposed by the protective layer to form a first gate and a second gate, wherein the second gate comprises a base structure and a plurality of separated structures which are arranged on the base structure and are spaced from each other.
2. the method of manufacturing a semiconductor device according to claim 1, wherein a material of the patterned core layer comprises at least one of borate silicate glass, borophosphate silicate glass, phosphate silicate glass, ashing removable dielectric, low K dielectric, heating removable organic polymer, polycrystalline silicon, amorphous silicon, and amorphous carbon.
3. The method for manufacturing a semiconductor device according to claim 1, wherein a plurality of cores corresponding to the second gate electrode next to the gate-dense region and a plurality of cores on the gate-dense region are arranged at equal line widths and equal intervals.
4. the method for manufacturing a semiconductor device according to claim 1, wherein a hard mask layer is further formed between the gate layer and the patterned core layer, the hard mask layer being of a single-layer structure or a stacked-layer structure; the step of etching the gate layer by using the side wall as a mask comprises the following steps:
patterning the hard mask by using the side wall as a mask through an etching process;
and removing the side wall, etching the gate layer by taking the patterned hard mask layer as a mask, and stopping etching in the gate layer to form a gate groove.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the patterned hard mask layer is etched back after the gate trench is formed and before the protective layer is formed, and the gate layer is further etched toward the semiconductor substrate while the patterned hard mask layer is thinned, and a bottom of the gate layer is kept connected; and after continuously etching the gate layer to the surface of the semiconductor substrate along the gate trench exposed by the protective layer, removing the hard mask layer and the protective layer.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the protective layer is filled in a gate trench in the second gate corresponding region to be formed and covers a surface of the hard mask layer in the second gate corresponding region to be formed.
7. The method for manufacturing a semiconductor device according to claim 1, further comprising, after forming the first gate and the second gate:
Covering the surfaces of the semiconductor substrate, the first gates and the second gates with an interlayer dielectric layer, wherein the interlayer dielectric layer at least fills the intervals among the adjacent discrete structures, the adjacent first gates, the adjacent second gates and the first gates and the second gates in each second gate;
And carrying out back etching on the interlayer dielectric layer to enable the top surface of the interlayer dielectric layer to be lower than the top surface of the discrete structure.
8. The method of manufacturing a semiconductor device according to claim 7, further comprising, after the etching back of the interlayer dielectric layer: and forming a connecting pad for electrically connecting the tops of the discrete structures in the second grid electrode, wherein the connecting pad covers the surface of the interlayer dielectric layer between the adjacent discrete structures in the second grid electrode and the surface of the discrete structure above the interlayer dielectric layer.
9. the method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is a floating gate type memory, and the gate layer includes a floating gate layer, an intergate dielectric layer, and a control gate layer which are stacked in this order on a surface of the semiconductor substrate; etching the gate layer by taking the side wall as a mask, and stopping etching the gate layer on the floating gate layer; the grid electrode dense region is a word line region, the grid electrode sparse region is a selection grid region, the formed first grid electrode is a word line, the formed second grid electrode is a selection grid, and the base structure of the selection grid is a floating grid layer with partial thickness or full thickness.
10. a semiconductor device, comprising:
A semiconductor substrate having a gate dense region and a gate sparse region;
A plurality of first gates distributed on the gate dense region of the semiconductor substrate;
a plurality of second gates distributed over the gate thinning-out region of the semiconductor substrate, each of the second gates having a base structure and a plurality of spaced apart discrete structures on the base structure.
11. the semiconductor device of claim 10, wherein a plurality of discrete structures of the second gate next to the gate dense region are equally spaced and equally wide from a plurality of the first gates on the gate dense region.
12. the semiconductor device according to claim 10, wherein the semiconductor device is a floating gate type memory, and the gate layer includes a floating gate layer, an inter-gate dielectric layer, and a control gate layer which are stacked in this order on a surface of the semiconductor substrate; the grid electrode dense region is a word line region, the grid electrode sparse region is a selection grid region, the second grid electrode is a selection grid, the first grid electrode is a word line, and the base structure of the selection grid is a floating grid layer with partial thickness or full thickness.
13. the semiconductor device according to claim 10, further comprising: and the interlayer dielectric layers are filled between the adjacent discrete structures in each second grid electrode, between the adjacent first grid electrodes, between the adjacent second grid electrodes and in the intervals between the first grid electrodes and the second grid electrodes.
14. The semiconductor device of claim 13, wherein a top surface of the interlevel dielectric layer is lower than a top surface of the discrete structures, the semiconductor device further comprising a connection pad for electrically connecting top portions of the discrete structures in the second gate, the connection pad covering a surface of the interlevel dielectric layer between adjacent discrete structures in the second gate and a surface of the discrete structures above the interlevel dielectric layer.
15. A mask for forming a patterned core layer in a method for manufacturing a semiconductor device according to any one of claims 1 to 9, or for forming a first gate electrode and a second gate electrode in a semiconductor device according to any one of claims 10 to 14.
16. A mask as claimed in claim 15, wherein when the semiconductor device is a floating gate type memory, the mask is a word line mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810577992.2A CN110571219B (en) | 2018-06-05 | 2018-06-05 | Semiconductor device, manufacturing method thereof and mask plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810577992.2A CN110571219B (en) | 2018-06-05 | 2018-06-05 | Semiconductor device, manufacturing method thereof and mask plate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110571219A true CN110571219A (en) | 2019-12-13 |
| CN110571219B CN110571219B (en) | 2021-09-03 |
Family
ID=68771956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810577992.2A Active CN110571219B (en) | 2018-06-05 | 2018-06-05 | Semiconductor device, manufacturing method thereof and mask plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110571219B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112039476A (en) * | 2020-03-17 | 2020-12-04 | 中芯集成电路（宁波）有限公司 | Film bulk acoustic resonator, manufacturing method thereof, filter and electronic equipment |
| CN112289805A (en) * | 2020-10-29 | 2021-01-29 | 长江存储科技有限责任公司 | Manufacturing method of groove structure, three-dimensional NAND memory and manufacturing method thereof |
| CN113097294A (en) * | 2021-03-02 | 2021-07-09 | 长江存储科技有限责任公司 | Control method of grid characteristic dimension and field effect transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090163030A1 (en) * | 2007-12-18 | 2009-06-25 | Mitsuhiro Omura | Semiconductor device manufacturing method |
| US9269718B1 (en) * | 2014-09-05 | 2016-02-23 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor memory device |
| CN107706095A (en) * | 2016-06-20 | 2018-02-16 | 中芯国际集成电路制造(北京)有限公司 | The dual patterning process of autoregistration, semiconductor devices and preparation method thereof, electronic installation |
| CN110061007A (en) * | 2018-01-18 | 2019-07-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2018
- 2018-06-05 CN CN201810577992.2A patent/CN110571219B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090163030A1 (en) * | 2007-12-18 | 2009-06-25 | Mitsuhiro Omura | Semiconductor device manufacturing method |
| US9269718B1 (en) * | 2014-09-05 | 2016-02-23 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor memory device |
| CN107706095A (en) * | 2016-06-20 | 2018-02-16 | 中芯国际集成电路制造(北京)有限公司 | The dual patterning process of autoregistration, semiconductor devices and preparation method thereof, electronic installation |
| CN110061007A (en) * | 2018-01-18 | 2019-07-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112039476A (en) * | 2020-03-17 | 2020-12-04 | 中芯集成电路（宁波）有限公司 | Film bulk acoustic resonator, manufacturing method thereof, filter and electronic equipment |
| CN112039476B (en) * | 2020-03-17 | 2024-03-12 | 中芯集成电路（宁波）有限公司 | Film bulk acoustic resonator, manufacturing method thereof, filter and electronic equipment |
| CN112289805A (en) * | 2020-10-29 | 2021-01-29 | 长江存储科技有限责任公司 | Manufacturing method of groove structure, three-dimensional NAND memory and manufacturing method thereof |
| CN113097294A (en) * | 2021-03-02 | 2021-07-09 | 长江存储科技有限责任公司 | Control method of grid characteristic dimension and field effect transistor |
| CN113097294B (en) * | 2021-03-02 | 2022-05-10 | 长江存储科技有限责任公司 | Control method of grid characteristic dimension and field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110571219B (en) | 2021-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7052983B2 (en) | Method of manufacturing a semiconductor device having selective epitaxial silicon layer on contact pads | |
| CN110581103B (en) | Semiconductor element and manufacturing method thereof | |
| CN108933140B (en) | Method for manufacturing semiconductor device | |
| US20080303115A1 (en) | Semiconductor memory device and method of fabricating the same | |
| CN109390285B (en) | Contact structure and manufacturing method thereof | |
| CN110571219B (en) | Semiconductor device, manufacturing method thereof and mask plate | |
| CN110061001B (en) | Semiconductor element and manufacturing method thereof | |
| CN109786385B (en) | Flash memory and forming method thereof and flash memory structure | |
| CN113013092A (en) | Semiconductor structure forming method and semiconductor structure | |
| KR100919342B1 (en) | Method of manufacturing a semiconductor device | |
| KR101168606B1 (en) | wiring structure of semiconductor device and Method of forming a wiring structure | |
| CN108962901B (en) | Semiconductor memory device, method of manufacturing the same, and mask plate | |
| US20230290727A1 (en) | Semiconductor devices and methods of manufacturing the same | |
| JP2000049112A (en) | Formation of self-alignment contact of semiconductor device | |
| US10971508B2 (en) | Integrated circuit and method of manufacturing the same | |
| US20080203586A1 (en) | Integrated Circuit and Methods of Manufacturing a Contact Arrangement and an Interconnection Arrangement | |
| KR20090049379A (en) | Method for manufacturing flash memory device | |
| CN113192824B (en) | Mask plate of split gate type flash memory and manufacturing method | |
| CN110571220B (en) | Semiconductor device, manufacturing method thereof and mask plate | |
| TWI469269B (en) | Method of forming word line of embedded flash memory | |
| CN110246841B (en) | Semiconductor element and manufacturing method thereof | |
| US6967161B2 (en) | Method and resulting structure for fabricating DRAM cell structure using oxide line spacer | |
| TW201644005A (en) | Semiconductor device and method of forming the same | |
| JP2007184489A (en) | Semiconductor integrated circuit device, and its manufacturing method | |
| TWI588973B (en) | Memory device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |