CN110676259B - Three-dimensional storage structure and manufacturing method thereof - Google Patents
Three-dimensional storage structure and manufacturing method thereof Download PDFInfo
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- CN110676259B CN110676259B CN201910779943.1A CN201910779943A CN110676259B CN 110676259 B CN110676259 B CN 110676259B CN 201910779943 A CN201910779943 A CN 201910779943A CN 110676259 B CN110676259 B CN 110676259B
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The invention provides a three-dimensional storage structure and a manufacturing method thereof. The stacking structure of the three-dimensional storage structure comprises a core array area and a step area located on at least one side of the core array area, the three-dimensional storage structure further comprises a hole structure, the hole structure is provided with a plurality of channel holes, the stacking structure is divided into areas in the three-dimensional storage structure, and the density of the hole structure in each area is adjusted respectively, so that the distribution of the hole structure in the core array area and the step area is more smooth in transition, and therefore in the process of forming a grid spacer groove in the three-dimensional storage structure, the possibility of generating an inclined point at the bottom of the grid spacer groove in the process of etching the grid spacer groove is effectively reduced or even avoided, and the performance of the three-dimensional storage structure is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional storage structure and a manufacturing method thereof.
Background
In the prior art, a Flash Memory (Flash Memory) has a main function of maintaining stored information for a long time without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, so that the Flash Memory is widely applied to electronic products. In order to further increase the Bit Density (Bit Density) of the flash memory and reduce the Bit Cost (Bit Cost), a three-dimensional flash memory (3D NAND) is further proposed.
In the 3D NAND flash memory structure, a stacked 3DNAND memory structure is realized by vertically stacking a plurality of layers of data storage units. The stack structure in the 3D NAND flash memory structure generally includes a core array region and a step region in which dummy channel holes and contact holes are simultaneously distributed, and a gate spacer extending from the core array region to the step region. However, in the conventional process for forming the 3D NAND flash memory structure, the density of the hole structure in the step region is much lower than that in the core array region, so that the gate spacer is prone to generate a slant point (weak point) at the bottom during the etching process, thereby affecting the performance of the finally formed 3D NAND flash memory structure.
Disclosure of Invention
The invention mainly aims to provide a three-dimensional storage structure and a manufacturing method thereof, and aims to solve the problem that a grid spacer groove in the prior art is easy to generate a slant point (weak point) in an etching process.
To achieve the above object, according to one aspect of the present invention, there is provided a three-dimensional memory structure including:
the device comprises a substrate and a stacked structure, wherein the stacked structure is positioned on the substrate;
the stacking structure comprises a core array area and a step area positioned on at least one side of the core array area, the three-dimensional storage structure also comprises a hole structure positioned in the stacking structure and penetrating to the substrate, the hole structure comprises a plurality of channel holes, and a storage structure is arranged in each channel hole;
dividing the stacked structure into a first region, a second region and a third region sequentially arranged along a first direction;
the first direction is a direction pointing from the core array region to the step region;
the second area comprises a part of the core array area and a part of the step area;
pore structures are distributed in the first area, the second area and the third area, and the density of the pore structures in the first area is defined as R1The density of the pore structure in the second region is R2The density of the hole structure in the third region is R3，R1And R2And R3Are not identical.
Further, R1>R2>R3。
Further, in the first direction, the density of the pore structures is the same in the second region; the density of the pore structure in the first region is graded and/or the density of the pore structure in the third region is graded.
Further, the density of the pore structure in the second region is graded in the first direction.
Further, in the first direction, the density of the pore structure in the second region is represented by RmaxGradation to RminAnd R is1≥Rmax＞Rmin≥R3。
Further, the hole structure in the first region is defined as a first through hole, the hole structure in the second region is defined as a second through hole, the hole structure in the third region is defined as a third through hole, projections of the first through hole, the second through hole and the third through hole on the substrate have the same size, and the distance between any two adjacent first through holes is defined as L1The distance between any two adjacent second through holes is L2The distance between any two adjacent third through holes is L3，L1、L2And L3Are not identical.
Further, L1＜L2＜L3。
Further, in the first direction, the distance between any two adjacent second through holes is equal; in the first direction, the pitch of the first through holes is gradually changed and/or the pitch of the third through holes is gradually changed.
Further, in the first direction, the distance between any two adjacent second through holes gradually changes.
Further, in the first direction, the distance between any two adjacent second through holes is LminGradual change to LmaxAnd L is1＜Lmin＜Lmax＜L3。
Further, the hole structure in the first region is defined as a first through hole, the hole structure in the second region is defined as a second through hole, the hole structure in the third region is defined as a third through hole, the distance between any two adjacent first through holes, the distance between any two adjacent second through holes and the distance between any two adjacent third through holes are the same, and the area of the projection of the first through holes on the substrate is defined as S1The area of the projection of the second through hole on the substrate is S2The projection area of the third through hole on the substrate is S3，S1、S2And S3Are not identical.
Further, S1＞S2＞S3。
Furthermore, the projected areas of any two second through holes on the substrate are the same; in the first direction, the area of the first through hole projected on the substrate and/or the area of the third through hole projected on the substrate are gradually changed.
Further, in the first direction, the area of the projection of each second through hole on the substrate is gradually changed.
Further, in the first direction, the area of the projection of each second through hole on the substrate is SmaxGradually change to SminAnd S is1＞Smax＞Smin＞S3。
Further, defining the hole structure in the first region as a first through hole, the hole structure in the second region as a second through hole, and the hole structure in the third region as a third through hole; defining the distance between any two adjacent first through holes as L1The distance between any two adjacent third through holes is L3In the first direction, the space between any two adjacent second through holes is gradually changed, and the projection area of the first through hole on the substrate is defined as S1The projection area of the third through hole on the substrate is S3And in the first direction, the projection area of each second through hole on the substrate is gradually changed.
Further, the pitch of each second trench via is defined by LminGradual change to LmaxThe area of projection of each second through hole on the substrate is SmaxGradually change to SminWherein L is1＜Lmin＜Lmax＜L3，S1＞Lmax＞Lmin＞S3。
Further, in the first direction, the pitch of each first through hole gradually changes and/or the pitch of each third through hole gradually changes; in the first direction, the area projected on the substrate by each first through hole is gradually changed and/or the area projected on the substrate by each third through hole is gradually changed.
Further, the hole structure further includes a dummy channel hole.
Furthermore, the three-dimensional storage structure further comprises a grid isolation groove, the grid isolation groove extends from the core array region to the step region and penetrates through the substrate, and a conductive semiconductor layer is arranged in the grid isolation groove.
According to another aspect of the present invention, there is provided a method for fabricating a three-dimensional memory structure, comprising the steps of:
s1, forming a stacked structure on the substrate, wherein the stacked structure comprises a core array area and a step area positioned on at least one side of the core array area;
s2, dividing the stacked structure into a first region, a second region and a third region arranged in sequence along a first direction, wherein the first direction is a direction pointing from the core array region to the step region, and the second region comprises part of the coreAn array region and a partial step region, wherein a plurality of hole structures penetrating through the substrate are formed in the first region, the second region and the third region, each hole structure comprises a plurality of channel holes, and the density of the hole structures in the first region is defined as R1The density of the pore structure in the second region is R2The density of the hole structure in the third region is R3，R1And R2And R3Are not identical;
and S3, forming a storage structure in the channel hole.
Further, R1>R2>R3。
Further, pore structures are formed in the second region such that the density of the pore structures in the second region is the same in the first direction; the hole structures are formed in the first region and/or the third region such that the density of the hole structures is graded in the first direction.
Further, the pore structure is formed in the second region such that the density of the pore structure in the second region is graded in the first direction.
Further, the hole structures are formed in the second region such that the density of the hole structures in the second region in the first direction is represented by RmaxGradation to RminAnd R is1＞Rmax＞Rmin＞R3。
Further, a hole structure is formed in the first region and is marked as a first through hole, so that the distance between any two adjacent first through holes is L1Forming a hole structure in the second region and marking as a second through hole, so that the distance between any two adjacent second through holes is L2Forming a hole structure in the third region and recording as a third through hole, so that the distance between any two adjacent third through holes is L3The projections of the first through hole, the second through hole and the third through hole on the substrate have the same size, L1、L2And L3Are not identical.
Further, L1＜L2＜L3。
Further, second through holes are formed in the second region, so that the pitches of any two adjacent second through holes in the first direction are equal; and forming first through holes in the first area and third through holes in the third area, so that the pitch of the first through holes is gradually changed and/or the pitch of the third through holes is gradually changed in the first direction.
Further, second through holes are formed in the second region so that the pitch of any two adjacent second through holes in the first direction is gradually changed.
Further, second through holes are formed in the second region such that the pitch of any two adjacent second through holes in the first direction is LminGradual change to LmaxAnd L is1＜Lmin＜Lmax＜L3。
Further, a hole structure is formed in the first region and is marked as a first through hole, so that the area of the projection of the first through hole on the substrate is S1Forming a hole structure in the second area and marking as a second through hole, so that the projection area of the second through hole on the substrate is S2Forming a hole structure in the third region and recording as a third through hole, so that the area of the projection of the third through hole on the substrate is S3，S1、S2And S3The distance between any two adjacent first through holes, the distance between any two adjacent second through holes and the distance between any two adjacent third through holes are not completely the same.
Further, S1＞S2＞S3。
Further, forming second through holes in the second region, so that the projected areas of any two second through holes on the substrate are the same; the first through hole is formed in the first region, and the third through hole is formed in the third region, so that the area of the first through hole projected on the substrate and/or the area of the third through hole projected on the substrate in the first direction are gradually changed.
Further, second through holes are formed in the second area, so that the area of projection of each second through hole on the substrate in the first direction is gradually changed.
Further, second through holes are formed in the second region such that the area projected on the substrate by each second through hole in the first direction is represented by SmaxGradually change to SminAnd S is1＞Lmax＞Lmin＞S3。
Further, a hole structure is formed in the first region and is marked as a first through hole, so that the distance between any two adjacent first through holes is L1The area of the first through hole projected on the substrate is S1(ii) a Forming a hole structure in the second region and marking as a second through hole, so that the distance between any two adjacent second through holes is L2The area of the projection of the second through hole on the substrate is S2(ii) a Forming a hole structure in the third region and marking as a third through hole, so that the distance between any two adjacent third through holes is L3The area of the projection of the third through hole on the substrate is S3(ii) a The distance between any two adjacent second through holes is gradually changed, and the projection area of each second through hole on the substrate is gradually changed.
Further, the pitch of each second trench via is defined by LminGradual change to LmaxThe area of projection of each second through hole on the substrate is SmaxGradually change to SminWherein L is1＜Lmin＜Lmax＜L3，S1＞Lmax＞Lmin＞S3。
Further, the first through holes are formed in the first area, the third through holes are formed in the third area, so that the distance between the first through holes and/or the distance between the third through holes in the first direction gradually changes, and the area projected by the first through holes on the substrate and/or the area projected by the third through holes on the substrate in the first direction gradually changes.
Further, step S2 further includes: forming a plurality of dummy channel holes penetrating to the substrate in each of the first region, the second region, and the third region; step S3 further includes: a dummy channel material layer is formed in the dummy channel hole.
Further, after step S2, the manufacturing method further includes the steps of: forming gate isolation grooves in the stacked structure, so that the gate isolation grooves extend from the core array region to the step region and penetrate to the substrate; a conductive semiconductor layer is formed in the gate spacer.
The technical scheme of the invention is applied to provide a three-dimensional storage structure, the stacked structure of the three-dimensional storage structure comprises a core array area and a step area positioned on at least one side of the core array area, the three-dimensional storage structure also comprises a hole structure, the hole structure is provided with a plurality of channel holes, the three-dimensional storage structure is divided into areas by the stacked structure, and the distribution of the hole structure in the transition from the core array area to the step area is more smooth by respectively adjusting the density of the hole structure in each area, so that in the process of forming a grid spacer groove in the three-dimensional storage structure, the possibility of generating an inclined point at the bottom of the grid spacer groove in the process of etching the grid spacer groove is effectively reduced or even avoided, and the performance of the three-dimensional storage structure is further improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram illustrating a top view of a hole structure in a three-dimensional storage structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a top view of a hole structure in another three-dimensional storage structure provided by an embodiment of the invention;
fig. 3 is a schematic cross-sectional view illustrating a gate spacer in a three-dimensional memory structure according to an embodiment of the present invention.
Wherein the figures include the following reference numerals:
10. a substrate; 110. a first region; 120. a second region; 130. a third region; 20. a stacked structure; 30. a dielectric layer; 40. a pore structure; 410. a first through hole; 420. a second through hole; 430. a third through hole; 50. and a gate spacer.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background, in the conventional process for forming a 3D NAND flash memory structure, the density of the hole structure in the step region is much lower than that in the core array region, so that the gate spacer tends to generate a slant point (weak point) at the bottom during the etching process, thereby affecting the performance of the finally formed 3D NAND flash memory structure.
The inventors of the present invention have studied the above problems, and have proposed a three-dimensional memory structure, as shown in fig. 1 and 2, including a substrate 10 and a stacked structure 20, where the stacked structure 20 is located on the substrate 10, and the stacked structure 20 includes a core array region and a step region located on at least one side of the core array region, and a hole structure 40 located in the stacked structure 20 and penetrating to the substrate 10, where the hole structure 40 includes a plurality of channel holes, and a memory structure is disposed in each channel hole, and the stacked structure is to be stackedThe structure 20 is divided into a first region 110, a second region 120 and a third region 130 which are sequentially arranged along a first direction, the first direction is a direction pointing from the core array region to the step region, the second region 120 comprises a part of the core array region and a part of the step region, the first region 110, the second region 120 and the third region 130 are all distributed with the pore structures 40, and the density of the pore structures 40 in the first region 110 is defined as R1The density of the hole structure 40 in the second region 120 is R2The density of the pore structure 40 in the third region 130 is R3，R1And R2And R3Are not identical.
The three-dimensional storage structure has the advantages that the stacked structure is divided into the regions, and the density of the pore structures in each region is respectively adjusted, so that the distribution of the pore structures in the transition from the core array region to the step region is more gradual, the possibility of generating inclined points at the bottom of the gate spacer groove in the process of forming the gate spacer groove in the three-dimensional storage structure is effectively reduced or even avoided, and the performance of the three-dimensional storage structure is improved.
The material of the substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 10 is single crystal silicon (Si).
The above-mentioned stacked structure has a core array region as shown in region a in fig. 1 and a step region located on at least one side of the core array region as shown in region B in fig. 1, and the hole structures 40 are distributed in both the core array region and the step region as shown in fig. 1.
The hole structure 40 includes a plurality of channel holes, each of which is distributed in the core array region and the step region, and a memory structure is formed in the channel hole. The memory structure may include a charge storage layer on a sidewall surface of the channel hole and a channel layer on a surface of the charge storage layer, the charge storage layer includes a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer, the charge trapping layer may be made of silicon nitride, and the channel layer may be made of polysilicon.
The hole structure 40 may further include a plurality of dummy channel holes, each dummy channel hole being distributed in the core array region and the step region, and a dummy channel material layer disposed in the dummy channel hole and not removed when the sacrificial layer is removed, so that the dummy channel material layer can support the step structure, and the step structure is not easily collapsed.
The stacked structure may include a plurality of sacrificial layers and a plurality of isolation layers, wherein each sacrificial layer and each isolation layer are alternately stacked in a direction away from the substrate 10, the sacrificial layers are subsequently removed to form a cavity, and the removed positions of the sacrificial layers are used for forming a control gate. The isolation layer is used for electrical isolation between the control gates of different layers and for electrical isolation between the control gates and other devices (conductive contacts, trench holes, etc.). The number of layers of the stacked structure is determined according to the number of memory cells required to be formed in the vertical direction.
The material of the isolation layer may be selected from any one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride, and the material of the sacrificial layer may be selected from one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polysilicon. The above materials enable the sacrificial layer to have a high etch selectivity with respect to the isolation layer.
The three-dimensional memory structure of the present invention may further include a gate spacer 50, as shown in fig. 3, the gate spacer 50 extends from the core Array region to the step region and penetrates through the substrate 10, and the gate spacer 50 is formed to form an Array Common Source (ACS). A conductive semiconductor layer is formed in the gate spacer 50, and a metal layer is formed on the conductive semiconductor layer so that the gate spacer is filled with the metal layer. The conductive semiconductor layer and the metal layer constitute an Array Common Source (ACS). The gate spacer 50 is also used to expose a portion of the surface of the sacrificial layer in the stacked structure before forming the conductive semiconductor layer, so as to form a control gate at the position where the sacrificial layer is removed.
The material of the conductive semiconductor layer may include silicon, germanium, silicon germanium, or silicon carbide, and the material of the metal layer may be tungsten.
The three-dimensional memory structure of the present invention may further include a dielectric layer 30, as shown in fig. 3, the dielectric layer 30 covers the step region, and the material of the dielectric layer 30 may be silicon oxide, but is not limited to the above kind, and those skilled in the art can reasonably select the material of the dielectric layer 30 according to the prior art.
In the above-described three-dimensional memory structure of the present invention, the density of the hole structures 40 in the first region 110 is R1The density of the hole structure 40 in the second region 120 is R2The density of the pore structure 40 in the third region 130 is R3Preferably R1＞R2＞R3. In a first direction, R2May be between R1And R3A fixed value therebetween, or a larger density RmaxTowards a lower density RminGradually change of the above Rmax≤R1And R ismin≥R3。
In the three-dimensional storage structure, the density of the hole structures (defined as the second through holes) in the second area connecting the core array area and the step area is smaller than that of the hole structures (defined as the first through holes) in the adjacent core array area (namely the first area), and the density of the second through holes is larger than that of the hole structures (defined as the third through holes) in the adjacent step area (namely the third area), so that the distribution of the hole structures in the transition from the core array area to the step area is smoother, the possibility of generating inclined points at the bottom of the gate spacer groove in the process of forming the gate spacer groove in the three-dimensional storage structure is effectively reduced or even avoided, and the performance of the three-dimensional storage structure is improved.
Influencing the density (R) of the pore structure 40 in the first, second and third regions 110, 120, 1301、R2And R3) May include the spacing of adjacent aperture structures 40, the cross-sectional area of aperture structures 40, which may be through aperture structures 40, and the likeThe projected size on the substrate 10.
According to a first embodiment of the invention, to realize R1＞R2＞R3So as to avoid the generation of the oblique point at the bottom of the gate spacer during the etching process, in a preferred embodiment, the hole structure 40 located in the first region 110 is defined as a first through hole 410, the hole structure 40 located in the second region 120 is defined as a second through hole 420, the hole structure 40 located in the third region 130 is defined as a third through hole 430, and the projections of the first through hole 410, the second through hole 420 and the third through hole 430 on the substrate 10 have the same size, as shown in fig. 2, the distance between any two adjacent first through holes 410 is defined as L1The distance between any two adjacent second through holes 420 is L2The distance between any two adjacent third through holes 430 is L3，L1＜L2＜L3. In other embodiments, L1，L2，L3The relationship between can be defined by itself, e.g. L1＜L2＝L3，L1＝L2＜L3，L1＜L3＝L2，L2＜L3＝L1And the like in any size combination.
In the above preferred embodiment, R is achieved by keeping the projected size of the hole structures 40 on the substrate 10 constant and adjusting the distances between adjacent hole structures 40 in the first region 110, the second region 120 and the third region 130, respectively, to optimize the density of the hole structures 40 in different regions1＞R2＞R3。
In the above preferred embodiment, the distance between any two adjacent second through holes 420 may be equal or may not be equal. In order to make the distribution of the hole structure in the transition from the core array area to the step area more gradual, the distance between any two adjacent second through holes 420 in the first direction is gradually changed and is LminGradual change to LmaxAnd L is1≤Lmin＜Lmax≤L3. The distance between some of the second through holes 420 and the adjacent second through holes 420 and the distance between other adjacent second through holes 420 can also be selectedAre different.
In other preferred embodiments, the distance between any two adjacent first through holes 410 may be equal or may not be equal. For example, the distance between any two adjacent first through holes 410 may be gradually increased or decreased along the first direction, or the distance between some of the first through holes 410 and the adjacent first through holes 410 may be selected to be different from the distance between other adjacent first through holes 410.
In other preferred embodiments, the distance between any two adjacent third through holes 430 may be equal or may not be equal. For example, the distance between any two adjacent third through holes 430 may gradually increase or decrease along the first direction, or a distance between a part of the third through holes 430 and the adjacent third through holes 430 may be selected to be different from the distance between other adjacent third through holes.
According to a second embodiment of the invention, to realize R1＞R2＞R3In a preferred embodiment, the hole structures 40 in the first region 110 are defined as first through holes 410, the hole structures 40 in the second region 120 are defined as second through holes 420, the hole structures 40 in the third region 130 are defined as third through holes 430, a distance between any two adjacent first through holes 410, a distance between any two adjacent second through holes 420, and a distance between any two adjacent third through holes 430 are the same, and a projection area of the first through holes 410 on the substrate 10 is defined as S1The projected area of the second through hole 420 on the substrate 10 is S2The projection area of the third through hole 430 on the substrate 10 is S3，S1＞S2＞S3. In other embodiments, R1，R2，R3The relationship between can be defined by itself, e.g. R1＜R2＝R3，R1＝R2＜R3，R1＜R3＝R2，R2＜R3＝R1And the like in any size combination.
In the preferred embodiment, the first region 110 and the second region are adjusted by keeping the pitch between the adjacent hole structures 40 constant120 and a third region 130 to achieve optimization of the density of the nanostructures 40 in the different regions, thereby achieving R1＞R2＞R3。
In the above preferred embodiment, the projected areas of any two second through holes 420 on the substrate 10 may be the same or different; in order to make the distribution of the hole structure in the transition from the core array region to the step region more gradual, it is more preferable that the area projected on the substrate 10 by each second through hole 420 is gradually changed in the first direction and is SmaxGradually change to SminAnd S is1≥Smax＞Smin≥S3. A portion of the second vias 420 may also be selected to have a different area on the substrate 10 than other second vias.
In other preferred embodiments, the projected areas of any two first through holes 410 on the substrate 10 may be the same or different, for example, the projected area of each first through hole 410 on the substrate 10 may gradually increase or decrease along the first direction, or the area of a part of the first through holes 410 may be selected to be different from the projected areas of other first through holes 410.
In other preferred embodiments, the projected areas of any two third through holes 430 on the substrate 10 may be the same or different, for example, the projected areas of the third through holes 430 on the substrate 10 may gradually increase or decrease along the first direction, or the area of a part of the third through holes 430 may be selected to be different from the projected areas of other third through holes 430.
According to a third embodiment of the invention, to realize R1＞R2＞R3In a preferred embodiment, the hole structure 40 in the first area 110 is defined as a first through hole 410, the hole structure 40 in the second area 120 is defined as a second through hole 420, and the hole structure 40 in the third area 130 is defined as a third through hole 430; defining the distance between any two adjacent first through holes 410 as L1The distance between any two adjacent third through holes 430 is L3In the first direction, the pitch of each second through hole 420 gradually changes; defining a projection of a first via 410 on the substrate 10Area is S1The projection area of the third through hole 430 on the substrate 10 is S3In the first direction, the area projected on the substrate 10 by each second through hole 420 is gradually changed. In other embodiments, L1，L2，L3And R1，R2，R3The relationship between can be defined by itself, e.g. L1＜L2＝L3，R1＜R2＝R3，L1＝L2＜L3，R1＝R2＜R3，L1＜L3＝L2，R1＜R3＝R2，L2＜L3＝L1，R2＜R3＝R1And the like in any size combination.
In the above preferred embodiment, by adjusting the distances between adjacent pore structures 40 in the first region 110, the second region 120 and the third region 130, and simultaneously adjusting the projection sizes of the pore structures 40 in the first region 110, the second region 120 and the third region 130 on the substrate 10, the distribution of the pore structures in the transition from the core array region to the step region is more gradual, so as to more effectively avoid the possibility of generating an inclined point at the bottom of the gate spacer during the etching process.
In the above preferred embodiment, the projected areas of any two second through holes 420 on the substrate 10 may be the same or different, and the projected areas of any two first through holes 410 on the substrate 10 may be the same or different; in order to make the distribution of the hole structure more gradual in the transition from the core array region to the step region, it is more preferable that the distance between any two adjacent second through holes 420 in the first direction is LminGradual change to LmaxAnd L is1≤Lmin＜Lmax≤L3While the area projected on the substrate 10 by each second through hole 420 is represented by SmaxGradually change to SminAnd S is1≥Smax＞Smin≥S3. Alternatively, a distance between some of the second through holes 420 and the adjacent second through holes 420 may be different from a distance between other adjacent second through holes 420, and some of the second through holes may be simultaneouslyThe second via 420 has a different area on the substrate 10 than the other second vias.
In other preferred embodiments, the distances between any two adjacent first through holes 410 may be equal or unequal, and the projected areas of any two first through holes 410 on the substrate 10 may be the same or different. For example, the distance between any two adjacent first through holes 410 may gradually increase or decrease along the first direction, and the area of the projection of each first through hole 410 on the substrate 10 gradually increases or decreases, or a distance between a part of the first through holes 410 and the adjacent first through holes 410 may be different from a distance between other adjacent first through holes 410, and an area of a part of the first through holes 410 is different from a projection area of other first through holes 410.
In other preferred embodiments, the distances between any two adjacent third through holes 430 may be equal or unequal, and the projected areas of any two third through holes 430 on the substrate 10 may be the same or different. For example, the distance between any two adjacent third through holes 430 may gradually increase or decrease along the first direction, and the area of the projection of each third through hole 430 on the substrate 10 gradually increases or decreases, or a distance between a part of the third through holes 430 and the adjacent third through holes 430 may be different from the distance between other adjacent third through holes 430, and the area of a part of the third through holes 430 is different from the area of the projection of other third through holes 430.
According to another aspect of the present invention, there is also provided a method for manufacturing the three-dimensional memory structure, including the following steps:
s1, forming a stacked structure 20 on the substrate 10, the stacked structure 20 including a core array region and a step region on at least one side of the core array region;
s2, dividing the stacked structure 20 into a first region 110, a second region 120 and a third region 130 sequentially arranged along a first direction, the first direction being a direction pointing from the core array region to the step region, the second region 120 including a part of the core array region and a part of the step region, in each of the first region 110, the second region 120 and the third region 130Forming a plurality of pore structures 40 extending through the substrate 10, the pore structures 40 including a plurality of channel holes, the density of the pore structures 40 defined as R in the first region 1101The density of the hole structure 40 in the second region 120 is R2The density of the pore structure 40 in the third region 130 is R3，R3，R1And R2And R3Are not identical;
and S3, forming a storage structure in the channel hole.
According to the manufacturing method, the densities of the hole structures formed in different areas can be optimized respectively, and the distribution of the hole structures in the transition from the core array area to the step area can be more smooth by adjusting the densities of the hole structures in the areas respectively, so that in the process of forming the grid separation groove in the three-dimensional storage structure, the possibility of generating an inclined point at the bottom of the grid separation groove in the process of etching the grid separation groove is effectively reduced or even avoided, and the performance of the three-dimensional storage structure is improved.
An exemplary embodiment of a method of fabricating a three-dimensional memory structure provided in accordance with the present invention will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, the above step S1 is executed: a stack structure 20 is formed on the substrate 10, the stack structure 20 including a core array region and a step region at least one side of the core array region.
The step of forming the above stacked structure may include: sacrificial layers and isolation layers are sequentially and alternately formed on the substrate 10. The isolation layer and the sacrificial layer may be prepared by conventional deposition processes of the prior art, such as chemical vapor deposition processes.
The step S1 may further include the step of forming the dielectric layer 30 on the step region, and the process of forming the dielectric layer may be selected from any one of a plasma enhanced chemical vapor deposition process, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a high density plasma chemical vapor deposition process, and an atomic layer chemical vapor deposition process.
After completion of the above step S1, steps S2 and S3 are sequentially performed: forming a plurality of hole structures 40 penetrating through the substrate 10 in each of the first, second and third regions 110, 120 and 130, the hole structures 40 including a plurality of channel holes, the density of the hole structures 40 defined as R in the first region 1101The density of the hole structure 40 in the second region 120 is R2The density of the pore structure 40 in the third region 130 is R3Preferably R1＞R2＞R3(ii) a A memory structure is formed in the channel hole.
The density of the formed hole structure is optimized in the steps, so that the density of the second through holes in the second area connecting the core array area and the step area is smaller than that of the first through holes in the adjacent core array area (namely, the first area), and the density of the second through holes is larger than that of the third through holes in the adjacent step area (namely, the third area), so that the distribution of the hole structure in the transition from the core array area to the step area is smoother, the possibility of generating inclined points at the bottom of the gate spacer groove in the process of forming the gate spacer groove in the three-dimensional storage structure is effectively reduced or even avoided, and the performance of the three-dimensional storage structure is improved.
The step S2 may further include a step of forming a plurality of dummy channel holes in the first, second, and third regions 110, 120, and 130, wherein in the step S3, some materials are filled in the dummy channel holes, and the materials are not removed when the sacrificial layer is removed, so as to support the step structure, such that the step structure is not easily collapsed.
In the above step S2, the density of the pore structures 40 formed in the first region 110 is R1The density of the pore structures 40 formed in the second region 120 is R2The density of the pore structure 40 formed in the third region 130 is R3，R1＞R2＞R3. In a first direction, R2May be between R1And R3A fixed value therebetween, or a larger density RmaxTowards a lower density RminGradually change of the above Rmax≤R1And R ismin≥R3。
According to a fourth embodiment of the invention, to achieve R1＞R2＞R3So as to avoid the inclined point generated at the bottom of the gate spacer during the etching process, in a preferred embodiment, the hole structure 40 is formed in the first region 110 and is denoted as the first through hole 410, so that the distance between any two adjacent first through holes 410 is L1 A hole structure 40 is formed in the second area 120 and is denoted as a second through hole 420, so that the distance between any two adjacent second through holes 420 is L2 A hole structure 40 is formed in the third region 130 and is denoted as a third through hole 430, so that the distance between any two adjacent third through holes 430 is L3The projections of the first through hole 410, the second through hole 420 and the third through hole 430 on the substrate 10 have the same size, and L1＜L2＜L3. In other embodiments, L1，L2，L3The relationship between can be defined by itself, e.g. L1＜L2＝L3，L1＝L2＜L3，L1＜L3＝L2，L2＜L3L1, and the like.
In the above preferred embodiment, R is achieved by keeping the projected size of the hole structures 40 on the substrate 10 constant and adjusting the distances between adjacent hole structures 40 in the first region 110, the second region 120 and the third region 130, respectively, to optimize the density of the hole structures 40 in different regions1＞R2＞R3。
In the preferred embodiment, the second through holes 420 are formed in the second region 120, so that the pitches of any two adjacent second through holes 420 may be equal or unequal. In order to make the distribution of the hole structure more gradual in the transition of the core array region to the stepped region, it is more preferable that the second through holes 420 are formed in the second region 120 so as to be in the first directionThe distance between any two adjacent second through holes 420 is gradually changed and is LminGradual change to LmaxAnd L is1≤Lmin＜Lmax≤L3. It is also possible to select a distance between some of the second through holes 420 and the adjacent second through holes 420 to be different from the distance between other adjacent second through holes 420.
In other preferred embodiments, the distance between any two adjacent first through holes 410 may be equal or may not be equal. For example, the distance between any two adjacent first through holes 410 may be gradually increased or decreased along the first direction, or the distance between some of the first through holes 410 and the adjacent first through holes 410 may be selected to be different from the distance between other adjacent first through holes 410.
In other preferred embodiments, the distance between any two adjacent third through holes 430 may be equal or may not be equal. For example, the distance between any two adjacent third through holes 430 may gradually increase or decrease along the first direction, or a distance between a part of the third through holes 430 and the adjacent third through holes 430 may be selected to be different from the distance between other adjacent third through holes.
According to a fifth embodiment of the invention, to achieve R1＞R2＞R3In a preferred embodiment, the hole structure 40 is formed in the first region 110 and is denoted as a first through hole 410, so that the area of the first through hole 410 projected on the substrate 10 is S1 A hole structure 40 is formed in the second area 120 and is denoted as a second via 420, such that the area of the projection of the second via 420 on the substrate 10 is S2 A hole structure 40 is formed in the third region 130 and is denoted as a third through hole 430, so that the area projected by the third through hole 430 on the substrate 10 is S3，S1＞S2＞S3And the pitch of any two adjacent first through holes 410, the pitch of any two adjacent second through holes 420, and the pitch of any two adjacent third through holes 430 are the same. In other embodiments, R1，R2，R3The relationship between can be defined by itself, e.g. R1＜R2＝R3，R1＝R2＜R3，R1＜R3＝R2，R2＜R3R1, and the like.
In the preferred embodiment, R is achieved by keeping the pitch of the adjacent pore structures 40 constant and adjusting the projection sizes of the pore structures 40 on the substrate 10 in the first region 110, the second region 120 and the third region 130 respectively to optimize the density of the pore structures 40 in different regions1＞R2＞R3。
In the above preferred embodiment, by forming the second through holes 420 in the second region 120, the areas of projection of any two second through holes 420 on the substrate 10 may be the same or different; in order to make the distribution of the hole structure in the transition from the core array region to the step region more gradual, it is more preferable that the second through holes 420 are formed in the second region 120, so that the area projected on the substrate 10 by each second through hole 420 in the first direction is gradually changed and is changed by SmaxGradually change to SminAnd S is1≥Smax＞Smin≥S3. A portion of the second vias 420 may also be selected to have a different area on the substrate 10 than other second vias.
In other preferred embodiments, the projected areas of any two first through holes 410 on the substrate 10 may be the same or different, for example, the projected area of each first through hole 410 on the substrate 10 may gradually increase or decrease along the first direction, or the area of a part of the first through holes 410 may be selected to be different from the projected areas of other first through holes 410.
In other preferred embodiments, the projected areas of any two third through holes 430 on the substrate 10 may be the same or different, for example, the projected areas of the third through holes 430 on the substrate 10 may gradually increase or decrease along the first direction, or the area of a part of the third through holes 430 may be selected to be different from the projected areas of other third through holes 430.
According to a sixth embodiment of the invention, to achieve R1＞R2＞R3In a preferred embodiment, the above stepsStep S2 includes:
the hole structure 40 is formed in the first region 110 and is denoted as a first through hole 410, so that the distance between any two adjacent first through holes 410 is L1The area of the first through hole 410 projected on the substrate 10 is S1；
A hole structure 40 is formed in the second area 120 and is denoted as a second via 420, such that a distance between any two adjacent second vias 420 is L2The area projected on the substrate 10 by the second through hole 420 is S2；
A hole structure 40 is formed in the third region 130 and is denoted as a third through hole 430, so that the distance between any two adjacent third through holes 430 is L3The area projected on the substrate 10 by the third through hole 430 is S3；
The distance between any two adjacent second through holes 420 gradually changes, and the area of the projection of each second through hole on the substrate gradually changes. In other embodiments, L1，L2，L3And R1，R2，R3The relationship between can be defined by itself, e.g. L1＜L2＝L3，R1＜R2＝R3，L1＝L2＜L3，R1＝R2＜R3，L1＜L3＝L2，R1＜R3＝R2，L2＜L3＝L1，R2＜R3＝R1And the like in any size combination.
In the above preferred embodiment, by adjusting the distances between adjacent pore structures 40 in the first region 110, the second region 120 and the third region 130, and simultaneously adjusting the projection sizes of the pore structures 40 in the first region 110, the second region 120 and the third region 130 on the substrate 10, the distribution of the pore structures in the transition from the core array region to the step region is more gradual, so as to more effectively avoid the possibility of generating an inclined point at the bottom of the gate spacer during the etching process.
In the above preferred embodiment, the projected areas of any two second through holes 420 on the substrate 10 may be mutually matchedThe same or different, and the projected areas of any two first through holes 410 on the substrate 10 may be the same or different; in order to make the distribution of the hole structure more gradual in the transition from the core array region to the step region, it is more preferable that the distance between any two adjacent second through holes 420 in the first direction is LminGradual change to LmaxAnd L is1≤Lmin＜Lmax≤L3While the area projected on the substrate 10 by each second through hole 420 is represented by SmaxGradually change to SminAnd S is1≥Smax＞Smin≥S3. It is also possible to select a distance between a part of the second through holes 420 and the adjacent second through holes 420 to be different from a distance between other adjacent second through holes 420, and to select a part of the second through holes 420 and other second through holes to have different areas on the substrate 10.
In other preferred embodiments, the distances between any two adjacent first through holes 410 may be equal or unequal, and the projected areas of any two first through holes 410 on the substrate 10 may be the same or different. For example, the distance between any two adjacent first through holes 410 may gradually increase or decrease along the first direction, and the area of the projection of each first through hole 410 on the substrate 10 gradually increases or decreases, or a distance between a part of the first through holes 410 and the adjacent first through holes 410 may be different from a distance between other adjacent first through holes 410, and an area of a part of the first through holes 410 is different from a projection area of other first through holes 410.
In other preferred embodiments, the distances between any two adjacent third through holes 430 may be equal or unequal, and the projected areas of any two third through holes 430 on the substrate 10 may be the same or different. For example, the distance between any two adjacent third through holes 430 may gradually increase or decrease along the first direction, and the area of the projection of each third through hole 430 on the substrate 10 gradually increases or decreases, or a distance between a part of the third through holes 430 and the adjacent third through holes 430 may be different from the distance between other adjacent third through holes 430, and the area of a part of the third through holes 430 is different from the area of the projection of other third through holes 430.
After the step S2, the manufacturing method of the present invention may further include the steps of: forming gate spacers 50 in the stacked structure 20 such that the gate spacers 50 extend from the core array region to the step region and through to the substrate 10; a conductive semiconductor layer is formed in the gate spacer 50.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
according to the three-dimensional storage structure, the stacked structure is divided into the regions, and the density of the pore structure in each region is respectively adjusted, so that the distribution of the pore structure in the transition from the core array region to the step region is more gradual, the possibility of generating an inclined point at the bottom of the gate spacer groove in the process of forming the gate spacer groove in the three-dimensional storage structure is effectively reduced or even avoided, and the performance of the three-dimensional storage structure is improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (34)
1. A three-dimensional memory structure, comprising:
the device comprises a substrate and a stacked structure, wherein the stacked structure is positioned on the substrate;
the stacked structure comprises a core array area and a step area positioned on at least one side of the core array area, the three-dimensional storage structure further comprises a hole structure positioned in the stacked structure and penetrating to the substrate, the hole structure comprises a plurality of channel holes, and a storage structure is arranged in each channel hole;
dividing the stacked structure into a first region, a second region and a third region sequentially arranged along a first direction;
the first direction is a direction pointing from the core array region to the step region;
the second region comprises a portion of the core array region and a portion of the step region;
the pore structures are distributed in the first region, the second region and the third region, and the density of the pore structures in the first region is defined as R1The density of the pore structure in the second region is R2The density of the pore structure in the third region is R3，R1And R2And R3Are not all the same as each other,
the density of the pore structure in the second region in the first direction is represented by RmaxGradation to RminAnd R is1≥Rmax＞Rmin≥R3。
2. The three-dimensional memory structure of claim 1, wherein R is1>R2>R3。
3. The three-dimensional memory structure according to claim 1, wherein the hole structure in the first region is defined as a first through hole, the hole structure in the second region is defined as a second through hole, the hole structure in the third region is defined as a third through hole, projections of the first through hole, the second through hole and the third through hole on the substrate have the same size, and a pitch of any two adjacent first through holes is defined as L1The distance between any two adjacent second through holes is L2The distance between any two adjacent third through holes is L3，L1、L2And L3Are not identical.
4. The three-dimensional memory structure of claim 3, wherein L is1＜L2＜L3。
5. The three-dimensional memory structure of claim 4,
in the first direction, the distance between any two adjacent second through holes is equal;
in the first direction, the pitch of the first through holes gradually changes and/or the pitch of the third through holes gradually changes.
6. The three-dimensional memory structure of claim 5,
in the first direction, the distance between any two adjacent second through holes gradually changes.
7. The three-dimensional memory structure of claim 6,
in the first direction, the distance between any two adjacent second through holes is LminGradual change to LmaxAnd L is1＜Lmin＜Lmax＜L3。
8. The three-dimensional memory structure of claim 1, wherein the hole structure in the first region is defined as a first through hole, the hole structure in the second region is defined as a second through hole, the hole structure in the third region is defined as a third through hole, a pitch of any two adjacent first through holes, a pitch of any two adjacent second through holes, and a pitch of any two adjacent third through holes are the same, and a projected area of the first through holes on the substrate is defined as S1The projection area of the second through hole on the substrate is S2The projection area of the third through hole on the substrate is S3，S1、S2And S3Are not identical.
9. The three-dimensional memory structure of claim 8, wherein S is1＞S2＞S3。
10. The three-dimensional memory structure of claim 9,
the projected areas of any two second through holes on the substrate are the same;
in the first direction, the area of the projection of the first through hole on the substrate and/or the area of the projection of the third through hole on the substrate gradually changes.
11. The three-dimensional memory structure of claim 10,
in the first direction, the projection area of each second through hole on the substrate is gradually changed.
12. The three-dimensional memory structure of claim 11,
in the first direction, the projection area of each second through hole on the substrate is SmaxGradually change to SminAnd S is1＞Smax＞Smin＞S3。
13. The three-dimensional memory structure of claim 1,
defining the hole structure in the first region as a first through hole, the hole structure in the second region as a second through hole, and the hole structure in the third region as a third through hole;
defining the distance between any two adjacent first through holes as L1The distance between any two adjacent third through holes is L3In the first direction, the distance between any two adjacent second through holes gradually changes, and the area of the projection of the first through hole on the substrate is defined as S1The projection area of the third through hole on the substrate is S3And in the first direction, the projection area of each second through hole on the substrate is gradually changed.
14. The three-dimensional memory structure of claim 13,
defining the interval of each second trench through hole from LminGradual change to LmaxThe area of projection of each second through hole on the substrate is SmaxGradually change to SminWherein L is1＜Lmin＜Lmax＜L3，S1＞Smax＞Smin＞S3。
15. The three-dimensional memory structure of claim 13,
in the first direction, the distance between the first through holes is gradually changed and/or the distance between the third through holes is gradually changed;
in the first direction, the area of the projection of each first through hole on the substrate is gradually changed and/or the area of the projection of each third through hole on the substrate is gradually changed.
16. The three-dimensional memory structure of claim 1 or 2, wherein the hole structure further comprises a dummy channel hole.
17. The three-dimensional memory structure of claim 1 or 2, further comprising a gate spacer trench extending from the core array region to the step region and through to the substrate, the gate spacer trench having a conductive semiconductor layer disposed therein.
18. A method for manufacturing a three-dimensional storage structure is characterized by comprising the following steps:
s1, forming a stacked structure on the substrate, wherein the stacked structure comprises a core array area and a step area positioned on at least one side of the core array area;
s2, dividing the stacked structure into a first region, a second region and a third region arranged in sequence along a first direction, wherein the first direction is a direction pointing from the core array region to the step region, the second region comprises a part of the core array region and a part of the step region, and the first region, the second region and the step region are arranged in sequence along a first direction, the first direction is a direction pointing from the core array region to the step region, the second region comprises a part of the core array region and a part of the step region, and the step region is arranged in the first directionA plurality of hole structures penetrating through the substrate are formed in the first region, the second region and the third region, each hole structure comprises a plurality of channel holes, and the density of the hole structures in the first region is defined as R1The density of the pore structure in the second region is R2The density of the pore structure in the third region is R3，R1And R2And R3Are not identical;
s3, forming a storage structure in the channel hole,
the hole structures are formed in the second region such that the density of the hole structures in the second region in the first direction is represented by RmaxGradation to RminAnd R is1＞Rmax＞Rmin＞R3。
19. The method of claim 18, wherein R is1>R2>R3。
20. The method according to claim 18, wherein the hole structure is formed in the first region and is denoted as a first through hole, so that a distance between any two adjacent first through holes is L1Forming the hole structure in the second region and marking as a second through hole, so that the distance between any two adjacent second through holes is L2Forming the hole structure in the third region and marking as a third through hole, so that the distance between any two adjacent third through holes is L3Projections of the first through hole, the second through hole and the third through hole on the substrate have the same size, L1、L2And L3Are not identical.
21. The method of claim 20, wherein L is1＜L2＜L3。
22. The method of manufacturing according to claim 21,
forming the second through holes in the second region so that pitches of any two adjacent second through holes in the first direction are equal;
forming the first through holes in the first region, and forming the third through holes in the third region, so that the pitch of the first through holes is gradually changed and/or the pitch of the third through holes is gradually changed in the first direction.
23. The method of manufacturing according to claim 22,
and forming the second through holes in the second area, so that the distance between any two adjacent second through holes in the first direction is gradually changed.
24. The method of manufacturing according to claim 23,
the second through holes are formed in the second area, so that the distance between any two adjacent second through holes in the first direction is LminGradual change to LmaxAnd L is1＜Lmin＜Lmax＜L3。
25. The method according to claim 18, wherein the hole structure is formed in the first region and is denoted as a first through hole, so that a projection area of the first through hole on the substrate is S1Forming the hole structure in the second area and marking as a second through hole so that the projection area of the second through hole on the substrate is S2Forming the hole structure in the third region and recording the hole structure as a third through hole so that the projection area of the third through hole on the substrate is S3，S1、S2And S3The distance between any two adjacent first through holes, the distance between any two adjacent second through holes and the distance between any two adjacent third through holes are not completely the same.
26. The method of claim 25, wherein S is1＞S2＞S3。
27. The method of manufacturing of claim 26,
forming the second through holes in the second area, so that the projected areas of any two second through holes on the substrate are the same;
and forming the first through hole in the first region, and forming the third through hole in the third region, so that the area of the first through hole projected on the substrate and/or the area of the third through hole projected on the substrate in the first direction are gradually changed.
28. The method of manufacturing according to claim 27,
and forming the second through holes in the second area so as to gradually change the projection area of each second through hole on the substrate in the first direction.
29. The method of manufacturing of claim 28,
the second through holes are formed in the second region, so that the projection area of each second through hole on the substrate in the first direction is SmaxGradually change to SminAnd S is1＞Smax＞Smin＞S3。
30. The method of manufacturing according to claim 18, wherein the step S2 includes:
forming the hole structure in the first area and marking as a first through hole, so that the distance between any two adjacent first through holes is L1The projection area of the first through hole on the substrate is S1；
The hole structure is formed in the second region and is denoted as a second via,so that the distance between any two adjacent second through holes is L2The projection area of the second through hole on the substrate is S2；
Forming the hole structure in the third region and marking as a third through hole, so that the distance between any two adjacent third through holes is L3The projection area of the third through hole on the substrate is S3；
The distance between any two adjacent second through holes is gradually changed, and the area of the projection of each second through hole on the substrate is gradually changed.
31. The method of manufacturing of claim 30,
defining the interval of each second trench through hole from LminGradual change to LmaxThe area of projection of each second through hole on the substrate is SmaxGradually change to SminWherein L is1＜Lmin＜Lmax＜L3，S1＞Smax＞Smin＞S3。
32. The method of manufacturing of claim 31,
the first through holes are formed in the first area, the third through holes are formed in the third area, so that the distance between the first through holes and/or the distance between the third through holes gradually change in the first direction, and the area of the projection of the first through holes on the substrate gradually changes in the first direction and/or the area of the projection of the third through holes on the substrate gradually changes in the first direction.
33. The method of manufacturing according to claim 18 or 19,
the step S2 further includes: forming a plurality of dummy channel holes penetrating to the substrate in each of the first, second, and third regions;
the step S3 further includes: forming a dummy channel material layer in the dummy channel hole.
34. The method of manufacturing of claim 18 or 19, wherein after the step S2, the method further comprises the steps of:
forming gate spacers in the stacked structure such that the gate spacers extend from the core array region to the step region and through to the substrate;
and forming a conductive semiconductor layer in the gate isolation groove.
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| CN111755454B (en) * | 2020-07-03 | 2021-07-06 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN112420724B (en) * | 2020-11-18 | 2021-09-28 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| CN112670294B (en) * | 2020-12-22 | 2024-04-09 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
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