CN100517656C - Method of manufacturing non-volatile memory device - Google Patents
Method of manufacturing non-volatile memory device Download PDFInfo
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- CN100517656C CN100517656C CNB2007100007104A CN200710000710A CN100517656C CN 100517656 C CN100517656 C CN 100517656C CN B2007100007104 A CNB2007100007104 A CN B2007100007104A CN 200710000710 A CN200710000710 A CN 200710000710A CN 100517656 C CN100517656 C CN 100517656C
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Abstract
A method for making nonvolatile memory device includes following steps: a step of providing semiconductor substrate which forms tunnel insulation layer and charge storage layer in active area and forms separating layer in separating area; a step of forming dielectric layer on the semiconductor substrate including the tunnel insulation layer and the charge storage layer, and etching the dielectric layer and the charge storage layer and a part of the tunnel insulation layer in order to bare the semiconductor substrate for forming contact holes; a step of forming a first node area in the bare semiconductor substrate; a step of forming conductive layer for controlling grid on the semiconductor substrate of the first node area thereby to filling the contact holes; a step of patterning the conductive layer, the dielectric layer and the charge storage layer to form selection wire and character wire, and simultaneously forming contact embolization on the first node area.
Description
The cross reference of related application
The application requires the priority of korean patent application 10-2006-48221 that submits in the korean patent application 10-2006-17234 that submitted on February 22nd, 2006, on May 29th, 2006 and the korean patent application 10-2006-121444 that submitted on December 4th, 2006, and these korean patent applications are incorporated this paper into through reference in its entirety.
Technical field
The present invention relates to nonvolatile semiconductor memory member, relate more specifically to a kind of method of making nonvolatile semiconductor memory member, it can be applied to the manufacturing process of NAND flash memory.
Background technology
A typical types of nonvolatile semiconductor memory member is a flash memory.Carried out active research for silicon/oxide/nitride/oxide/silicon (SONOS) type flash memory, wherein the floating grid of flash memory forms with insulating material, for example form, rather than use electric conducting material to form such as polysilicon with nitride layer.
SONOS type flash memory generally has the structure that stacks gradually oxide skin(coating), nitride layer, oxide skin(coating) and polysilicon layer on Semiconductor substrate.Following oxide skin(coating) is as tunnel insulation layer, and nitride layer is as the electric charge storage layer that is used for store charge, i.e. floating grid.Oxide skin(coating) is used to provide the insulation between electric charge storage layer and the control grid on forming on the nitride layer.
Fig. 1 is the sectional view of traditional flash memory device.
Referring to Fig. 1, in traditional flash memory, on Semiconductor substrate 100, form tunnel insulation layer 102; Be used to control the drain selection line SSL that comprises electric charge storage layer 104, dielectric layer 106 and conductive layer 112 of grid; The word line (not shown); With drain electrode selection wire (not shown).Interface 110 forms between word line and selection wire.The source region that forms between drain selection line SSL becomes public source CS.Insulating barrier 118 is formed on the whole surface of resulting structures.Insulating barrier on the etching public source CS, and fill with electric conducting material in the zone after the etching, public source embolism CSP formed.
In common flash memory, charge storage layer 104 can form with polysilicon, and in the flash memory of SONOS structure, charge storage layer 104 can form with nitride layer.Similarly, in common flash memory, dielectric layer 106 can form with the ONO structure, and in the flash memory of SONOS structure, dielectric layer 106 can form with alumina layer.In Fig. 1, the hard mask of Reference numeral 114 expressions.
In flash memory, the drain electrode (not shown) forms between drain electrode selection wire (not shown), and public source CS forms between drain selection line SSL.Therefore, along with the device integrated level increases, in the process that forms source electrode contact embolism or drain electrode contact embolism such as public source embolism, be difficult to guarantee overlapping (overlay) tolerance limit with adjacent selection wire.Also be difficult to guarantee the good puncture voltage between drain electrode selection wire and drain electrode contact embolism.Therefore, by broadening, make the integrated level that is difficult to improve device in the distance of drain electrode between the selection wire.
In addition, in order to form public source embolism (CSP), must comprise the several processes of chemico-mechanical polishing (CMP).Simultaneously, for the bit line electric insulation that makes public source embolism CSP and formed afterwards, must after forming public source embolism CSP, form interlayer insulating film in addition.Because the interpolation of described interlayer insulating film makes that the degree of depth of the drain contact hole of formation increases subsequently.If the degree of depth of drain contact hole is increased, then reduced the edge of contact etch technology, cause damage to the contact hole upper surface, between adjacent contact embolism, produce bridge.In addition, the contact hole bottom width diminishes, and perhaps keeps described insulating barrier, and therefore drain electrode contact embolism and drain electrode may not can be electrically connected.In order to prevent this problem, must reduce the thickness of interlayer insulating film.But, when electrical connection between consideration bit line and public source embolism CSP or parasitic capacitance, be difficult to reduce the thickness of interlayer insulating film.
Summary of the invention
The invention provides a kind of method of making nonvolatile semiconductor memory member, wherein, part at public source embolism that forms on the public source or the drain electrode contact embolism that forms in drain electrode forms with word line and selection wire, therefore prevented to aim at the generation of mistake, reduce processing step, and improved the reliability of technology.
In one embodiment, a kind of method of making nonvolatile semiconductor memory member may further comprise the steps: form tunnel insulation layer on Semiconductor substrate, electric charge storage layer and dielectric layer, etching part dielectric layer, electric charge storage layer and tunnel insulation layer are to form the contact hole that exposes Semiconductor substrate, in the Semiconductor substrate that is exposed, form first interface, on described dielectric layer, form the control grid to form the unit grid, on first interface, form the control grid to fill described contact hole, make conductive layer, dielectric layer and electric charge storage layer patterning are with formation selection wire and word line, and the contact embolism.
In another embodiment, a kind of method of making nonvolatile semiconductor memory member may further comprise the steps: form tunnel insulation layer comprising on the Semiconductor substrate of electric charge storage layer, electric charge storage layer and dielectric layer, etching part dielectric layer, electric charge storage layer and tunnel insulation layer form the contact hole in common source region and the drain region, in Semiconductor substrate, form first interface to expose described contact hole, forming the control grid on the described dielectric layer to form the unit grid and on first interface, to form the control grid to fill described contact hole, make the control grid, dielectric layer and electric charge storage layer patterning are with formation selection wire and word line, and public source embolism and drain electrode embolism.
Description of drawings
Fig. 1 is the sectional view of traditional flash memory device.
Fig. 2 A to 2G is the sectional view of explanation according to the method for the manufacturing flash memory of first embodiment of the present invention.
Fig. 3 A to 3G is the sectional view of explanation according to the method for the manufacturing flash memory of second embodiment of the present invention.
Embodiment
Describe according to specific embodiments of the present invention below with reference to accompanying drawing.
Fig. 2 A to 2G is the sectional view of explanation according to the method for the manufacturing flash memory of first embodiment of the present invention.
With reference to figure 2A, on Semiconductor substrate 200, form tunnel insulation layer 202 and electric charge storage layer 204 successively.In common flash memory, electric charge storage layer 204 can form with polysilicon, and in the flash memory of SONOS structure, electric charge storage layer 204 preferably forms with nitride layer.
In common flash memory, on electric charge storage layer 204, form and separate the mask (not shown).By adopting the etch process etching charge of separating mask to store layer 204, tunnel insulation layer 202 and Semiconductor substrate 200, therefore in separated region, form groove.Described groove uses filling insulating material to form separate layer.Remove then and separate mask.
Simultaneously, in the flash memory of SONOS structure, before forming tunnel insulation layer 202 and electric charge storage layer 204, can in the marker space, form the separate layer (not shown).In addition, can further in the (not shown) of neighboring area, be formed for forming transistorized gate insulator (not shown) and grid conducting layer (not shown) and separate layer.Fig. 2 A is the sectional view of the active area between the marker space.Therefore, although form separate layer earlier, active area is also invisible.
Referring to Fig. 2 B, on the whole surface of the structure that comprises electric charge storage layer 204 of gained, form dielectric layer 206.The function of dielectric layer 206 is to make the conductive layer and electric charge storage layer 204 electric insulations that are used to control grid that form in the subsequent process.In common flash memory, dielectric layer 206 can have the ONO structure, and in the flash memory of SONOS structure, dielectric layer 206 preferably forms with alumina layer.
Simultaneously, in the flash memory of SONOS structure, on dielectric layer 206, form cover layer 207.When the neighboring area (not shown) is removed the etch process of a part of dielectric layer 206, cover layer 207 is as etching mask.Cover layer 207 can form with polysilicon.Therefore, in common flash memory, the step that forms cover layer 207 can be omitted.
Referring to Fig. 2 C, remove cover layer 207, dielectric layer 206, electric charge storage layer 204 and the tunnel insulation layer 202 in the zone that wherein will form contact embolism (public source embolism or drain electrode contact embolism), form contact hole 208.Contact hole 208 can have wide or narrow or identical with it width of width than the contact embolism that will form in subsequent process.Thereby a part of Semiconductor substrate 200 is exposed.
Then, implanted dopant in the Semiconductor substrate 200 of described exposure forms first interface 210.First interface 210 is preferred by injecting the formation of N type impurity.Preferably inject N type impurity, so that obtain ohmic contact when in subsequent process, forming the contact embolism with metal level with high concentration.The impurity that is used to form first interface 210 and injects spreads to both sides, and therefore the width in first interface 210 becomes greater than the width of contact hole 208.If first interface 210 the public source embolism will be formed at wherein the zone in formation, then first interface 210 becomes the part of public source.If the formation in drain electrode contact embolism will be formed at wherein zone of first interface 210, then first interface 210 becomes the part of described drain electrode.This will be described in more detail below.
Referring to Fig. 2 D, on the whole surface of the structure that comprises first interface 210 of gained, be formed for controlling the conductive layer 212 and the hard mask pattern 214 of grid successively.Conductive layer 212 preferably has the stepped construction of polysilicon layer and silicide layer, perhaps can only use metal level to form.Under latter event, described metal level preferably forms with tungsten.
Referring to Fig. 2 E, adopt hard mask pattern 214 to make conductive layer 212, cover layer 207, dielectric layer 206 and electric charge storage layer 204 patternings by etch process, thereby form contact embolism and drain selection line SSL between drain electrode selection wire (not shown), a plurality of word line WL0 to WL2 (for simplicity, only showing each three word line) and the selection wire simultaneously.On first interface 210, form described contact embolism.At this moment, in Fig. 2 C, if first interface 210 forms in the zone that will form the public source embolism, then this contact embolism becomes public source embolism CSP.In addition, if first interface 210 forms in the zone that will form drain electrode contact embolism, then this contact embolism becomes drain electrode contact embolism.
Fig. 2 E represents the example that wherein first interface 210 forms and public source embolism CSP forms on first interface 210 in the zone that will form the public source embolism.Public source embolism CSP (or drain electrode contact embolism) can have the width greater than contact hole width (referring to 208 among Fig. 2 C).The part that can comprise in this case, electric charge storage layer 204 and dielectric layer 206 in the edge of public source embolism CSP.If the width of public source embolism CSP is less than the width of contact hole, then public source embolism CSP does not comprise electric charge storage layer 204 and dielectric layer 206, but only comprises conductive layer 212.
Referring to Fig. 2 F, utilize in Semiconductor substrate 200 zones of ion implantation between word line WL0 to WL2, selection wire SSL (drain electrode selection wire (not shown)) and public source embolism CSP and form second interface 216.Second interface 216 is preferred by injecting the formation of N type impurity.Second interface 216 between selection wire becomes public source CS or drain electrode (not shown) with first interface 210.
Referring to Fig. 2 G, on the whole surface of Semiconductor substrate 200, form interlayer insulating film 218.As mentioned above, in the present embodiment, public source embolism CSP or drain electrode contact embolism form with word line WL0 to WL2 and selection wire.Therefore, can prevent contingent aligning mistake in the process that forms public source embolism CSP subsequently.
In addition, in the prior art,, formed first interlayer insulating film, and, formed second interlayer insulating film then in order to form drain electrode contact embolism in order to form the public source embolism.Yet, in the present embodiment,, therefore can only be formed for forming the interlayer insulating film of drain electrode contact embolism because the public source embolism forms with word line and selection wire.So, can reduce processing step, the gross thickness attenuation of interlayer insulating film can be made, and the etched thickness when forming drain contact hole can be reduced.
Fig. 3 A to 3G is the sectional view of explanation according to the method for the manufacturing nonvolatile semiconductor memory member of second embodiment of the present invention.
Referring to Fig. 3 A, on Semiconductor substrate 300, form tunnel insulation layer 302 and electric charge storage layer 304 successively.In common flash memory, electric charge storage layer 304 usefulness polysilicons form, and in the flash memory of SONOS structure, electric charge storage layer 304 preferably forms with nitride layer.
In common flash memory, on electric charge storage layer 304, form and separate the mask (not shown).Adopt and separate mask, thereby in the marker space, form groove by etch process etching charge storage layer 304, tunnel insulation layer 302 and Semiconductor substrate 300.With described groove filling insulating material, form separate layer.Remove then and separate mask.
Simultaneously, in the flash memory of SONOS structure, before forming tunnel insulation layer 302 and electric charge storage layer 304, preferably in the marker space, form the separate layer (not shown).In addition, preferably further in the (not shown) of neighboring area, be formed for forming transistorized gate insulator (not shown) and grid conducting layer (not shown) and separate layer.Fig. 3 A is the sectional view of the active area between described marker space.Therefore, although separate layer forms earlier, active area also is sightless.
Referring to Fig. 3 B, on the whole surface of the structure that comprises electric charge storage layer 304 of gained, form dielectric layer 306.The function of dielectric layer 306 is the conductive layer and electric charge storage layer 304 electric insulations that are used to control grid that make forming in subsequent process.In common flash memory, dielectric layer 306 can have the ONO structure, and in the flash memory of SONOS structure, dielectric layer 306 preferably forms with alumina layer.
Simultaneously, in the flash memory of SONOS structure, on dielectric layer 306, form cover layer 307.Removing the etch process of a part of dielectric layer 306 from the neighboring area (not shown), cover layer 307 is as etching mask.Cover layer 307 can form with polysilicon.Therefore, in common flash memory, the step that forms cover layer 307 can be omitted.
Referring to Fig. 3 C, remove cover layer 307, dielectric layer 306, electric charge storage layer 304 and the tunnel insulation layer 302 in the zone that wherein will form contact embolism (public source embolism or drain electrode contact embolism), form contact hole 308a and 308b.Each of contact hole 308a and 308b can have than wide or narrow or identical with it width of the width that contacts embolism that will form in subsequent process.Thereby a part of Semiconductor substrate 300 is exposed.
Then, implanted dopant in the Semiconductor substrate 300 that is exposed forms first interface 310a and the 310b.Each of the first interface 310a and 310b preferably forms by injecting N type impurity.Preferably inject N type impurity, so that obtain ohmic contact when in subsequent process, forming the contact embolism with metal level with high concentration.Spread to both sides for forming the impurity that the first interface 310a and 310b inject, therefore the width of the first interface 310a and 310b becomes greater than the width of contact hole 308a and 308b.The first interface 310a that forms in the public source zone becomes the part of public source, and the first interface 310b that forms in the drain region becomes the part of described drain electrode.This will be described in more detail below.
Referring to Fig. 3 D, on the whole surface of the structure that comprises the first interface 310a and 310b of gained, be formed for controlling the conductive layer 312 and the hard mask pattern 314 of grid successively.Conductive layer 312 preferably has the stepped construction of polysilicon layer and silicide layer, perhaps can only use metal level to form.Under latter event, described metal level preferably forms with tungsten.
Make conductive layer 312, cover layer 307, dielectric layer 306 and electric charge storage layer 304 patternings by the etch process that adopts hard mask pattern 314, thereby form drain electrode selection wire DSL, a plurality of word line WL0 to WLn and drain selection line SSL.At this moment, on the first interface 310a between the drain selection line SSL, form public source embolism CSP.On the first interface 310b between the drain electrode selection wire DSL, also form drain electrode contact embolism DCP.In the first embodiment, the example that wherein forms public source embolism CSP or drain electrode contact embolism has been described.But Fig. 3 E has described and has formed public source embolism CSP contacts embolism DCP with drain electrode example simultaneously.
The width of public source embolism CSP or drain electrode contact embolism DCP can be greater than the width of each contact hole (referring to 308a among Fig. 3 C and 308b).In this case, the edge at public source embolism CSP or drain electrode contact embolism DCP can comprise that Partial charge stores layer 204 and dielectric layer 206.If the width of public source embolism CSP or drain electrode contact embolism DCP is less than the width of contact hole, then public source embolism CSP or drain electrode contact embolism DCP do not comprise electric charge storage layer 304 and dielectric layer 306, but public source embolism CSP or drain electrode contact embolism DCP only comprise conductive layer 312.
Then, preferably utilize formation second interface 316 in Semiconductor substrate 230 zones of ion implantation between word line WL0 to WLn, selection wire SSL and DSL, public source embolism CSP and drain electrode contact embolism DCP.Second interface 316 is preferred by injecting the formation of N type impurity.Second interface 316 that forms between selection wire SSL becomes public source CS with the first interface 310a.In addition, second interface 316 that forms between drain electrode contact embolism DCP becomes drain electrode with the first interface 310b.
Referring to Fig. 3 F, on the whole surface of the resulting structures that comprises Semiconductor substrate 300, form interlayer insulating film 318.In order to reduce the step that produces by following structure, preferably on interlayer insulating film 318, carry out chemico-mechanical polishing (CMP) process.
Referring to Fig. 3 G, after the interlayer insulating film 318 and hard mask pattern 314 on part removal drain electrode contact embolism DCP, fill the part of being removed with electric conducting material, drain electrode contacts embolism 320 in the formation.Forming the bit line 322 that is connected to drain electrode contact embolism on the interlayer insulating film 318.
As mentioned above, in the present embodiment, public source embolism CSP contacts embolism DCP with drain electrode and forms with word line WL0 to WLn and selection wire DSL and SSL.Therefore, can prevent contingent aligning mistake in the process that forms public source embolism CSP or drain electrode contact embolism DCP subsequently.
In addition, in the prior art,, formed first interlayer insulating film, and, formed second interlayer insulating film then in order to form drain electrode contact embolism in order to form the public source embolism.Yet in the present embodiment, the public source embolism forms with word line and selection wire.Therefore can only be formed for forming the interlayer insulating film 318 of drain electrode contact embolism.So, can reduce processing step, can reduce the gross thickness of interlayer insulating film, and the etched thickness can reduce on forming drain contact hole the time.
As mentioned above, according to the present invention, form with word line and selection wire at public source embolism that forms on the public source or the part drain electrode contact embolism that in drain electrode, forms.Therefore, can prevent to aim at the generation of mistake, reduce the quantity of processing step, and can improve the reliability of process.
Disclosed embodiment of the present invention are illustratives and nonrestrictive.Various replacements and etc. simultaneously possible.Other increase, minimizing or improvement all fall within the scope of the appended claims.
Claims (19)
1. method of making nonvolatile semiconductor memory member, this method may further comprise the steps:
On Semiconductor substrate, form tunnel insulation layer, electric charge storage layer and dielectric layer;
Etching part insulating barrier, electric charge storage layer and tunnel insulation layer are to form the contact hole that exposes described Semiconductor substrate;
In the Semiconductor substrate that is exposed, form first interface;
The conductive layer that is formed for controlling grid on described dielectric layer is formed for controlling the conductive layer of grid to fill described contact hole to form the unit grid on first interface;
Make conductive layer, dielectric layer and electric charge storage layer patterning with formation selection wire and word line, and the contact embolism.
2. the method for claim 1 further comprises following steps: after forming described contact embolism, form second interface in the Semiconductor substrate between word line, selection wire and contact embolism.
3. the method for claim 2, the impurity concentration in wherein said first interface is higher than the impurity concentration in described second interface.
4. the method for claim 1, it is included in and forms described first interface in the common source region, and wherein said contact embolism becomes the public source embolism.
5. the method for claim 1, it is included in and forms described first interface in the drain region, and wherein said contact embolism becomes drain electrode contact embolism.
6. the method for claim 1, it comprises with polysilicon and forms electric charge storage layer.
7. the method for claim 1, it comprises with nitride layer and forms electric charge storage layer.
8. the process of claim 1 wherein that described dielectric layer has the ONO structure.
9. the method for claim 1, it comprises with alumina layer and forms dielectric layer.
10. method of making nonvolatile semiconductor memory member, this method may further comprise the steps:
Form tunnel insulation layer, electric charge storage layer and dielectric layer on the Semiconductor substrate of electric charge storage layer comprising;
Etching part dielectric layer, electric charge storage layer and tunnel insulation layer form the contact hole in common source region and the drain region;
In Semiconductor substrate, form first interface to expose described contact hole;
Be formed for controlling the conductive layer of grid on the described dielectric layer to form the unit grid and on first interface, to be formed for controlling the conductive layer of grid to fill described contact hole;
Make control grid, dielectric layer and electric charge storage layer patterning with formation selection wire and word line, and public source embolism and drain electrode embolism.
11. the method for claim 10 further comprises following steps: after forming described public source embolism and drain electrode contacts embolism, form second interface in the Semiconductor substrate between word line, selection wire, public source embolism and drain electrode contact embolism.
12. the method for claim 11, the impurity concentration in wherein said first interface is higher than the impurity concentration in described second interface.
13. the method for claim 10 further comprises:
After forming described public source embolism and described drain electrode contact embolism,
Form interlayer insulating film beyond the Great Wall at unit grid, public source embolism and drain electrode contact bolt;
Form second contact hole to expose described drain electrode contact embolism; With
Fill second contact hole with electric conducting material.
14. the method for claim 10, it comprises with polysilicon and forms described electric charge storage layer.
15. the method for claim 10, it comprises with nitride layer and forms described electric charge storage layer.
16. the method for claim 10, wherein said dielectric layer has the ONO structure.
17. the method for claim 10, it comprises with alumina layer and forms dielectric layer.
18. the method for claim 10, it further is included in and forms tectal step on the described dielectric layer.
19. the method for claim 18, it comprises with polysilicon and forms described cover layer.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060017234 | 2006-02-22 | ||
| KR20060017234 | 2006-02-22 | ||
| KR1020060048221 | 2006-05-29 | ||
| KR1020060121444 | 2006-12-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101026128A CN101026128A (en) | 2007-08-29 |
| CN100517656C true CN100517656C (en) | 2009-07-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2007100007104A Expired - Fee Related CN100517656C (en) | 2006-02-22 | 2007-01-10 | Method of manufacturing non-volatile memory device |
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| CN (1) | CN100517656C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101146872B1 (en) * | 2009-05-21 | 2012-05-17 | 에스케이하이닉스 주식회사 | Method for fabricating of Non-volatile memory device |
| CN104810370B (en) * | 2014-01-26 | 2018-04-13 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic device |
| KR102234799B1 (en) * | 2014-08-14 | 2021-04-02 | 삼성전자주식회사 | Semiconductor device |
| CN105514107B (en) * | 2014-09-22 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | Nonvolatile memory and preparation method thereof |
| US11235969B2 (en) * | 2018-10-30 | 2022-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS-MEMS integration with through-chip via process |
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