CN116053136A - Method for manufacturing semiconductor memory device - Google Patents

Abstract

The invention discloses a manufacturing method of a semiconductor memory device, which comprises the steps of performing a first doping process to form a well region in a semiconductor substrate, forming a word line in the semiconductor substrate, forming a bit line contact hole on the semiconductor substrate to expose a first active region, performing a doping process to the first active region exposed by the bit line contact hole, forming a bit line contact and a bit line on the semiconductor substrate, wherein the bit line contact is connected with the doped first active region, forming a spacer between the bit lines, defining a memory cell contact hole on the semiconductor substrate by the spacer and the bit line, exposing a second active region, performing a doping process to the second active region exposed by the memory cell contact hole, and forming a memory node contact in the memory cell contact hole, wherein the memory node contact is connected with the doped second active region.

Description

Manufacturing method of semiconductor memory device

technical field

This application is a divisional application with an invention title of "Method for Manufacturing a Semiconductor Storage Device". The original application date is July 31, 2020, and the application number is 202010760383.8.

The embodiments disclosed in the present invention relate to a manufacturing method of a semiconductor memory device, more specifically, it relates to a method for improving the gate-induced drain leakage (Gate Induced Drain Leakage, GIDL) problem of buried word lines A method for fabricating a semiconductor memory device.

Background technique

The Gate Induced Drain Leakage (GIDL) effect is the main off-state leakage current of MOSFET. This effect originates from when the MOSFET gate is off (the NMOS gate is connected to a negative voltage, the PMOS gate is connected to a positive voltage) and the drain region is connected to a voltage (the NMOS drain region is connected to a positive voltage, and the PMOS drain region is connected to a negative voltage). The energy band near the interface of the overlapping portion of the impurity diffusion layer and the gate is strongly bent, resulting in the formation of an inversion layer on the surface, and the depletion layer is very narrow, so that the energy band-energy band tunneling effect of band electrons and valence band holes occurs (Band-to-Band Tunneling), thus forming a drain leakage current. It is the main source of off-state leakage current and determines the lower limit of gate oxide thin oxide thickness. When the MOS has a thin gate, the GIDL will cause holes to damage the gate oxide layer through the tunneling effect or be trapped by the thin gate, which will cause the performance degradation of the MOSFET and reduce the reliability. In addition to the off-state leakage current, the gate-induced drain leakage current may also cause other adverse consequences, for example, holes may cause damage to the gate oxide layer through the tunneling effect or be trapped by the gate oxide layer, resulting in degradation of MOSFET performance, and Reduced reliability.

The traditional method of suppressing GIDL is mainly by increasing the thickness of the gate dielectric layer or diffusing the impurities at the drain terminal away from the gate. Obviously, in the semiconductor industry that pursues high integration, such solutions are not conducive to further shrinking devices, especially In terms of scaling of storage devices, it will also cause adverse effects such as other parasitic effects (such as hot carrier effect, hot carrier effect). Therefore, the industry still needs to actively develop other methods that can effectively improve GIDL problems.

Contents of the invention

In view of the gate-induced drain leakage (GIDL) problem that the above-mentioned semiconductor devices are prone to encounter, the present invention proposes a novel manufacturing method of a semiconductor storage device, which is characterized in that The source/drain implantation process is changed to be performed before the bit line contact and the storage node contact, so that the implantation process depth can be connected according to the buried word line groove depth, thereby improving the GIDL problem.

The object of the present invention is to provide a method for manufacturing a semiconductor storage device, the steps of which include providing a semiconductor substrate, performing a first doping process to form a well region in the semiconductor substrate, and after the formation of the well region, word lines are formed in the semiconductor substrate, after the word lines are formed, a bit line contact hole is formed on the semiconductor substrate to expose the first active region, the first active region exposed to the bit line contact hole performing a second doping process, and after the second doping process, forming a bit line contact and a bit line on the semiconductor substrate, wherein the bit line contact and the doped first active The source region is connected, a spacer is formed between the bit lines, the spacer and the bit line define a memory cell contact hole on the semiconductor substrate and expose a second active region, and the memory cell is contacted. A third doping process is performed on the second active region exposed by the hole, and after the third doping process, a storage node contact is formed in the memory cell contact hole, wherein the storage node contact connected with the doped second active region.

These and other objects of the present invention will become more apparent to the reader after reading the following detailed description of the preferred embodiment which is depicted in various drawings and drawings.

Description of drawings

This specification contains drawings and constitutes a part of this specification, so that readers can have a further understanding of the embodiments of the present invention. The drawings depict some embodiments of the invention and together with the description herein explain its principles. In these diagrams:

Fig. 1 depicts a plan view of a semiconductor memory device according to a preferred embodiment of the present case;

2 to 8 illustrate cross-sectional views of a semiconductor memory device during a manufacturing process according to a preferred embodiment of the present invention; and

FIG. 9 shows a flow chart of a manufacturing process of a semiconductor storage device according to a preferred embodiment of the present application.

It should be noted that all the illustrations in this manual are illustrations in nature. For the sake of clarity and convenience of illustration, the size and proportion of each component in the illustration may be exaggerated or reduced. Generally speaking, the The same reference symbols will be used to designate corresponding or similar component features in modified or different embodiments.

Wherein, the reference signs are explained as follows:

1a First active region

1b second active area

100 semiconductor substrate

101 device isolation layer

103 bit line contact holes

105 storage unit area

107 Wells

109 word line groove

111 gate insulating layer

113 Grid top cover layer

115 insulating interlayer

117 dielectric layer

119 hard mask layer

121 position wire contacts

125 Hard Mask Patterns

127 Partition wall

129 insulating layer

131 spacer

133 storage node contact hole

135 storage node contacts

ACT active area

BL bit line

D1 first direction

D2 second direction

D3 third direction

P1 first doping process

P2 second doping process

P3 third doping process

S1-S8 steps

WL word line

Detailed ways

Exemplary embodiments of the present invention will now be described in detail below, and the described features will be illustrated with reference to the accompanying drawings for readers to understand and achieve technical effects. Readers will understand that the description herein is by way of illustration only and is not intended to limit the present case. Various embodiments of the present application and various features that do not conflict with each other in the embodiments can be combined or rearranged in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present invention will be understood by those skilled in the art and are intended to be included within the scope of the present invention.

Readers should be able to easily understand that the meanings of "on", "on" and "above" in this case should be interpreted in a broad way so that "on" not only means "directly on "Something "on" also includes the meaning of "on" something with an intervening feature or layer in between, and "on" or "over" not only means "on" something or The meaning of "over" and may also include its meaning of "on" or "over" something without intervening features or layers in between (ie, directly on something).

In addition, spatial relative terms such as "under", "beneath", "lower", "above", "upper", etc. may be used herein for convenience of description to describe the separation of one component or feature from another. The relationship of one or more components or features as shown in the drawings.

As used herein, the term "substrate" refers to a material onto which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include a wide variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. Layers may extend horizontally, vertically and/or along inclined surfaces. A substrate can be a layer, can comprise one or more layers, and/or can have one or more layers thereon, above, and/or below. Layers may include multiple layers. For example, interconnect layers may include one or more conductor and contact layers (in which contacts, interconnects, and/or vias are formed) and one or more dielectric layers.

Please refer now to FIG. 1 , which shows a basic layout arrangement of a semiconductor memory device according to a preferred embodiment of the present invention. The semiconductor memory device of this application is formed on a semiconductor substrate 100 . The semiconductor substrate 100 has a memory cell area and a peripheral area around the memory cell area. The memory cell area is used to set memory cells of a semiconductor memory device, or called a storage node. A plurality of storage nodes are arranged in a matrix in the memory cell area and can store charges to generate different storage states. The peripheral area is used to set the peripheral circuits of the storage device, such as column decoder, column decoder, sense amplifier, or I/O control module. Since the inventive features of this case have nothing to do with the peripheral area, only components and features in the memory cell area are shown in the figure.

The semiconductor substrate 100 has a plurality of active regions ACT defined by the device isolation layer 101 . In an example, the active region ACT is strip-shaped and has a long axis extending toward the third direction D3. A plurality of active regions ACT are evenly arranged in a staggered manner on the entire substrate plane. A bit line contact hole 103 is formed in the middle of each active region ACT, and a doped region and a bit line contact of the semiconductor storage device will be formed in the bit line contact hole 103 in subsequent manufacturing processes. A plurality of word lines WL are embedded in the semiconductor substrate 100, which extend toward the first direction D1 and are arranged in parallel with each other at intervals. The angle between the first direction D1 and the third direction D3 is preferably between 45 degrees and 90 degrees. . In an example, the word line WL extends through both sides of the bit line contact hole 103 in the active region ACT, so that each active region ACT is divided into a region of the bit line contact hole 103 located in the middle of the active region ACT and a region of the bit line contact hole 103 located in the middle of the active region ACT. Memory cell regions 105 at both ends of the active region ACT. Subsequent manufacturing processes will form doped regions and storage node contacts on the memory cell region. A bit line structure is also formed on the semiconductor substrate 100 , which extend toward a second direction D2 perpendicular to the first direction D1 and are arranged in parallel with each other at intervals, which will not be shown in FIG. 1 for simplicity of illustration. In subsequent embodiments, the cross-sectional structure of the semiconductor storage device and the relative position and connection relationship of the components during the manufacturing process will be represented by using the line I-I' and the line II-II' in FIG. I' cuts through the long axis of the active region ACT along the third direction D3, and the line II-II' cuts through the device isolation layer 101 and the plurality of memory cell regions 105 of the active region ACT along the first direction D1.

After understanding the basic plane layout of the semiconductor storage device, the following embodiments will now illustrate the manufacturing method of the relevant components in the semiconductor storage device of the present invention according to the flow chart shown in Figure 9, and the method is in various stages and steps Clearer details and understanding can be obtained from the corresponding cross-sectional structures of FIGS. 2 to 8 , respectively.

First, please refer to FIG. 2 , the entire process of the semiconductor storage device of the present invention starts from a semiconductor substrate 100 . Such as silicon substrates, germanium substrates and/or silicon germanium substrates and other substrates. In step S1 , the semiconductor substrate 100 is firstly subjected to a first doping process P1 , such as an ion implantation process, to form various wells 107 inside. In the present invention, the well 107 can be used as the channel region of the buried channel array transistor. There may be more than one well 107 formed in the semiconductor substrate 100, which may be distributed in different depths of the substrate and have different conductivity types, such as p-type wells and/or n-type wells, and only one well 107 will be shown in the figure. The semiconductor substrate 100 defines a plurality of active regions ACT, such as strip-shaped active regions ACT as shown in FIG. 1 , and each active region ACT is separated by the surrounding device isolation layer 101 . In the process, separate active regions ACT can be formed by performing a photolithography process on the semiconductor substrate 100, and the recesses between the active regions ACT are filled with isolation materials, such as silicon oxide, to form device isolation. Layer 101. The depth of the device isolation layer 101 may correspond to the depth of the peak concentration of the well 107 .

Please refer to Figure 3 next. It should be noted that, in order to express specific parts more clearly, the cross-sectional structure in Fig. 3 is cut with the line I-I' along the long axis of the active region ACT in Fig. The relative relationship between the word line, the bit line and the doped region of the semiconductor storage device of the present invention. After forming the device isolation layer 101 and defining the active region ACT in the aforementioned step S1 , the next step S2 is to fabricate word lines in the semiconductor substrate 100 . The fabrication of word lines first includes forming word line trenches 109 in the semiconductor substrate 100 . As shown in FIG. 1, the word line WL to be formed in the semiconductor memory device of the present invention extends along the first direction D1 through the device isolation layer 101 and a plurality of active regions ACT. Therefore, it is shown in FIG. The word line trenches 109 in the active region ACT also have the word line trenches 109 formed in the device isolation layer 101 . Wherein, since the etching rate of the device isolation layer 101 made of silicon oxide is generally greater than the etching rate of the silicon active region ACT in the same etching process, it can be seen from the figure that the device isolation layer 101 is formed in the device isolation layer 101 The depth of the word line trench 109 is deeper than the depth of the word line trench 109 formed in the active region ACT.

Please refer to Figure 4 next. After the word line trench 109 is formed, the next step is to form the word line structure in the word line trench 109 . The entire word line structure may include an outermost gate insulating layer 111 , a word line WL in the middle, and a gate capping layer 113 above the gate insulating layer 110 and the word line WL. The gate insulating layer 111 can be conformally formed on the surface of the word line trench 109 , and its material can be silicon oxide, hafnium oxide, or aluminum oxide. The word line WL is formed on the gate insulating layer 111 and is electrically insulated from the surrounding active region ACT through the gate insulating layer 111 . The word line WL fills the inner space of the word line trench 109 , and its material can be metal, such as tungsten, aluminum, titanium and/or tantalum. The material of the gate capping layer 113 can be a silicon nitride layer, which fills the space above the gate insulating layer 110 and the word line WL, and the surface is flush with the surface of the active region ACT. An insulating interlayer 115 may also be formed on the surface of the semiconductor substrate 100 to isolate the lower active region ACT from the upper components. The insulating interlayer 115 may be formed of a single insulating layer or a plurality of insulating layers, such as a silicon nitride layer, a silicon nitride layer, and/or a silicon oxynitride layer, and the like.

Please refer to Figure 5 next. After the word line structure is formed in step S2, then in step S3, a dielectric layer 117 and a hard mask layer 119 are sequentially formed on the insulating interlayer 115, and the hard mask layer 119 is used as an etching mask for etching. A photolithography process to form a bit line contact hole 103 in the active region and the insulating interlayer 115 . In an example, the shape of the bit line contact hole 103 may be an ellipse. In addition, as shown in FIG. 1 , the bit line contact holes 103 are uniformly arranged in a staggered manner on the substrate plane. In some embodiments, the bit line contact hole 103 may be formed through an anisotropic etching process. In this case, part of the device isolation layer 101 and the portion of the gate capping layer 113 adjacent to the bit line contact hole 103 will be etched together.

Refer back to Figure 5. After forming the bit line contact hole 103 in the aforementioned step S3, then in step S4, without removing the dielectric layer 117 and the hard mask layer 119, a second doping process P2, such as an ion implantation process, is performed to A doped region is formed in the active region ACT below the bit line contact hole 103 , hereinafter referred to as a first active region 1a. The second doping process P2 may use a dopant of a conductivity type opposite to that of the active region ACT (ie, opposite to the first doping process P1 ). The first active region 1a is located at the center of each active region ACT, and its bottom surface may be positioned at a predetermined depth from the top surface of the active region ACT. It should be noted that in the present invention, the first active region 1a of the semiconductor memory device is formed after the word line WL, which is different from the conventional method of forming the first active region 1a before the word line WL. Groove depth to maintain the effect of implantation process depth, thus improving the GIDL problem.

Please refer to Figure 6 next. After forming the first active region 1a of the semiconductor memory device in the aforementioned step S4, then in step S5, a bit line structure is formed on the first active region 1a. In the embodiment of the present invention, the bit line structure includes a bit line contact 121, a bit line BL, a hard mask pattern 125, and partition walls 127 on both sides from bottom to top, wherein the bit line contact 121 It is electrically connected with the lower first active region 1a. There may be a silicide layer between the bit line contact 121 and the bit line BL. The step of forming the bit line structure may include: removing the dielectric layer 117 and the hard mask layer 119, sequentially forming a polysilicon layer, a metal layer and a hard mask layer on the semiconductor substrate 100, wherein the polysilicon layer will fill the bit line contact hole 103 and in contact with the first active region 1a below, and then use the bit line mask pattern as an etching mask to sequentially etch the hard mask layer, the metal layer and the polysilicon layer, thus forming the bit line structure. The bit line mask pattern can be removed after the etching process. In the present invention, the bit line BL basically extends along the second direction D2 perpendicular to the word line WL, and one bit line BL passes through the first active region 1a of the plurality of active regions ACT, and passes through the plurality of bit lines. The wire contacts 121 are electrically connected to the corresponding first active regions 1a.

In an example, the polysilicon layer may be a doped polysilicon layer, and the metal layer may be a tungsten layer, an aluminum layer, a titanium layer, a tantalum layer, or the like. In this way, each bit line structure may include a stacked bit line contact 121 made of polysilicon, a bit line BL made of metal, and a hard mask pattern 125 in sequence from bottom to top. In addition, the minimum width of the bit line contact hole 103 may be greater than the width of each bit line structure. Sidewalls of the bitline contact 121 of the bitline structure may be spaced apart from sidewalls of the corresponding bitline contact hole 103 . Afterwards, an insulating partition wall 127 is formed on the sidewall of each bit line structure. The material of the partition wall 127 may include a silicon oxide layer, a silicon nitride layer and/or a silicon oxynitride layer, which will cover the entire The sidewall of the bit line structure and fill up the remaining space of the bit line contact hole 103 . In this way, the fabrication of the bit line structure is completed. In addition, after the fabrication of the bit line structure is completed, a conformal insulating layer 129 can be covered on the entire surface of the substrate.

Please refer to Figure 7 next. After the bit line structure is formed in step S5 , then in step S6 , a plurality of spacers 131 are formed on the semiconductor substrate 100 to define a plurality of memory cell regions 105 on the semiconductor substrate 100 . The spacers 131 can be formed by the following steps: (1) forming a sacrificial layer, such as a silicon oxide layer, on the insulating layer 129; (2) patterning the sacrificial layer to form a plurality of spacer patterns in the sacrificial layer ; (3) filling spacer material in the spacer patterns, such as a silicon nitride, to form a plurality of spacers 131; (4) removing the sacrificial layer. Since the manufacturing method of the above-mentioned spacer 131 is a known technology and is not the focus of the present invention, the detailed manufacturing steps will not be described and shown too much in the text and figures. After the spacer 131 is formed, the exposed insulating layer 129 and the insulating interlayer 115 can be removed by using the spacer 131 and the bit line structure as an etching mask to perform anisotropic etching, so as to form the storage node contact hole 133. The underlying active region ACT is exposed. The anisotropic etching also removes part of the active region ACT, so that the bottom surface of the storage node contact hole 133 is lower than the top surface of the active region ACT.

Refer back to Figure 7. After forming the storage node contact hole 133 and exposing the active region ACT in the aforementioned step S6, then in step S7, a third doping process P3, such as an ion implantation process, is performed to make the active area under the storage node contact hole 133 A doped region is formed in the region ACT, hereinafter referred to as the second active region 1b. Like the second doping process P2, the third doping process P3 may use a dopant of a conductivity type opposite to that of the active region ACT (ie, opposite to the first doping process P1). The second active region 1b is located at both ends of each active region ACT, that is, the memory cell region 105 shown in FIG. 1, and its bottom surface may be positioned at a predetermined depth downward from the top surface of the active region ACT. The depth of the first active region 1a may be deeper than that of the second active region 1b. It should be noted that in the present invention, the second active region 1b of the semiconductor memory device is formed after the formation of the word line WL, which is different from the conventional formation before the word line WL. The depth of the groove is used to maintain the effect of the depth of the implantation process, thus improving the GIDL problem.

Please refer to Figure 8 next. After the formation of the second active region 1 b of the semiconductor memory device in the aforementioned step S7 , then in step S8 , the storage node contact 135 is formed in the storage node contact hole 133 . In an example, the top surface of the storage node contact 135 may be lower than the top surface of the hard mask pattern 125 of the bit line structure. The storage node contact 135 may be formed by depositing a conductive layer to fill the storage node contact hole 133, performing a planarization process to remove the conductive layer above the bit line structure and the top surface of the spacer 131, and performing a The etch back process recesses the top surface of the conductive layer, thus forming storage node contacts 135 . Storage node contacts 135 may include, for example, doped semiconductor materials (eg, doped silicon), metals (eg, tungsten, aluminum, titanium, and/or tantalum), conductive metal nitrides (eg, titanium nitride, tantalum nitride, and and/or tungsten nitride) and/or metal-semiconductor alloys (such as metal silicides). In some other embodiments, the storage node contact 135 may sequentially include a polysilicon layer, a metal silicide layer, and a landing pad from bottom to top, on which the respective corresponding capacitors are connected as a storage node. node. Since the above-mentioned parts are not the focus of the present invention, in order to avoid obscuring the focus of the invention, the detailed description of these parts will be omitted herein.

In the present invention, it can be seen from FIG. 8 that the word line WL divides each active area ACT into a first active area 1a located in the middle and a second active area 1b located at both ends of the active area ACT. The word line WL serves as the buried gate of the semiconductor storage device, which controls the switch of the channel region of the array transistor, that is, the switch between the first active region 1a in the middle of the active region ACT and the second active region 1b at both ends. . The first active region 1a is connected to the bit line contact and the bit line, and the second active region 1b is connected to the storage node contact 135 and the capacitor.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (6)

1. A method for manufacturing a semiconductor memory device, comprising: providing a semiconductor substrate; performing a first doping process to form a well region in the semiconductor substrate; forming word lines in the semiconductor substrate after the formation of the well region; After the word lines are formed, a bit line contact hole is formed on the semiconductor substrate between two adjacent word lines to expose the first active region; and, A second doping process is performed on the first active region exposed by the bit line contact hole. 2. The manufacturing method of a semiconductor memory device according to claim 1, wherein after the second doping process, a bit line contact and a bit line are formed on the semiconductor substrate, wherein the bit line a contact piece is connected to the doped first active region; forming a spacer between the bit lines, the spacer and the bit line define a memory cell contact hole on the semiconductor substrate and expose a second active region; performing a third doping process on the second active region exposed by the contact hole of the memory cell; and, After the third doping process, a storage node contact is formed in the memory cell contact hole, wherein the storage node contact is connected to the doped second active region. 3. The method for manufacturing a semiconductor storage device according to claim 2, further comprising forming a shallow trench isolation structure in the semiconductor substrate after the well region is formed, and the shallow trench isolation structure will The semiconductor substrate is divided into a plurality of active regions, and the first active region and the second active region are included in the active regions. 4. The manufacturing method of a semiconductor memory device according to claim 3, wherein each of the active regions includes a first active region located in the center of the active region and a first active region located in the center of the active region. The second active region on both sides of the region. 5. The manufacturing method of a semiconductor memory device according to claim 2, further comprising performing an etching process to etch the semiconductor substrate in the memory cell contact hole after the spacer is formed, so that the The semiconductor substrate in the contact hole of the memory cell is recessed. 6. The method for manufacturing a semiconductor memory device according to claim 2, wherein the depth of the doped first active region is deeper than the depth of the doped second active region.

Images