CN116053136A

CN116053136A - Method for manufacturing semiconductor memory device

Info

Publication number: CN116053136A
Application number: CN202211305019.8A
Authority: CN
Inventors: 张钦福; 冯立伟; 童宇诚
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-07-31
Filing date: 2020-07-31
Publication date: 2023-05-02
Also published as: CN111863727A; CN111863727B

Abstract

The invention discloses a manufacturing method of a semiconductor memory device, which comprises the steps of performing a first doping process to form a well region in a semiconductor substrate, forming a word line in the semiconductor substrate, forming a bit line contact hole on the semiconductor substrate to expose a first active region, performing a doping process to the first active region exposed by the bit line contact hole, forming a bit line contact and a bit line on the semiconductor substrate, wherein the bit line contact is connected with the doped first active region, forming a spacer between the bit lines, defining a memory cell contact hole on the semiconductor substrate by the spacer and the bit line, exposing a second active region, performing a doping process to the second active region exposed by the memory cell contact hole, and forming a memory node contact in the memory cell contact hole, wherein the memory node contact is connected with the doped second active region.

Description

Method for manufacturing semiconductor memory device

Technical Field

The present application is a divisional application entitled "method of manufacturing a semiconductor memory device", and the original application date is 31/07/2020, and the application number is 202010760383.8.

Embodiments of the present disclosure relate to a method of fabricating a semiconductor memory device, and more particularly, to a method of fabricating a semiconductor memory device that can improve the problem of gate induced drain leakage (Gate Induced Drain Leakage, GIDL) at a buried word line location.

Background

The gate induced drain leakage (Gate Induced Drain Leakage, GIDL) effect is the dominant off-state leakage of MOSFETs. This effect arises from the formation of an inversion layer on the surface due to the strong bending of the Band at the portion where the drain impurity diffusion layer overlaps the gate near the interface when the MOSFET gate is off (NM 0S gate is negative, PMOS gate is positive) and the drain is negative (NM 0S drain is positive, PMOS drain is negative), while the depletion layer is so narrow that Band-to-Band Tunneling (Band-to-Band Tunneling) occurs in the conduction Band electrons and valence Band holes, thus forming a drain leakage current. It is the main source of off-state leakage current and determines the lower thickness limit of the thin oxide layer of the gate oxide layer. When the MOS is provided with a thin gate, GIDL may cause holes to damage the gate oxide layer by tunneling effect or be trapped by the thin gate, which may cause degradation of performance and reliability of the MOSFET. In addition to off-state leakage, gate induced drain leakage may have other adverse consequences, such as damage to or trapping by the gate oxide layer due to tunneling effects, resulting in degraded MOSFET performance and reduced reliability.

The conventional method for inhibiting GIDL is mainly to increase the thickness of the gate dielectric layer or diffuse impurities at the drain end away from the gate, and obviously, in the semiconductor industry pursuing high integration, such a scheme is not beneficial to further shrinking the device, especially in the aspect of shrinking the memory device, and other parasitic effects (such as hot carrier effect, hot carrier effect) and other adverse effects are caused. Therefore, there is still a need to develop other methods for effectively improving GIDL problem.

Disclosure of Invention

In view of the above-mentioned problems of Gate Induced Drain Leakage (GIDL) that are easily encountered in semiconductor devices, the present invention provides a novel method for fabricating a semiconductor memory device, which is characterized in that the source/drain implantation process that is performed after the well region implantation process is changed to be performed before the bit line contact and before the storage node contact is fabricated, so that the effect of connecting the implantation process depth according to the recess depth of the buried word line can be achieved, thereby improving the GIDL problem.

The invention provides a method for manufacturing a semiconductor memory device, which comprises the steps of providing a semiconductor substrate, performing a first doping process to form a well region in the semiconductor substrate, forming a word line in the semiconductor substrate after the well region is formed, forming a bit line contact hole on the semiconductor substrate to expose a first active region after the word line is formed, performing a second doping process to expose the first active region of the bit line contact hole, forming a bit line contact and a bit line on the semiconductor substrate after the second doping process, wherein the bit line contact is connected with the doped first active region, forming a spacer between the bit line and the bit line, defining a memory cell contact hole on the semiconductor substrate and exposing a second active region, performing a third doping process to expose the memory cell contact hole on the second active region, and forming a memory node contact in the memory cell contact hole after the third doping process, wherein the spacer and the bit line contact are connected with the second active region.

These and other objects of the present invention will become more readily apparent to those skilled in the art from a reading of the following detailed description of the preferred embodiment, which is to be read in connection with the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to further explain the principles of the invention. The drawings illustrate some embodiments of the invention and, together with the description, explain its principles. In these illustrations:

FIG. 1 is a plan view of a semiconductor memory device according to a preferred embodiment of the present invention;

FIGS. 2 to 8 are cross-sectional views of a semiconductor memory device during a manufacturing process according to a preferred embodiment of the present invention; and

fig. 9 is a flow chart showing a manufacturing process of a semiconductor memory device according to the preferred embodiment of the invention.

It should be noted that all figures in this specification are schematic representations for clarity and convenience in the drawings, in which the various elements in the figures may be exaggerated in size or scale, and in general, the same reference numerals will be used to designate corresponding or analogous element features in modified or different embodiments.

Wherein reference numerals are as follows:

1a first active region

1b second active region

100. Semiconductor substrate

101. Device isolation layer

103. Bit line contact hole

105. Memory cell area

107. Trap

109. Word line trench

111. Gate insulating layer

113. Gate cap layer

115. Insulating interlayer

117. Dielectric layer

119. Hard mask layer

121. Bit line contact

125. Hard mask pattern

127. Partition wall

129. Insulating layer

131. Spacing piece

133. Storage node contact hole

135. Storage node contact

ACT active region

BL bit line

D1 First direction

D2 Second direction

D3 Third direction of

P1 first doping process

P2 second doping process

P3 third doping process

S1-S8 steps

WL word line

Detailed Description

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the features are shown for the purpose of understanding and realizing the technical effects by a reader. It will be appreciated by those skilled in the art that the description herein is made by way of example only and is not intended to be limiting. The various embodiments of the present disclosure and the various features of the embodiments that do not conflict with one another may be combined or rearranged in a variety of ways. Modifications, equivalents, or improvements therein may be apparent to those skilled in the art without departing from the spirit and scope of the present invention, and are intended to be included within the scope of the present invention.

The reader should readily understand that the meanings of "on …", "above …" and "above …" in this disclosure should be interpreted in a broad sense such that "on …" means "directly on" something but also includes the meaning of "on" something with intervening features or layers therebetween, and "on …" or "above …" means "not only" on "or" above "something but also may include the meaning of" on "or" above "something without intervening features or layers therebetween (i.e., directly on something).

Further, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one component or feature's relationship to another component or feature as illustrated in the figures.

As used herein, the term "substrate" refers to a material to which a subsequent material is added. The substrate itself may be patterned. The material added on top of the substrate may or may not remain patterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal facing at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along an inclined surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Referring now to fig. 1, therein is shown a basic layout arrangement of a semiconductor memory device according to a preferred embodiment of the present invention. The semiconductor memory device is formed on a semiconductor substrate 100. The semiconductor substrate 100 has a memory cell region, which is a memory cell for setting a semiconductor memory device, or referred to as a memory node, and a peripheral region located around the memory cell region. The plurality of storage nodes are arranged in a matrix pattern in the storage cell region and can store charges to generate a distinct storage state. The peripheral region is used for setting peripheral circuits of the memory device, such as column decoder, sense amplifier, or I/O control module. Since the inventive features of the present invention are independent of the peripheral region, only the features and characteristics of the memory cell region are shown.

The semiconductor substrate 100 has thereon a plurality of active regions ACT defined by a device isolation layer 101. In an example, the active region ACT is in a bar-like pattern and has a long axis extending in the third direction D3. The plurality of active regions ACT are uniformly arranged in a staggered manner over the entire substrate plane. A bit line contact hole 103 is formed in the middle of each active region ACT, and a doped region and a bit line contact of the semiconductor memory device are formed in the bit line contact hole 103 in a subsequent manufacturing process. The semiconductor substrate 100 further has a plurality of word lines WL embedded therein, extending in the first direction D1 and arranged in parallel with each other at intervals, and an included angle between the first direction D1 and the third direction D3 is preferably between 45 degrees and 90 degrees. In the example, the word lines WL extend across both sides of the bit line contact holes 103 of the active regions ACT, thus dividing each active region ACT into a bit line contact hole 103 region located in the middle of the active region ACT and memory cell regions 105 located at both ends of the active region ACT. The subsequent fabrication process will form doped regions and storage node contacts on the storage cell regions. The semiconductor substrate 100 is further formed with a bit line structure extending in a second direction D2 orthogonal to the first direction D1 and arranged in parallel with each other at a distance, which is not shown in fig. 1 for simplicity of illustration. In the following embodiments, the relative positions and connection relationships between the cross-sectional structure of the semiconductor memory device and the constituent parts during the fabrication process will be described by taking the line i-i 'and the line ii-ii' in fig. 1 as the cross-sectional lines, wherein the line i-i 'cuts through the long axis of the active region ACT along the third direction D3, and the line ii-ii' cuts through the device isolation layer 101 and the memory cell regions 105 of the plurality of active regions ACT along the first direction D1.

Having understood the basic planar layout of the semiconductor memory device, the following embodiments will now describe the method of fabricating related components in the semiconductor memory device according to the present invention with reference to the flowchart shown in fig. 9, wherein the method can be more clearly detailed and understood from the corresponding cross-sectional structures of fig. 2 to 8 at various stages and steps, respectively.

Referring first to fig. 2, the entire semiconductor memory device process of the present invention is performed from a semiconductor substrate 100. Such as a silicon substrate, a germanium substrate, and/or a silicon germanium substrate. In step S1, the semiconductor substrate 100 is first subjected to a first doping process P1, such as an ion implantation process, to form various wells 107 therein. In the present invention, the well 107 may be used as a channel region of a buried channel array transistor. More than one well 107 may be formed in the semiconductor substrate 100, which may be distributed at different depths of the substrate and have different conductivity types, such as p-type wells and/or n-type wells, which will be indicated by only one well 107. The semiconductor substrate 100 defines a plurality of active regions ACT, such as the stripe-like active regions ACT shown in fig. 1, each of which is separated by a surrounding device isolation layer 101. In the process, the device isolation layer 101 may be formed by performing a photolithography process on the semiconductor substrate 100 to form individual separated active regions ACT, and filling a spacer material such as silicon oxide into the recesses between the active regions ACT. The depth of the device isolation layer 101 may correspond to the depth of the spike concentration of the well 107.

Next, please refer to fig. 3. It should be noted that for the sake of clarity of specific portions, the cross-sectional structure of fig. 3 is cut by using the line i-i' along the long axis of the active region ACT in fig. 1 as a cross-sectional line to show the relative relationship of the word line, bit line, and doped region of the semiconductor memory device of the present invention in the subsequent process. After the device isolation layer 101 is formed and the active region ACT is defined in the step S1, a word line is fabricated in the semiconductor substrate 100 in the step S2. The fabrication of the word lines first involves forming word line trenches 109 in the semiconductor substrate 100. As shown in fig. 1, a word line WL predetermined to be formed in the semiconductor memory device of the present invention extends through the device isolation layer 101 and the plurality of active regions ACT along the first direction D1, and thus, in fig. 3, there is a word line trench 109 formed in the active region ACT and also a word line trench 109 formed in the device isolation layer 101. In this case, since the etching rate of the device isolation layer 101 made of silicon oxide is higher than that of the active region ACT made of silicon in the same etching process, the depth of the word line trench 109 formed in the device isolation layer 101 is deeper than that of the word line trench 109 formed in the active region ACT.

Next, please refer to fig. 4. After the formation of the word line trench 109, a word line structure is formed in the word line trench 109. The entire word line structure may include an outermost gate insulating layer 111, the middle word line WL, and a gate cap layer 113 over the gate insulating layer 110 and the word line WL. The gate insulating layer 111 may be conformally formed on the surface of the word line trench 109, and the material may be silicon oxide, hafnium oxide, aluminum oxide, or the like. The word line WL is formed on the gate insulating layer 111 and is electrically insulated from the surrounding active region ACT through the gate insulating layer 111. The word line WL fills the interior space of the word line trench 109, which may be made of a metal such as tungsten, aluminum, titanium, and/or tantalum. The material of the gate cap layer 113 may be a silicon nitride layer that fills the space above the gate insulating layer 110 and the word line WL and has a surface that is flush with the surface of the active region ACT. An insulating interlayer 115 may also be formed on the surface of the semiconductor substrate 100 to isolate the underlying active region ACT from overlying components. The insulating interlayer 115 may be formed of a single insulating layer or a plurality of insulating layers, such as a silicon nitride layer, and/or a silicon oxynitride layer, etc.

Next, please refer to fig. 5. After the word line structure is formed in the step S2, in step S3, a dielectric layer 117 and a hard mask layer 119 are sequentially formed on the insulating interlayer 115, and a photolithography process is performed using the hard mask layer 119 as an etching mask to form a bit line contact hole 103 in the active region and the insulating interlayer 115. In an example, the shape of the bit line contact hole 103 may be elliptical. Further, as shown in fig. 1, the bit line contact holes 103 are uniformly arranged in a staggered manner on the substrate plane. In some embodiments, the bit line contact hole 103 may be formed by an anisotropic etching process. In this case, portions of the device isolation layer 101 and portions of the gate cap layer 113 adjacent to the bit line contact holes 103 are etched together.

Referring back to fig. 5. After the bit line contact hole 103 is formed in the aforementioned step S3, a second doping process P2, such as an ion implantation process, is performed without removing the dielectric layer 117 and the hard mask layer 119 in step S4 to form a doped region, hereinafter referred to as a first active region 1a, in the active region ACT under the bit line contact hole 103. The second doping process P2 may use a dopant of a conductivity type opposite to that of the active region ACT (i.e., opposite to that of the first doping process P1). The first active region 1a is located at the center of each active region ACT, and the bottom surface thereof may be positioned at a predetermined depth downward from the top surface of the active region ACT. It should be noted that in the present invention, the first active region 1a of the semiconductor memory device is formed after the word line WL, which is different from the conventional method before the word line WL, and this method can achieve the effect of connecting the implantation process depth according to the depth of the recess in which the word line is buried, thereby improving the GIDL problem.

Next, please refer to fig. 6. After the first active region 1a of the semiconductor memory device is formed in the aforementioned step S4, a bit line structure is formed on the first active region 1a in step S5. In the embodiment of the invention, the bit line structure sequentially includes, from bottom to top, a bit line contact 121, a bit line BL, a hard mask pattern 125, and spacers 127 on two sides, where the bit line contact 121 is electrically connected to the first active region 1a below. A silicide layer may also be present between bit line contact 121 and bit line BL. The step of forming the bit line structure may include: the dielectric layer 117 and the hard mask layer 119 are removed, and a polysilicon layer, a metal layer and a hard mask layer are sequentially formed on the semiconductor substrate 100, wherein the polysilicon layer fills the bit line contact hole 103 and contacts the underlying first active region 1a, and then the hard mask layer, the metal layer and the polysilicon layer are sequentially etched using the bit line mask pattern as an etching mask, thus forming the bit line structure as shown in fig. 6. The bit line mask pattern may be removed after the etching process. In the present invention, the bit lines BL extend substantially along the second direction D2 perpendicular to the word lines WL, and one bit line BL passes through the first active regions 1a of the plurality of active regions ACT and is electrically connected to the corresponding first active regions 1a through the plurality of bit line contacts 121.

In an example, the polysilicon layer may be a doped polysilicon layer, and the metal layer may be a tungsten layer, an aluminum layer, a titanium layer, a tantalum layer, or the like. Thus, each bit line structure may include, from bottom to top, stacked bit line contacts 121 of polysilicon, bit lines BL of metal, and hard mask patterns 125. In addition, the minimum width of the bit line contact hole 103 may be greater than the width of each bit line structure. The sidewalls of the bit line contacts 121 of the bit line structure may be spaced apart from the sidewalls of the corresponding bit line contact holes 103. Thereafter, insulating spacers 127 are formed on the sidewalls of each bit line structure, wherein the spacers 127 may comprise a silicon oxide layer, a silicon nitride layer and/or a silicon oxynitride layer, which cover the sidewalls of the entire bit line structure and fill the remaining bit line contact hole 103 space. Thus, the bit line structure is completed. In addition, after the bit line structure is fabricated, a conformal insulating layer 129 may be covered over the entire substrate surface.

Next, please refer to fig. 7. After the bit line structure is formed in the aforementioned step S5, a plurality of spacers 131 are formed on the semiconductor substrate 100 in step S6, so as to define a plurality of memory cell regions 105 on the semiconductor substrate 100. The spacer 131 may be formed through the following steps: (1) Forming a sacrificial layer, such as a silicon oxide layer, on the insulating layer 129; (2) Patterning the sacrificial layer to form a plurality of spacer patterns in the sacrificial layer; (3) Filling the spacer patterns with a spacer material, such as a silicon nitride, to form a plurality of spacers 131; (4) removing the sacrificial layer. Since the method for fabricating the spacer 131 is well known and is not the focus of the present invention, the detailed fabricating steps will not be described or illustrated in detail herein. After the spacers 131 are formed, an anisotropic etch may then be performed using the spacers 131 and the bit line structure as an etch mask to remove the exposed insulating layer 129 and insulating interlayer 115, thereby forming storage node contact holes 133 exposing the underlying active regions ACT. This anisotropic etch also removes portions of the active region ACT such that the bottom surface of the storage node contact hole 133 is lower than the top surface of the active region ACT.

Referring back to fig. 7. After the storage node contact hole 133 is formed and the active region ACT is exposed in the aforementioned step S6, a third doping process P3, such as an ion implantation process, is performed in step S7 to form a doped region, hereinafter referred to as a second active region 1b, in the active region ACT under the storage node contact hole 133. As with the second doping process P2, the third doping process P3 may use a dopant of a conductivity type opposite to that of the active region ACT (i.e., opposite to that of the first doping process P1). The second active regions 1b are located at both ends of each active region ACT, i.e., the memory cell region 105 shown in fig. 1, and the bottom surface thereof may be positioned at a predetermined depth downward from the top surface of the active region ACT. The depth of the first active region 1a may be deeper than the depth of the second active region 1b. It should be noted that in the present invention, the second active region 1b of the semiconductor memory device is formed after the formation of the word line WL, which is different from the conventional method before the formation of the word line WL, the effect of connecting the implantation process depth according to the recess depth of the buried word line can be achieved, thereby improving the GIDL problem.

Next, please refer to fig. 8. After the second active region 1b of the semiconductor memory device is formed in the aforementioned step S7, next in step S8, a storage node contact 135 is formed in the storage node contact hole 133. In an example, the top surface of the storage node contact 135 may be lower than the top surface of the hard mask pattern 125 of the bit line structure. The storage node contacts 135 may be formed by the following process: a conductive layer is deposited to fill the storage node contact hole 133, a planarization process is performed to remove the conductive layer over the bit line structure and the top surface of the spacer 131, and an etch back process is performed to recess the top surface of the conductive layer, thus forming the storage node contact 135. Storage node contacts 135 may include, for example, doped semiconductor material (e.g., doped silicon), metal (e.g., tungsten, aluminum, titanium, and/or tantalum), conductive metal nitride (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride), and/or metal-semiconductor alloy (e.g., metal silicide). In some other embodiments, the storage node contact 135 may comprise, from bottom to top, a polysilicon layer, a metal silicide layer, and a landing pad, which may be connected to respective corresponding capacitors as a storage node. Since these portions are not important points of the present invention, detailed descriptions of these portions will be omitted herein in order to avoid obscuring the focus of the present invention.

In the present invention, it can be seen from fig. 8 that the word line WL divides each active region ACT into a first active region 1a located in the middle and second active regions 1b located at both ends of the active region ACT. The word line WL serves as a buried gate of the semiconductor memory device, which controls switching of the channel region of the array transistor, i.e., switching between the first active region 1a in the middle of the active region ACT to the second active region 1b at both ends. The first active region 1a is connected to the bit line contacts and the bit lines, and the second active region 1b is connected to the storage node contacts 135 and the capacitors.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of manufacturing a semiconductor memory device, comprising:

providing a semiconductor substrate;

forming a well region in the semiconductor substrate by performing a first doping process;

forming a word line in the semiconductor substrate after the well region is formed;

forming bit line contact holes on the semiconductor substrate between two adjacent word lines to expose the first active region after the word lines are formed; the method comprises the steps of,

and performing a second doping process on the first active region exposed by the bit line contact hole.

2. The method of manufacturing a semiconductor memory device according to claim 1, wherein a bit line contact and a bit line are formed on the semiconductor substrate after the second doping process, wherein the bit line contact is connected to the doped first active region;

forming spacers between the bit lines, the spacers and the bit lines defining memory cell contact holes on the semiconductor substrate and exposing the second active region;

performing a third doping process on the second active region exposed by the memory cell contact hole; the method comprises the steps of,

and after the third doping process, forming a storage node contact in the storage unit contact hole, wherein the storage node contact is connected with the doped second active region.

3. The method of claim 2, further comprising forming a shallow trench isolation structure in the semiconductor substrate after the well region is formed, the shallow trench isolation structure dividing the semiconductor substrate into a plurality of active regions, the first active region and the second active region being included in the active regions.

4. The method of manufacturing a semiconductor memory device according to claim 3, wherein each of the active regions includes the first active region located at a center of the active region and the second active regions located at both sides of the active region.

5. The method of claim 2, further comprising etching the semiconductor substrate within the memory cell contact hole after the spacer is formed such that the semiconductor substrate within the memory cell contact hole is recessed.

6. The method of manufacturing a semiconductor memory device according to claim 2, wherein a depth of the doped first active region is deeper than a depth of the doped second active region.