KR101589275B1 - Method for fabricating nonvolatile memory devices - Google Patents

Abstract

A method of manufacturing a non-volatile memory device of a three-dimensional structure is provided. A method of fabricating a nonvolatile memory device includes forming a stack structure in which at least two or more first and second insulating films having different etching rates are alternately stacked on a semiconductor substrate and penetrating the first and second insulating films, Forming active columns connected to the substrate and forming trenches through the stack structure between the active columns to form line-type stack structures and to form upper surfaces of the line-shaped stack structures Forming horizontal supporting posts that contact, removing the second insulating films, forming openings between the first insulating films, and locally forming conductive patterns in the openings.

3D, horizontal support, vertical support

Description

TECHNICAL FIELD [0001] The present invention relates to a method for fabricating nonvolatile memory devices,

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a method of manufacturing a nonvolatile memory device having a three-dimensional structure.

In general, a nonvolatile memory device is an element capable of electrically erasing and programming data, and capable of preserving data even when power is shut off. Accordingly, the use of nonvolatile memory devices is increasing in various fields in recent years.

Nonvolatile memory devices constitute various types of memory cell transistors, and are largely divided into NAND type and NOR type depending on the cell array structure. NAND type nonvolatile memory devices and NOR type nonvolatile memory devices have advantages and disadvantages that are divided into high integration and high performance.

In particular, the NAND type nonvolatile memory device is advantageous in high integration because of a cell string structure in which a plurality of memory cell transistors are serially connected. Since the NAND-type nonvolatile memory device adopts an operation method of simultaneously changing the information stored in the plurality of memory cell transistors, the information update speed is much faster than the NOR type nonvolatile memory device. Due to such high integration and fast update speed, NAND type nonvolatile memory devices are mainly used in portable electronic products requiring mass storage such as digital cameras or MP3 players. The advantages of such NAND type nonvolatile memory devices are continuously being explored and promoted, and a three-dimensional NAND type nonvolatile memory device is being developed.

The advantages of such NAND type nonvolatile memory devices are continuously being explored and promoted, and a three-dimensional NAND type nonvolatile memory device is being developed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a nonvolatile memory device having a three-dimensional structure capable of preventing process defects.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of fabricating a nonvolatile memory device, the method comprising: forming a first insulating layer on a semiconductor substrate and a second insulating layer on the first insulating layer, Forming stack structures, passing through the first and second insulating films to form active columns connected to the semiconductor substrate, forming trenches through the stack structure between the active columns to form line stack structures, Overlying adjacent line stack structures, forming horizontal supports that are in contact with the tops of the line stack structures, removing the second insulating films, forming openings between the first insulating films, locally challenging To form patterns.

The details of other embodiments are included in the detailed description and drawings.

According to the method of manufacturing a nonvolatile memory device of a three-dimensional structure of the present invention, horizontal supports are formed over the top surface of the line-type stack structures for forming conductive lines arranged in a three-dimensional structure. Accordingly, the upper surface of the line-shaped stack structures having a high height can be fixed by being contacted with the horizontal supports. Therefore, in the line-type stack structure, when the openings are formed between the stacked first insulating films, the line-shaped stack structure can be prevented from collapsing.

In addition, by forming vertical supports extending through the stacked insulating films at the edge portions of the line-shaped stack structure, it is possible to prevent the first insulating films from collapsing when the openings are formed between the stacked first insulating films.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in this specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. A non-volatile memory device according to embodiments of the present invention has a three-dimensional structure.

1 is a circuit diagram showing a nonvolatile memory device according to embodiments of the present invention.

Referring to FIG. 1, a non-volatile memory device according to an embodiment of the present invention includes a cell array including a plurality of strings STR. The cell array includes a plurality of bit lines BL1 to BL3, word lines WL1 to WL4, upper and lower selection lines USL1 to USL3 and LSL, and a common source line CSL. And includes a plurality of strings STR between the bit lines BL1 to BL3 and the common source line CSL.

Each string STR includes a plurality of memory cell transistors MC connected in series between upper and lower selection transistors UST and LST and upper and lower selection transistors UST and LST. The drains of the upper select transistors UST are connected to the bit lines BL1 to BL3 and the sources of the lower select transistors LST are connected to the common source line CSL. The common source line CSL is a line to which the sources of the lower selection transistors LST are connected in common.

The upper select transistors UST are connected to the upper select lines USL1 to USL3 and the lower select transistors LST are connected to the lower select line LSL. Also, each of the memory cells MC is connected to the word lines WL1 to WL4.

Such cell arrays are arranged in a three-dimensional structure, and the strings STR have a structure in which memory cells MC are connected in series in a z-axis direction perpendicular to the xy plane parallel to the upper surface of the substrate. Accordingly, the channels of the selection transistors UST and LST and the memory cell transistors MC can be formed perpendicular to the xy plane.

In a nonvolatile memory device having a three-dimensional structure, m memory cells may be formed in each xy plane, and an xy plane having m memory cells may be stacked in n layers. (Where m and n are natural numbers).

Hereinafter, a method of manufacturing a nonvolatile memory device according to embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 2 to 9 are views sequentially illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 2, a stack structure in which first and second insulating films 110 and 115 having different etching rates are alternately stacked is formed on a semiconductor substrate 100 in a memory cell region. The semiconductor substrate 100 may include an impurity region (or a well 102), and the first and second insulating films 110 and 115 may be stacked on the surface of the impurity region 102. [ At this time, the number of the first and second insulating films 110 and 115 stacked may vary depending on the memory capacity, and the height of the stack structure increases as the memory capacity increases. In addition, the second insulating layer 115 may be formed of a material having a higher wet etching rate than the first insulating layer 110. For example, the first and second insulating films 110 and 115 may be formed of a silicon oxide film and a silicon nitride film, respectively, and may be formed of silicon oxide films having different wet etching rates.

Referring to FIG. 3, active pillars 124 are formed in the central portion (i.e., memory cell region) of the stack structure.

More specifically, the channel holes are formed through the first and second insulating films 110 and 115 to expose the semiconductor substrate 100 at the central portion of the stack structure, that is, at the portion where the memory cells are formed. The channel holes may be formed by performing a normal photolithography process, and the channel holes may be formed in a planar matrix form.

Thereafter, a charge storage layer 122 may be formed on the inner walls of the channel holes, and semiconductor materials may be embedded in the channel holes to form the active pillars 124. The charge storage layer 122 may be formed by conformally depositing along the surface of the channel holes and removing the deposited charge storage layer 122 on the surface of the semiconductor substrate 100. Specifically, the charge storage film 122 includes a charge tunneling film, a charge trapping film, and charge blocking films. On the other hand, in another embodiment, the charge storage film 122 may be formed in a subsequent process. That is, the charge storage layer 122 may be formed to surround the active pillars 124 and vertical supports.

The active pillars 124 may be formed by embedding semiconductor material in the channel holes. In this case, the semiconductor material may be a polycrystalline or single crystal semiconductor, or may be formed by epitaxial processing using the semiconductor substrate 100 as a seed layer, or by depositing a semiconductor material. The active pillars 124 buried in the channel holes may be connected to the semiconductor substrate 100.

The stack structure including active pillars 124 is then patterned to form a line type stack structure. In detail, the trenches 132 passing through the first and second insulating films 110 and 115 may be formed between the active pillars 124 to form the line-shaped stack structures.

The trenches 132 may be formed by performing a normal photolithography and etching process and the semiconductor substrate 100, that is, the impurity region 102 may be exposed by the trenches 132. [ The trenches 132 may be formed in a line shape and may be spaced apart from each other by a predetermined distance in parallel with each other. Thus, by forming the trenches 132, one side walls of the first and second insulating layers 110 and 115 can be exposed to the trenches 132. [

Referring to FIG. 4, a sacrificial insulation layer 134 is buried in the trenches 132 between the line-shaped stack structures and planarized until the uppermost first insulation layer 110 is exposed. The sacrificial insulating layer 134 may be formed of a material having an etch selectivity with respect to the first insulating layer 110. According to one embodiment, the sacrificial insulating layer 134 may be formed of the same material as the second insulating layer 115 so that the sacrificial insulating layer 134 may be removed together with the second insulating layers 115 in a subsequent process. Thereafter, horizontal supports 140 are formed on the line-shaped stack structures. The horizontal supports 140 are used to remove the second insulating films 115 of the line stack structure in a subsequent process and to form conductive patterns between the first insulating films 115, The pillars 124) can be prevented from falling down.

5A and 5B show a planar structure of horizontal supports in a method of manufacturing a nonvolatile memory device according to embodiments of the present invention.

4 and 5A, the horizontal supports 140 are formed across the line-type stack structures and may be formed to contact the upper surfaces of the at least two line-type stack structures. In addition, the horizontal supports 140 are spaced apart from each other to expose portions of the sacrificial insulation layers 134.

Specifically, the horizontal supports 140 may be formed by forming a material film having an etch selectivity with the second insulating film 115 on the top surface of the line-type stack structure, and patterning the material film in a line shape. The material film for forming the horizontal supports 140 may be the same insulating material as the first insulating film 110, and semiconductor materials and metal materials are also possible. That is, the horizontal supports 140 cross the plurality of line stack structures in contact with the upper surfaces of the line stack structures. In addition, the horizontal supports 140 having a line shape may be disposed on the active pillars 124, or disposed between the active pillars 124.

In addition, although the figure shows that the horizontal supports 140 are disposed perpendicular to the line stack structures, the present invention is not limited thereto, and the horizontal supports may obliquely cross the upper surfaces of the plurality of line stack structures.

In addition, the horizontal supports 140 may be formed on both sides of the active pillars 124 arranged in a matrix form. In other words, the horizontal supports 140 may be formed across the top surfaces of the line-like stack structures at the edge portions of the memory cell region. That is, the distance L between the horizontal supports 140 may vary.

In addition, the horizontal supports 140 may have portions (not shown) extending between the line stack structures. That is, the sacrificial insulation layer 134 may be filled between the portions extending from the horizontal supports 140.

Meanwhile, referring to FIG. 5B, the horizontal supports 140 'may be formed with local patterns in contact with the upper surface of the adjacent line stack structures.

In detail, a sacrificial insulating film 134 is buried between the line-type stack structures, a material film is formed on the top surface of the line-shaped stack structures, and then the material film is patterned to form a local The horizontal support patterns 140 'may be formed. The horizontal support patterns 140 'may be formed in a square or circular pattern, and may be arranged in a matrix or a radiation pattern. As such, the horizontal support pattern 140 'can also prevent collapse of the line stack structure while contacting the upper surface of the adjacent line stack structures.

Referring to FIG. 6, after forming the horizontal supports 140, the sacrificial insulation layer 134 between the line stack structures is removed to expose the sidewalls of the line stack structure. That is, the sidewalls of the first and second insulating films 110 and 115 are exposed. At this time, the sacrificial insulating film 134 can be removed through anisotropic etching or isotropic etching. For example, the wet etching solution may be supplied to the upper surface of the sacrificial insulating layer 134 to remove the sacrificial insulating layer 134. When the sacrificial insulating film 134 is removed, the horizontal supports 140 are formed of a material having an etch selectivity with respect to the sacrificial insulating film 134, and thus remain on the line-shaped stack structures spaced from each other. Accordingly, the upper surface of the line-shaped stack structures spaced apart from each other is fixed by the horizontal supports 140, thereby preventing the line-shaped stack structures from collapsing. That is, the horizontal supports 140 across the top surface of the line-shaped stack structures spaced apart from each other can maintain the spacing of the line-shaped stack structures. And, the trenches can be re-formed between the line-type stack structures.

In order to form a conductive pattern (i.e., gate electrodes) between the vertically stacked first insulating films 110, the second insulating films 115 between the first insulating films 110 in the line- Remove. That is, openings 152 are formed between the vertically stacked first insulating films 110 to expose the charge storage film 122. Here, when the second insulating films 115 are the same material as the sacrificial insulating film 134, the sacrificial insulating film 134 and the second insulating film 115 can be continuously removed through isotropic etching.

Since the horizontal supports 140 are formed of a material having the etch selectivity with the second insulating films 115, they remain on the top surfaces of the line-type stack structures during the removal of the second insulating films 115. That is, the horizontal supports 140 maintain the spacing between the line stack structures, thereby preventing the line stack structures from collapsing.

Referring to FIG. 7, after the second insulating films 115 are removed, the conductive film 160 is embedded in the openings 152. The conductive film 160 may be formed of a polysilicon film, a metal film, a silicide film, or a composite film thereof. When the conductive film 160 is buried in the openings 152, the conductive film 160 may be buried between the first insulating films 110 that are horizontally adjacent to each other.

When the conductive film 160 is buried between the first insulating films 110, the conductive film 160 between the first insulating films 110 horizontally adjacent to each other is anisotropically etched as shown in FIG. That is, the trenches 132 may be formed between the first insulating films 110, thereby locally forming the conductive patterns 162 in each of the openings 152. That is, the conductive patterns 162 may be separated for each layer.

Further, in order to remove the conductive films 160 between the first insulating films 110, a part of the horizontal supports 140 across the line-shaped stack structures may also be removed. On the other hand, when the horizontal supports 140 are formed of a semiconductor film or a conductive film, the horizontal supports 140 may be removed after the conductive patterns 162 are formed in the openings 152.

As the conductive patterns 162 are locally formed in the openings 152, word lines arranged three-dimensionally on the semiconductor substrate 100 can be formed. The active pillars 124 are connected to the semiconductor substrate 100 through the stacked conductive lines.

According to another embodiment of the present invention, after the openings 152 are formed between the vertically adjacent first insulating layers 110, a conductive pattern (not shown) may be selectively formed in the openings 152 using a selective deposition or plating process. (Not shown). The process of separating the conductive patterns 162 from each other after the conductive film is embedded in the openings 152 may be omitted.

After locally forming the conductive patterns 162 in the openings 152, the insulating film 170 is buried between the horizontally adjacent conductive patterns 162. The insulating film 170 may be buried up to between the horizontal supports 142. That is, after the conductive patterns 162 are three-dimensionally arranged on the semiconductor substrate 100, the horizontal supports 142 may be provided as part of the insulating film.

Referring to FIG. 9, a bit line 184 may be formed on the insulating layer 170 and the horizontal supports 142, which are connected to the active pillars 124 through the contact plugs 182. The bit lines 184 may be formed across the three dimensionally arranged word lines 162.

 10A to 10F, a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention will be described in detail.

10A to 10F are views sequentially illustrating a method of manufacturing a nonvolatile memory device according to the second and fifth embodiments of the present invention.

Referring to FIG. 10A, on the semiconductor substrate 200 including the memory cell region MR and the contact regions CR, first and second insulating films 210 and 215 having different etch selectivities are alternately Laminated. Specifically, the first and second insulating films 210 and 215 are formed of materials having different wet etching rates. For example, the first and second interlayer insulating films 210 and 215 may be formed of a silicon oxide film and a silicon nitride film, respectively.

Thereafter, active pillars 224 passing through the first and second insulating films 210 and 215 and a charge storage film 222 surrounding the active pillars 224 are formed in the memory cell region MR.

In detail, a plurality of channel holes are formed in the memory cell region MR through the first and second insulating films 210 and 215. The channel holes may be formed by performing a normal photolithography and etching process. The channel holes may expose the impurity region 202 of the semiconductor substrate 200 and may be formed in a matrix form in the planar memory cell region MR. Thereafter, the charge storage film 222 is formed conformally along the surface of the channel holes, and the deposited charge storage film is anisotropically etched to form a charge storage film 222 (only on the sidewalls of the first and second insulating films 210 and 215) ), And exposes the surface of the semiconductor substrate 200. For example, the charge storage film 222 may be formed by depositing a charge tunneling film, a charge trap film, and a charge blocking film in order. Subsequently, semiconductor material is buried in the channel holes to form the active pillars 224. In this case, the semiconductor material may be a polycrystalline or single crystal semiconductor, or may be formed by epitaxial processing using the semiconductor substrate 200 as a seed layer, or by depositing a semiconductor material. Thereafter, the semiconductor material filled in the channel holes may be planarized to expose the upper surface of the uppermost first insulating film 210.

Referring to FIG. 10B, vertical supports 230 penetrating the first and second insulating films 210 and 215 are formed in the contact region CR. More specifically, a plurality of dummy holes are formed for forming the vertical supports 230 around the memory cell region MR. The dummy holes may expose the surface of the semiconductor substrate 200. Thereafter, insulating material may be embedded in the dummy holes, and the upper portion may be planarized to form columnar vertical supports 230.

Specifically, the vertical supports 230 may be formed on the same line as the active pillars 224 of the memory cell region MR, and the vertical supports 230 may be formed symmetrically with respect to the memory cell region MR As shown in FIG. In addition, the vertical supports 230 may be formed on each side of the memory cell region MR in the line-type stack structure, or may be formed on both sides of the memory cell region MR, respectively. The plurality of vertical supports 230 formed on both sides of the memory cell region MR may be spaced apart from each other by a predetermined distance.

Referring to FIG. 10C, the first and second insulating films 210 and 215 of the contact region CR in which the vertical supports 230 are formed are patterned in the form of a step.

In the contact region CR, the height of the stacked first and second insulating films 210 and 215 decreases gradually toward the edge. Here, by patterning the first and second insulating films 210 and 215 in a stepwise manner, the vertical supports 230 of the contact region CR can also be etched together. That is, the vertical supports adjacent to the memory cell region MR pass through both the first and second insulating films 210 and 215, and the remaining vertical supports may be sequentially etched. Therefore, when a plurality of vertical supports 230 are formed on both sides of the memory cell region MR, the length of the plurality of vertical supports 230 decreases toward the edge of the contact region CR.

When the vertical supports 230 are formed on both sides of the memory cell region MR, the vertical supports 230 are etched when patterning the stacked first and second insulating films 210 and 215 in a stepwise manner. . That is, the vertical supports 230 may penetrate both the first and second insulating films 210 and 215 stacked.

After the first and second insulating films 210 and 215 of the contact region CR are patterned in a stepwise manner, an insulating film 240 is formed on the stepped first and second insulating films 210 and 215 . The insulating layer 240 may be planarized until the first insulating layer 210 located on the uppermost layer of the memory cell region MR is exposed.

 Next, the first and second insulating films 210 and 215 stacked in the form of a plate across the memory cell region MR and the contact regions CR are patterned to form line-type stack structures. Patterning of the first and second insulating films 210 and 215 in a line form may be performed before forming the active pillars 224 or the vertical supports 230. At this time, the line-shaped stack structure can expose the sidewalls of the first and second insulating films 210 and 215, and includes the active pillars 224 and the vertical supports 230 arranged in a line.

On the other hand, after forming the line-shaped stack structures, the horizontal supports described in the embodiment of the present invention may be formed in the memory cell region MR.

Referring to FIG. 10D, the second insulating films 215 formed between the first insulating films 210 are removed. Specifically, the second insulating layer 215 may be removed by supplying an etchant having a high etching selectivity to the second insulating layer 215 to the front surface of the semiconductor substrate 200 on which the line-shaped stack structures are formed. The first insulating layers 210 are vertically spaced from each other and are spaced apart from the active pillars 224 of the memory cell region MR and the active pillars 224 of the contact region CR. May be supported by vertical supports 230.

Referring to FIG. 10E, a conductive material may be filled between the first insulating layers 210 to form the gate electrodes 250 in the form of a line. More specifically, when a conductive material is deposited between the first insulating films 210, a conductive film 250 is formed between the first insulating films 210 to surround the active posts 224 and the vertical supports 230 . Thereafter, the conductive film 250 filled in between the adjacent line-shaped stack structures may be removed to form the gate electrodes 250 in the form of a line. Here, the conductive material may be polysilicon or a metal material.

Referring to FIG. 10F, contact plugs 260 connected to the gate electrodes 250 of the respective layers are formed in the contact regions CR of the gate electrodes 250. In the contact plugs 260, since the gate electrodes 250 of the contact region CR are formed in a stepped shape, the lengths of the contact plugs 260 can be changed.

After forming the contact plugs 260, they are electrically connected to the active pillars 224 and form bit lines 270 across the gate electrodes 250. Global word lines 275 may also be formed on the contact plugs 260.

FIGS. 11A to 11E are views sequentially illustrating a method of manufacturing a non-volatile memory device according to still another embodiment of the present invention.

Referring to FIG. 11A, first and second insulating films 210 and 215 having different etch selectivities are repeatedly stacked on a semiconductor substrate 200 so as to cover the memory cell region MR and the contact region CR Thereby forming a stacked structure in the form of a flat plate. That is, the sidewalls of the first and second insulating films 210 and 215 are aligned.

In a stacked structure in the form of a flat plate, the first and second insulating films 210 and 215 stacked on the contact region CR are patterned in the form of a step. That is, in the contact region CR, the stacking height of the first and second insulating films 210 and 215 gradually decreases toward the edge of the first and second insulating films 210 and 215.

Then, the planar stack structure is covered with an insulating film and planarized to equalize the heights of the memory cell region MR and the contact region CR. That is, the insulating film 240 may be formed on the stack structure in the form of a step.

Referring to FIG. 11B, active pillars 224a are formed in the memory cell region MR and vertical supports 224b are formed in the contact region CR.

More specifically, channel holes are formed in the memory cell region MR and dummy holes are formed in the contact region CR. The channel holes and the dummy holes may be formed by performing a normal photolithography process, and the channel holes may be formed in a planar matrix form. The dummy holes may be formed on one side of the channel holes located at the edge of the memory cell region MR, as shown in FIG. Also, as shown in FIG. 10, a plurality of dummy holes may be formed on the same line as the channel holes, and the dummy holes formed in the same line are spaced apart from each other. Here, the dummy hole adjacent to the channel hole may penetrate through all the first and second insulating films 210 and 215 stacked. The number of the first and second insulating films 210 and 215 passing through as the dummy holes are moved away from the memory cell region MR is sequentially reduced.

Then, charge storage films 222a and 222b are formed on the sidewalls of the channel holes and the dummy holes, and the semiconductor material is buried in the channel holes and the dummy holes to form the active pillars 224a and the vertical supports 224b. That is, the charge storage layers 222a and 222b may be formed around the active pillars 224a of the memory cell region MR and the vertical supports 224b of the contact region CR. The active pillars 224a and the vertical supports 224b may be formed to have the same length. On the other hand, the active pillars 224a of the memory cell region MR pass all of the stacked first and second insulating films 210 and 215, and the vertical supports 224b of the contact region CR are connected to the first And a part of the second insulating films 210 and 215.

 Referring to FIG. 11C, a planar stack structure including active pillars 224a and vertical supports 224b may be patterned to form line stack structures. As the line-shaped stack structures are formed, the sidewalls of the first and second insulating films 210 and 215 can be exposed.

On the other hand, after forming the line-shaped stack structures, the horizontal supports described in the embodiment of the present invention may be formed in the memory cell region MR.

Thereafter, an etching solution having a high etching selection ratio is supplied to the first insulating film 210 between the line-shaped stack structures, thereby removing the second insulating films 215. Accordingly, openings are formed between the first insulating films 210 that are vertically spaced from each other. The first insulating films 210 spaced apart from each other are electrically connected to the active pillars 224a of the memory cell region MR extending perpendicularly to the semiconductor substrate 200 and the vertical supports 224b of the contact region CR ). ≪ / RTI > That is, when the second insulating films 215 are removed through the wet etching process, the distance between the first insulating films 210 can be reduced or collapsed.

Referring to FIG. 11D, a conductive material may be filled between the first insulating layers 210 to form the gate electrodes 250 in the form of a line. Specifically, when a conductive material is deposited between the first insulating films 210, the conductive films 250 may be formed around the active pillars 224a and the vertical supports 224a. Thereafter, the gate electrode 250 in the form of a line may be formed between the first insulating films 210 by removing the conductive film 250 filled between the adjacent line-shaped stack structures. Here, the conductive material may be polysilicon or a metal material.

Referring to FIG. 11E, contact plugs 260 connected to the gate electrodes 250 of the respective layers are formed in the contact regions CR of the gate electrodes 250. In the contact plugs 260, since the gate electrodes 250 of the contact region CR are formed in a stepped shape, the lengths of the contact plugs 260 can be changed.

After forming the contact plugs 260, they are electrically connected to the active pillars 224 and form bit lines 270 across the gate electrodes 250. Global word lines 275 may also be formed on the contact plugs 260. The conductive pattern is not formed on the vertical supports 224b, such as the bit line 270 or the global word line 275, so that the operation of the non-volatile memory device according to the embodiment of the present invention is not affected.

On the other hand, the vertical supports 230 and 224b described with reference to Figs. 10A to 10E and Figs. 11A to 11E can be combined with the horizontal supports 124 described with reference to Figs. 2-9.

12 is a plan view of a non-volatile memory device fabricated in accordance with embodiments of the present invention

12, the gate electrodes LSL, WL and USL are formed in the form of a line, and the active pillars PL pass through the gate electrodes LSL, WL and USL of the memory cell region MR. The gate electrodes LSL, WL and USL of the contact region CR and the vertical supports SP having different lengths pass through the gate electrodes LSL, WL and USL. That is, vertical support posts SP are located at both ends of the gate electrodes LSL, WL, and USL. A plurality of vertical support posts SP may be formed on the same line as the active posts PL, and the vertical support posts SP on the same line are spaced apart from each other. Here, the active pillars PL and adjacent vertical supports SP can pass through all the gate electrodes LSL, WL, and USL. As the vertical supports SP are moved away from the memory cell region MR, the number of the first and second insulating films 210 and 215 through which the vertical supports SP pass can be sequentially reduced.

13 is a schematic diagram of a memory system including a non-volatile memory device in accordance with embodiments of the present invention.

13, the memory system 1100 may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, A memory card, or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes an input / output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions executed by the controller. The input / output device 1120 may receive data or signals from outside the system 1100, or output data or signals outside the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

Memory 1130 includes a non-volatile memory device in accordance with embodiments of the present invention. Memory 1130 may also include other types of memory, volatile memory that may be accessed at any time, and various other types of memory.

The interface 1140 serves to transmit data to and receive data from the communication network.

14 is a block diagram schematically illustrating an example of a memory card having a flash memory device according to an embodiment of the present invention.

Referring to FIG. 14, a memory card 1200 for supporting a high capacity data storage capability mounts a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 has a data exchange protocol of a host connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs all control operations for data exchange of the memory controller 1220. Although not shown in the drawings, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, It is obvious to those who have acquired knowledge.

According to the above flash memory device and memory card or memory system of the present invention, it is possible to provide a reliable memory system through the flash memory device 1210 with the erase characteristics of the dummy cells improved. In particular, the flash memory device of the present invention can be provided in a memory system such as a solid state disk (SSD) device which is actively in progress. In this case, a reliable memory system can be implemented by blocking read errors caused by dummy cells.

15 is a block diagram briefly showing an information processing system for mounting a flash memory system 1310 according to the present invention.

Referring to FIG. 15, the flash memory system 1310 of the present invention is installed in an information processing system such as a mobile device or a desktop computer. An information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, a user interface 1350, . The flash memory system 1310 will be configured substantially the same as the memory system or flash memory system mentioned above. The flash memory system 1310 stores data processed by the central processing unit 1330 or externally input data. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention can be provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. It is clear to those who have learned.

Further, the flash memory device or memory system according to the present invention can be mounted in various types of packages. For example, the flash memory device or the memory system according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is possible to solve this problem. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

1 is a simplified circuit diagram of a non-volatile memory device according to embodiments of the present invention.

FIGS. 2 to 9 are views sequentially illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

10A to 10F, a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention will be described in detail.

FIGS. 11A to 11E are views sequentially illustrating a method of manufacturing a non-volatile memory device according to still another embodiment of the present invention.

12 is a plan view of a non-volatile memory device fabricated in accordance with embodiments of the present invention

13 is a schematic diagram of a memory system including a non-volatile memory device in accordance with embodiments of the present invention.

14 is a block diagram schematically illustrating an example of a memory card having a flash memory device according to an embodiment of the present invention.

15 is a block diagram briefly showing an information processing system equipped with a flash memory system according to the present invention.

Claims (10)

A stack structure in which at least two or more first and second insulating films having different etching rates are alternately stacked is formed on a semiconductor substrate, Forming active columns connected to the semiconductor substrate through the first and second insulating films, Forming trenches through the stack structure between the active columns to form line stack structures, Forming horizontal supports that are in contact with the upper surfaces of the line stack structures over the adjacent line stack structures, Removing the second insulating films to form openings between the first insulating films, And forming conductive patterns locally in the openings. ≪ Desc / Clms Page number 20 > The method according to claim 1, Wherein the horizontal supports maintain spacing between the line stack structures. ≪ RTI ID = 0.0 > 18. < / RTI > The method according to claim 1, Wherein the horizontal supports are line patterns traversing the top surface of the plurality of line stack structures. ≪ RTI ID = 0.0 > 31. < / RTI > The method according to claim 1, Wherein the horizontal supports are patterns formed locally over the top surface of two adjacent line stack structures. ≪ RTI ID = 0.0 > 18. < / RTI > The method according to claim 1, The forming of the horizontal supports, A sacrificial insulating film is buried in the trenches, Further comprising forming the horizontal supports to contact top surfaces of the line stack structure and the sacrificial insulation layers. ≪ Desc / Clms Page number 20 > 6. The method of claim 5, Before forming the openings, Removing the sacrificial insulating film to expose sidewalls of the line stack structure. ≪ Desc / Clms Page number 22 > 6. The method of claim 5, Wherein the sacrificial insulating layer is formed of a material having an etch selectivity with respect to the first insulating layer. 6. The method of claim 5, Wherein the horizontal supports are formed of a material having an etch selectivity to the second insulating film and the sacrificial insulating film. The method according to claim 1, Further comprising forming vertical supports through the edge portions of the first insulating films. ≪ Desc / Clms Page number 20 > 10. The method of claim 9, The forming of the conductive patterns fills the space between the vertically adjacent first insulating films, Wherein the conductive patterns surround the active pillars and the vertical supports. ≪ Desc / Clms Page number 20 >

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