CN109841521B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN109841521B CN109841521B CN201711191620.8A CN201711191620A CN109841521B CN 109841521 B CN109841521 B CN 109841521B CN 201711191620 A CN201711191620 A CN 201711191620A CN 109841521 B CN109841521 B CN 109841521B
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Abstract
A semiconductor device and a method of forming the same, wherein the method comprises: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a material layer to be processed, and the surface of the material layer to be processed is provided with a bulge; performing one or more cycles of a surface treatment process until the protrusions are removed, the steps of the surface treatment process comprising: forming a covering layer on the surface of the material layer to be processed by adopting a spin coating process; etching the covering layer until the top area of the bulge is exposed; modifying the exposed surface material of the projection of the covering layer to form a modified layer on the surface of the projection; and after the modified layer is formed, etching to remove the modified layer and the covering layer. The method effectively improves the surface flatness of the material layer to be processed.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
MOS (metal-oxide-semiconductor) transistors, are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure located on a surface of a semiconductor substrate, the gate structure comprising: the gate electrode layer is positioned on the surface of the gate dielectric layer; and the source and drain doped regions are positioned in the semiconductor substrate at two sides of the grid structure.
With the development of semiconductor technology, the conventional planar MOS transistor has a weak ability to control channel current, resulting in a serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure.
However, the performance of the semiconductor device formed by the finfet in the prior art still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which can effectively improve the surface flatness of a material layer to be processed.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a material layer to be processed, and the surface of the material layer to be processed is provided with a bulge; performing one or more cycles of a surface treatment process until the protrusions are removed, the steps of the surface treatment process comprising: forming a covering layer on the surface of the material layer to be processed by adopting a spin coating process; etching the covering layer until the top area of the bulge is exposed; modifying the exposed surface material of the projection of the covering layer to form a modified layer on the surface of the projection; and after the modified layer is formed, etching to remove the modified layer and the covering layer.
Optionally, the material of the cover layer comprises silicon oxide; the material of the material layer to be processed is polysilicon; the modification treatment comprises an oxidation process; the material of the modified layer is silicon oxide.
Optionally, the oxidation process is a dry oxidation process, and the parameters include: the gas used comprises oxygen.
Optionally, the oxidation process is a wet oxidation process, and the adopted solution is H2O2And (3) solution.
Optionally, the material layer to be processed is located on the surface of the semiconductor substrate.
Optionally, the semiconductor substrate has a fin portion thereon; the material layer to be processed is located on the semiconductor substrate and the fin portion.
Optionally, the number of the fins is one or more.
Optionally, the semiconductor substrate includes a dense region and a sparse region; the semiconductor substrate dense area and the sparse area are respectively provided with a plurality of fin parts, and the distance between the adjacent fin parts of the dense area is smaller than the distance between the adjacent fin parts of the sparse area; the height of the bulges on the surface of the material layer to be processed in the dense area is greater than that of the bulges on the surface of the material layer to be processed in the sparse area.
Optionally, the method further includes: before the material layer to be processed is formed, forming an isolation structure covering the side wall of the fin part; after the isolation structure is formed, a gate dielectric material layer is formed on the surface of the fin portion; forming the material layer to be processed on the gate dielectric material layer and the isolation structure; and after the one or more times of circulating surface treatment processes are carried out, the material layer to be treated and the gate dielectric material layer are patterned to form a gate structure crossing the fin part.
Optionally, the process of etching the capping layer until the top region of the protrusion is exposed comprises an atomic layer etching process.
Optionally, when the number of times of the surface treatment process is multiple, the thickness of the modified layer formed by the surface treatment process is gradually reduced.
Optionally, when the number of times of the surface treatment process is multiple, the thickness of the modification layer formed by each time of the surface treatment process is the same.
Optionally, when the number of surface treatment processes is multiple, the thickness of the modified layer formed in each surface treatment process ranges from 0.5A to 5A.
Optionally, the process of removing the modification layer and the cover layer by etching is a wet etching process, a dry etching process or an atomic layer etching process.
Optionally, the method further includes: before the one or more times of circulating surface treatment processes, carrying out chemical mechanical grinding on the surface of the material layer to be treated.
Optionally, the number of times of performing the surface treatment process is 5 to 500 times.
The invention also provides a semiconductor device formed by any one of the methods.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the semiconductor device provided by the technical scheme of the invention, in each surface treatment process, the coating layer is formed on the surface of the material layer to be treated by adopting a spin coating process, so that the flatness of the top surface of the coating layer is better. Because the top surface of the covering layer is relatively flat, the thickness of the covering layer at the top of the protrusion is smaller than that of the covering layer at the side part of the protrusion, and when the covering layer is etched to expose the top area of the protrusion, the side part of the protrusion is also provided with the covering layer covering the surface of the material layer to be processed. And after modifying the exposed surface material of the bump to form a modified layer, etching to remove the modified layer and the covering layer, thereby reducing the height of the bump. Because the covering layer on the side part of the bulge protects the surface of the material layer to be processed in the process of removing the modified layer, the surface of the material layer to be processed on the side part of the bulge is prevented from being greatly lost in the process of removing the modified layer. Secondly, the thickness of the covering layer on the surface of the material layer to be processed on the side part of the bulge is consistent, and in the process of removing the modified layer and the covering layer by etching, the consumption degree of each area on the surface of the material layer to be processed on the side part of the bulge is prevented from having great difference. In conclusion, after the surface treatment process, the protrusions can be removed, and the flatness of the whole surface of the material layer to be treated is better.
Further, the process of etching the capping layer until the top region of the protrusion is exposed includes an atomic layer etching process, which can precisely control the etching process.
Further, before the one or more times of circulating surface treatment process, the surface of the material layer to be treated is subjected to chemical mechanical polishing, so that the height of the protrusion is reduced, and the height of the protrusion can be reduced in a short time by the chemical mechanical polishing; after the surface of the material layer to be treated is subjected to chemical mechanical polishing, the surface of the material layer to be treated can be well flattened only by carrying out a surface treatment process for a few times of circulation. Therefore, the process efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor device;
fig. 2 to 11 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices formed by the prior art is poor.
A method for forming a semiconductor device, please refer to fig. 1, comprising: providing a semiconductor substrate 100, wherein the semiconductor substrate 100 is provided with a fin part 110; forming a gate dielectric material layer 120 on the semiconductor substrate 100 and the fin portion 110; a layer of gate electrode material 130 is deposited over the layer of gate dielectric material 120.
The gate electrode material layer 130 is used to form a part of the gate structure after being patterned, and in order to make the electrical performance stability of the gate structure better, the surface of the gate electrode material layer 130 needs to be made more planar.
Since the fin 110 protrudes from the semiconductor substrate 100, after the gate electrode material layer 130 is formed by a deposition process, the gate electrode material layer 130 has a protrusion at a position corresponding to the fin 110. In order to improve the flatness of the surface of the gate electrode material layer 130, one method is: the surface of the gate electrode material layer 130 is polished by a chemical mechanical polishing process. The surface of the gate electrode material layer 130 is polished by a chemical mechanical polishing process, so that the height of the protrusions can be reduced to a certain extent. However, when the polishing protrusion is raised to a height close to the surface of the gate electrode material layer 130, the surface of the gate electrode material layer 130 on the side of the protrusion is also polished while the protrusion is polished, so that the protrusion is difficult to completely remove, and the surface flatness of the gate electrode material layer 130 is poor. Even if the polishing time of the chemical mechanical polishing process is increased, the flatness of the surface of the gate electrode material layer 130 cannot be ensured.
On the basis, the invention provides a method for forming a semiconductor device, wherein a material layer to be processed is arranged on a semiconductor substrate, and a bulge is arranged on the surface of the material layer to be processed; performing one or more cycles of a surface treatment process until the protrusions are removed, the steps of the surface treatment process comprising: forming a covering layer on the surface of the material layer to be processed by adopting a spin coating process; etching the covering layer until the top area of the bulge is exposed; modifying the exposed surface material of the projection of the covering layer to form a modified layer on the surface of the projection; and etching to remove the modified layer and the covering layer. The method effectively improves the surface flatness of the material layer to be processed.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 11 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 2, a semiconductor substrate 200 is provided, the semiconductor substrate 200 has a material layer 221 to be processed thereon, and a surface of the material layer 221 to be processed has a protrusion.
In this embodiment, the semiconductor substrate 200 has a fin portion 210 thereon, and the material layer to be processed 221 is located on the semiconductor substrate 200 and the fin portion 210. In other embodiments, the layer of material to be processed is located on the surface of the semiconductor substrate.
In this embodiment, the material layer to be processed 221 is taken as a gate electrode material layer as an example for explanation.
The semiconductor substrate 200 provides a process platform for forming semiconductor devices.
The semiconductor substrate 200 may be single crystalline silicon, polycrystalline silicon, or amorphous silicon. The semiconductor substrate 200 may be a semiconductor material such as silicon, germanium, or silicon germanium. In this embodiment, the material of the semiconductor substrate 200 is single crystal silicon.
In this embodiment, the semiconductor substrate 200 includes a dense region and a sparse region, the dense region and the sparse region of the semiconductor substrate 200 each have a plurality of fins 210, a distance between adjacent fins 210 in the dense region is smaller than a distance between adjacent fins 210 in the sparse region, and a protrusion height of the surface of the material layer to be processed 221 in the dense region is greater than a protrusion height of the surface of the material layer to be processed 221 in the sparse region. In other embodiments, the semiconductor substrate does not distinguish between dense and sparse regions.
The position of the protrusion corresponds to the position of the fin portion 210, and the protrusion is located on the fin portion 210.
The fin 210 is formed by patterning a semiconductor substrate. Or: forming a fin material layer on the semiconductor substrate 200; the fin material layer is patterned to form a fin 210.
The number of the fins 210 is one or more. In this embodiment, the number of the fins 210 is more than one.
The process for forming the gate electrode material layer is a deposition process, such as a plasma chemical vapor deposition process or a low pressure chemical vapor deposition process.
The gate electrode material layer is made of polysilicon.
In this embodiment, the method further includes: before forming the material layer to be processed 221, an isolation structure 201 covering a portion of the sidewall of the fin 210 is formed, and a top surface of the isolation structure 201 is lower than a top surface of the fin 210. The material of the isolation structure 201 comprises silicon oxide; after the isolation structure 201 is formed, a gate dielectric material layer 220 is formed on the surface of the fin portion 210; the material layer to be processed 221 is formed on the gate dielectric material layer 220 and the isolation structure 201.
In this embodiment, the gate dielectric material layer 220 is located on the surface of the fin portion 210 and the surface of the isolation structure 201, and accordingly, the process for forming the gate dielectric material layer 220 is a deposition process, and the gate dielectric material layer 220 is made of silicon oxide or a high K (K is greater than 3.9) dielectric material. In other embodiments, the gate dielectric material layer is only located on the surface of the fin portion, and accordingly, the process of forming the gate dielectric material layer is an oxidation process, and the material of the gate dielectric material layer includes silicon oxide.
Then, carrying out one or more times of circulating surface treatment process until the protrusion is removed, wherein the surface treatment process comprises the following steps: forming a covering layer on the surface of the material layer to be processed by adopting a spin coating process; etching the covering layer until the top area of the bulge is exposed; modifying the exposed surface material of the projection of the covering layer to form a modified layer on the surface of the projection; and after the modified layer is formed, etching to remove the modified layer and the covering layer.
The present embodiment exemplifies the surface treatment process performed three cycles until the projections are removed. In other embodiments, two, four, five or more cycles of the surface treatment process are performed.
Referring to fig. 3, a first capping layer 230 is formed on the surface of the material layer 221 to be processed by using a spin coating process.
The material of the first capping layer 230 includes silicon oxide.
The first capping layer 230 is formed by a spin coating process, so that the surface of the first capping layer 230 has better flatness.
Referring to fig. 4, the first capping layer 230 is etched until the top region of the protrusion is exposed.
In this embodiment, the process of etching the first cover layer 230 until the top region of the protrusion is exposed is an atomic layer etching process, which has the following advantages: the etching process can be accurately controlled, and the probability of completely removing the first covering layer 230 on the side of the protrusion is reduced.
The atomic layer etch process includes multiple atomic layer etch cycles. Only one atomic layer etch cycle is described below.
In etching the first capping layer 230, the atomic layer etch cycle includes: introducing a first gas into the chamber, wherein the first gas is adsorbed on the surface of the first cover layer 230, and the first gas is combined with the suspension bonds on the surface of the first cover layer 230 to form an adsorption modified layer on the surface of the first cover layer 230; the process of forming the adsorption modification layer has "self-limiting", and once the surface of the first cover layer 230 is saturated with the first gas, the process of forming the adsorption modification layer is immediately stopped; then, removing the excess first gas in the chamber; after the excessive first gas in the chamber is removed, introducing a second gas into the chamber and removing the adsorption modification layer by an ion bombardment method, wherein the process of removing the adsorption modification layer is self-limiting, namely once the adsorption modification layer is completely removed, the process of ion bombardment is also terminated; thereafter, the by-products after the ion bombardment and the excess second gas are discharged.
In other embodiments, the process of etching the first capping layer until the top region of the protrusion is exposed is a dry etching process or a wet etching process.
Referring to fig. 5, the exposed surface material of the protrusions of the first cover layer 230 is modified to form a first modified layer 240 on the surface of the protrusions.
The modification treatment includes an oxidation process, such as a dry oxidation process or a wet oxidation process.
The material of the first modification layer 240 includes silicon oxide.
When the modification treatment adopts a dry oxidation process, the parameters of the dry oxidation process comprise: the gas used comprises oxygen at a temperature of 100-500 deg.C, for example 350 deg.C.
When the modification treatment adopts a wet oxidation process, the parameters of the wet oxidation process comprise: the solution used is H2O2And (3) solution.
Referring to fig. 6, after the first modified layer 240 is formed, the first modified layer 240 and the first capping layer 230 are etched away.
The process of removing the first modified layer 240 and the first capping layer 230 by etching is a wet etching process, a dry etching process or an atomic layer etching process.
In this embodiment, the process of removing the first modified layer 240 and the first cover layer 230 by etching is an atomic layer etching process, and has the following advantages: the etching process can be accurately controlled.
In this embodiment, the first modified layer 240 and the first capping layer 230 are removed by etching in a single etching process, which simplifies the process.
Referring to fig. 7, after the first modified layer 240 and the first capping layer 230 are removed by etching, a second capping layer 231 is formed on the surface of the material layer 221 to be processed by using a spin coating process.
The material of the second cover layer 231 is referred to the material of the first cover layer 230.
The second capping layer 231 is formed by a spin coating process, so that the surface of the second capping layer 231 has better flatness.
Referring to fig. 8, the second capping layer 231 is etched until the top region of the protrusion is exposed.
In this embodiment, the process of etching the second cover layer 231 until the top area of the protrusion is exposed is an atomic layer etching process, which has the following advantages: the etching process can be accurately controlled, and the probability of completely removing the second cover layer 231 on the side of the protrusion is reduced.
In other embodiments, the process of etching the second capping layer until the top region of the protrusion is exposed is a dry etching process or a wet etching process.
Referring to fig. 9, the exposed surface material of the second cover layer 231 is modified to form a second modified layer 241 on the surface of the protrusion.
The modification of the exposed surface material of the second cover layer 231 is not described in detail with reference to the modification of the exposed surface material of the first cover layer 230.
The material of the second modification layer 241 includes silicon oxide.
Referring to fig. 10, after the second modified layer 241 is formed, the second modified layer 241 and the second capping layer 231 are etched away.
The process of removing the second modification layer 241 and the second capping layer 231 by etching is a wet etching process, a dry etching process or an atomic layer etching process.
In this embodiment, the process of removing the second modified layer 241 and the second covering layer 231 by etching is an atomic layer etching process, and has the following advantages: the etching process can be accurately controlled.
In this embodiment, the second modified layer 241 and the second capping layer 231 are removed by etching in one etching process, which simplifies the process.
Then, after the second modified layer 241 and the second covering layer 231 are removed by etching, a third covering layer is formed on the surface of the material layer 221 to be processed by adopting a spin coating process; etching the third covering layer until the top area of the bulge is exposed; modifying the exposed surface material of the projection of the third covering layer to form a third modified layer on the surface of the projection; and after the third modified layer is formed, etching to remove the third modified layer and the third covering layer.
The material of the third cover layer is referenced to the material of the first cover layer 230.
And the third covering layer is formed by adopting a spin coating process, so that the surface flatness of the third covering layer is better.
In this embodiment, the process of etching the third cover layer until the top region of the protrusion is exposed is an atomic layer etching process, which has the following advantages: the etching process can be accurately controlled, and the probability of completely removing the third covering layer on the side part of the protrusion is reduced.
In other embodiments, the process of etching the third capping layer until the top region of the protrusion is exposed is a dry etching process or a wet etching process.
The exposed surface material of the third cover layer 232 is modified, and the modification of the exposed surface material of the first cover layer 230 is referred to and will not be described in detail.
The third modification layer is made of silicon oxide.
The process of removing the third modified layer and the third capping layer by etching refers to the process of removing the first modified layer 240 and the first capping layer 230 by etching.
In this embodiment, after the surface treatment process is performed for three cycles, the surface of the material layer 221 to be treated has better surface flatness (refer to fig. 11).
In this embodiment, when the number of times of the surface treatment process is plural, the thickness of the modified layer formed by the surface treatment process is gradually reduced. In the previous times of the surface treatment process, the modification layer with larger thickness is formed, and the modification layer with larger thickness is correspondingly removed, so that the process efficiency is improved; in the subsequent times of the surface treatment process, the modification layer with smaller thickness is formed, so that the surface bulge of the material layer to be treated is reduced to the maximum extent, the flatness of the material layer to be treated is ensured, and the process requirement is met.
When the thickness of the modified layer formed by the surface treatment process is gradually reduced, the thickness of the modified layer formed in the last surface treatment process is in the range of 0.5-5 angstroms.
In other embodiments, when the number of surface treatment processes is multiple, the thickness of the modified layer formed by each surface treatment process is the same.
In one embodiment, when the number of surface treatment processes is plural, the thickness of the modified layer formed in each surface treatment process ranges from 0.5A to 5A.
In each surface treatment process, a coating layer is formed on the surface of the material layer to be treated by adopting a spin coating process, so that the flatness of the top surface of the coating layer is better. Because the top surface of the covering layer is relatively flat, the thickness of the covering layer at the top of the protrusion is smaller than that of the covering layer at the side part of the protrusion, and when the covering layer is etched to expose the top area of the protrusion, the side part of the protrusion is also provided with the covering layer covering the surface of the material layer to be processed. And after modifying the exposed surface material of the bump to form a modified layer, etching to remove the modified layer and the covering layer, thereby reducing the height of the bump. Because the covering layer on the side part of the bulge protects the surface of the material layer to be processed in the process of removing the modified layer, the surface of the material layer to be processed on the side part of the bulge is prevented from being greatly lost in the process of removing the modified layer. Secondly, the thickness of the covering layer on the surface of the material layer to be processed on the side part of the bulge is consistent, and in the process of removing the modified layer and the covering layer by etching, the consumption degree of each area on the surface of the material layer to be processed on the side part of the bulge is prevented from having great difference. In conclusion, after the surface treatment process, the protrusions can be removed, and the flatness of the whole surface of the material layer to be treated is better.
In this embodiment, after the surface treatment process is performed, the heights of the surfaces of the material layer 221 to be treated in the dense region and the material layer 221 to be treated in the sparse region are relatively consistent, and the surface flatness of the material layer 221 to be treated in the dense region and the material layer 221 to be treated in the sparse region is relatively good.
In this embodiment, before performing the one or more cycles of the surface treatment process, the method further includes: the surface of the material layer to be treated is subjected to chemical mechanical polishing, so that the height of the protrusion is reduced, and the height of the protrusion can be reduced in a short time by the chemical mechanical polishing; after the surface of the material layer to be treated is subjected to chemical mechanical polishing, the surface of the material layer to be treated can be well flattened only by carrying out a surface treatment process for a few times of circulation. Therefore, the process efficiency is improved.
In other embodiments, the surface of the material layer to be treated is not subjected to chemical mechanical polishing prior to the one or more cycles of the surface treatment process.
In one embodiment, the surface treatment process is performed 5 to 500 times. If the times of the surface treatment process are too many, the improvement of the surface flatness of the material layer to be treated reaches the limit of the process, and the surface flatness of the material layer to be treated cannot be further improved by increasing the times of the surface treatment process continuously, so that the process is wasted.
In this embodiment, after performing the one or more cycles of the surface treatment process, the method further includes: patterning the material layer to be processed 221 and the gate dielectric material layer 220 to form a gate structure crossing the fin portion 210, wherein the gate structure covers part of the top surface and part of the side wall surface of the fin portion 210; source and drain doped regions are formed in fin 210 on both sides of the gate structure.
Accordingly, the present embodiment also provides a semiconductor device formed by the above method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a material layer to be processed, and the surface of the material layer to be processed is provided with a bulge;
performing one or more cycles of a surface treatment process until the protrusions are removed, the steps of the surface treatment process comprising:
forming a covering layer on the surface of the material layer to be processed by adopting a spin coating process;
etching the covering layer until the top area of the bulge is exposed;
modifying the exposed surface material of the projection of the covering layer to form a modified layer on the surface of the projection;
after the modified layer is formed, etching to remove the modified layer and the covering layer;
the material of the covering layer comprises silicon oxide; the material of the material layer to be processed is polysilicon; the modification treatment comprises an oxidation process; the material of the modified layer is silicon oxide.
2. The method of claim 1, wherein the oxidation process is a dry oxidation process, and parameters include: the gas used comprises oxygen.
3. The method of claim 1, wherein the oxidation process is a wet oxidation process and the solution is H2O2And (3) solution.
4. The method according to claim 1, wherein the material layer to be processed is located on a surface of a semiconductor substrate.
5. The method for forming a semiconductor device according to claim 1, wherein the semiconductor substrate has a fin portion thereon; the material layer to be processed is located on the semiconductor substrate and the fin portion.
6. The method of claim 5, wherein the number of fins is one or more.
7. The method for forming a semiconductor device according to claim 5, wherein the semiconductor substrate includes a dense region and a sparse region; the semiconductor substrate dense area and the sparse area are respectively provided with a plurality of fin parts, and the distance between the adjacent fin parts of the dense area is smaller than the distance between the adjacent fin parts of the sparse area; the height of the bulges on the surface of the material layer to be processed in the dense area is greater than that of the bulges on the surface of the material layer to be processed in the sparse area.
8. The method for forming a semiconductor device according to claim 5, further comprising: before the material layer to be processed is formed, forming an isolation structure covering the side wall of the fin part; after the isolation structure is formed, a gate dielectric material layer is formed on the surface of the fin portion; forming the material layer to be processed on the gate dielectric material layer and the isolation structure; and after the one or more times of circulating surface treatment processes are carried out, the material layer to be treated and the gate dielectric material layer are patterned to form a gate structure crossing the fin part.
9. The method of claim 1, wherein the process of etching the cap layer until the top region of the protrusion is exposed comprises an atomic layer etching process.
10. The method for forming a semiconductor device according to claim 1, wherein when the number of times of the surface treatment process is plural, the thickness of the modified layer formed by the surface treatment process is gradually decreased.
11. The method for forming a semiconductor device according to claim 1, wherein when the number of surface treatment processes is plural, the thickness of the modified layer formed by each surface treatment process is the same.
12. The method for forming a semiconductor device according to claim 1, wherein when the number of surface treatment processes is plural, a thickness of the modified layer formed in each surface treatment process is in a range of 0.5A to 5A.
13. The method for forming a semiconductor device according to claim 1, wherein the process of removing the modification layer and the capping layer by etching is a wet etching process, a dry etching process, or an atomic layer etching process.
14. The method for forming a semiconductor device according to claim 1, further comprising: before the one or more times of circulating surface treatment processes, carrying out chemical mechanical grinding on the surface of the material layer to be treated.
15. The method for forming a semiconductor device according to claim 1, wherein the surface treatment process is performed 5 to 500 times.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117216A (en) * | 2011-11-17 | 2013-05-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method for semiconductor component preventing unfilled corner from being generated in shallow groove isolation structure |
| CN105845557A (en) * | 2016-05-17 | 2016-08-10 | 上海华力微电子有限公司 | Polysilicon gate flattening method |
| CN107230635A (en) * | 2016-03-24 | 2017-10-03 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150021811A (en) * | 2013-08-21 | 2015-03-03 | 삼성전자주식회사 | Method of manufacturing the semiconductor device |
-
2017
- 2017-11-24 CN CN201711191620.8A patent/CN109841521B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117216A (en) * | 2011-11-17 | 2013-05-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method for semiconductor component preventing unfilled corner from being generated in shallow groove isolation structure |
| CN107230635A (en) * | 2016-03-24 | 2017-10-03 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
| CN105845557A (en) * | 2016-05-17 | 2016-08-10 | 上海华力微电子有限公司 | Polysilicon gate flattening method |
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