CN111554574B - Planarization method, semiconductor device and manufacturing method thereof - Google Patents

Planarization method, semiconductor device and manufacturing method thereof Download PDF

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CN111554574B
CN111554574B CN202010426605.2A CN202010426605A CN111554574B CN 111554574 B CN111554574 B CN 111554574B CN 202010426605 A CN202010426605 A CN 202010426605A CN 111554574 B CN111554574 B CN 111554574B
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material layer
substrate
planarization
layer
semiconductor device
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CN111554574A (en
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金光复
杨涛
胡艳鹏
卢一泓
刘青
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

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Abstract

The invention discloses a planarization method, a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to solve the problem of height difference when removing a crystal boundary generated by an evaporation gate electrode material. The planarization method comprises the following steps: providing a substrate; forming a material layer on a substrate; modifying the material layer to enable the surface roughness of the modified material layer to be smaller than that of the material layer before modification; and removing the upper part of the material layer to planarize the material layer. The planarization method provided by the invention is used for forming the semiconductor device. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Description

Planarization method, semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a planarization method, a semiconductor device and a manufacturing method thereof.
Background
Dynamic Random Access Memory (DRAM) represents whether a binary bit (bit) is a 1 or a 0 by using how much charge is stored in a capacitor. The DRAM has a simple structure, and each bit of data only needs one capacitor and one transistor for processing. At the same time, the DRAM has high density, higher capacity per unit volume and lower cost.
As semiconductor memory devices become highly integrated, it is necessary to form a desired structure by vapor deposition materials when manufacturing DRAMs. For example: in forming the gate electrode, it is necessary to evaporate a gate electrode material (e.g., tungsten). However, grain boundaries are easily generated in the process of evaporating the gate electrode material, so that after the gate electrode material is subjected to planarization treatment, the planarized gate electrode material still has height difference, and the performance of the memory device is affected when a subsequent manufacturing process is performed.
Disclosure of Invention
The invention aims to provide a planarization method, a semiconductor device and a manufacturing method thereof, which are used for avoiding height difference generated when a gate electrode material is formed by evaporation.
In order to achieve the above object, the present invention provides a planarization method. The planarization method comprises the following steps:
providing a substrate;
forming a material layer on a substrate;
modifying the material layer to enable the surface roughness of the modified material layer to be smaller than that of the material layer before modification;
and removing the upper part of the material layer to planarize the material layer.
Compared with the prior art, in the planarization method provided by the invention, the material layer formed on the substrate is modified, so that the surface roughness of the material layer after modification is smaller than that of the material layer before modification, and the modification depth of the material layer is consistent. On the basis, when the substrate is subjected to planarization treatment, the upper material of the material layer can be conveniently removed. The upper part of the material layer is removed, meanwhile, the lower part of the material layer can be ensured to be flattened, and the flattened surface levelness is better. Therefore, when the planarization method provided by the invention is applied to planarization of the evaporated gate electrode material, the surface height difference generated by the crystal boundary can be reduced after the gate electrode material is planarized, and the performance of a high memory device is further ensured.
The invention also provides a semiconductor device. The semiconductor device includes: and a gate electrode formed by using the planarization layer formed by the planarization method.
Compared with the prior art, the semiconductor device provided by the invention has the same beneficial effect as the planarization method in the technical scheme, and the detailed description is omitted here.
The invention also provides a manufacturing method of the semiconductor device. The manufacturing method of the semiconductor device comprises the following steps:
providing a substrate;
forming a conductive material layer on a substrate;
flattening the conductive material layer by adopting the flattening method to form a flattening layer on the substrate;
and processing the planarization layer to obtain the gate electrode formed on the substrate.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention has the same beneficial effects as the planarization method in the technical scheme, and the details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 illustrates a schematic diagram of a structure formed after a prior art planarization process;
FIG. 2 is a schematic diagram of a structure formed after a planarization method according to an embodiment of the present invention;
fig. 3 to 6 are process diagrams illustrating a planarization method provided by an embodiment of the present invention;
fig. 7 shows a schematic diagram of forming a gate electrode in an embodiment of the invention.
Reference numerals:
a substrate 100, a trench 102, a material layer 104, an upper portion 106 of the material layer, a lower portion 108 of the material layer, an oxide film 110, a gate electrode 112, a first active region 114, and a second active region 116.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
A Dynamic Random Access Memory (DRAM) is a volatile Memory, and includes a Memory area (Memory cell region) composed of a plurality of Memory cells (Memory cells) and a peripheral area (peripheral area) composed of a control circuit. Each memory cell includes a transistor (transistor) electrically connected to a capacitor (capacitor), the transistor controlling the storage or release of charge in the capacitor for the purpose of storing data. The control circuit may be positioned to each memory cell to control access to its data using word lines (abbreviated WL) and bit lines (abbreviated BL) that traverse the memory region and are electrically connected to the memory cells.
As a result of analysis of the semiconductor device, it has been found that, in the conventional technique, a desired structure is formed by a vapor deposition material when manufacturing a DRAM. For example: in forming the gate electrode 112, a gate electrode material (e.g., tungsten) needs to be evaporated. Grain boundaries are easily generated during the process of evaporating the gate electrode material. This is due to the manner in which the metal tungsten is deposited. The metal tungsten is usually grown by CVD, and the growth process requires the formation of crystal nuclei, and the tungsten thin film has a polycrystalline structure due to the crystal nucleus growth, so that grain boundaries are easily generated. Moreover, the crystal nucleus at the initial stage of film formation is relatively large, and the surface of the tungsten thin film grown based on the crystal nucleus is very rough, so that after the gate electrode material is subjected to planarization treatment, the planarized gate electrode material has height difference (as shown in fig. 1) between the inside of the wafer and a local pattern area, and further the formation of a subsequent transistor is influenced, so that the performance of a manufactured and formed memory device is poor.
In order to solve the above problems, embodiments of the present invention provide a planarization method, a semiconductor device and a method for fabricating the same, which utilize a novel planarization method (as shown in fig. 4) to make the upper portion 106 of the material layer less rigid than the lower portion 108 of the material layer, and the interface between the upper portion 106 of the material layer and the lower portion 108 of the material layer is parallel or nearly parallel to the substrate 100. After the planarization process is performed on the material layer 104, the height difference of the lower portion 108 of the material layer (as shown in fig. 2) can be reduced as much as possible, thereby improving the performance of the memory device. The semiconductor device manufactured by the above planarization method and the manufacturing method of the semiconductor device have the same effects.
For convenience of description, only the differences between the planarization method provided by the embodiment of the present invention and the planarization method in the prior art will be described below, and other undescribed steps may refer to the description in the prior art. Of course, those skilled in the art can also modify the existing other planarization methods based on the following description of the embodiments of the present invention.
In view of the above problems, fig. 3 to 6 show process diagrams of a planarization method provided by an embodiment of the present invention. The embodiment of the invention provides a planarization method. The planarization method may be to planarize the existing semiconductor film layer, or may be to planarize the metal electrode. As shown in fig. 3 to 6, the planarization method includes:
step 1: as shown in fig. 3, a substrate 100 is provided. The substrate 100 may be, for example, a bulk silicon substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, a silicon germanium substrate, or an epitaxial thin film substrate formed by epitaxial growth. The following description will be made taking a silicon substrate as an example.
As shown in fig. 3, in some alternatives, a trench 102 may be opened in the substrate 100. Illustratively, trenches 102 are formed in substrate 100 by etching down using a metal oxide as an etch mask for etching trenches 102 in substrate 100, trenches 102 may each be in the shape of a rounded U, a right-angled U, an elliptical U, or a trapezoid. Of course, the manner of forming the trench 102 is not limited thereto, and other manners suitable for practical use may also be adopted.
Step 2: as shown in fig. 4, a material layer 104 is formed on the substrate 100. The material layer 104 may be formed by a Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), evaporation, or the like process. Illustratively, the tungsten material layer is formed by CVD of metal tungsten or vapor deposition of metal tungsten. Of course, the material layer 104 may be formed by using a conductive material such as copper, nickel, or titanium, or a semiconductor material such as germanium or silicon, according to the actual situation, but is not limited thereto. The material layer 104 may be formed in other practical ways, and the thickness of the material layer 104 may be selected according to practical situations.
And step 3: as shown in fig. 4 and 5, the material layer 104 is modified such that the surface roughness of the material layer after modification is less than the surface roughness of the material layer before modification, and the upper portion 106 of the material layer has a hardness less than the lower portion 108 of the material layer. The interface of the upper portion 106 of the material layer and the lower portion 108 of the material layer is parallel or nearly parallel to the substrate 100.
As shown in fig. 4 and 5, in the embodiment of the present invention, a method for performing modification treatment on the material layer 104 includes: the material layer 104 is subjected to a surface treatment to form an oxide material layer with a certain thickness. The interface between the oxidized material layer and the lower portion 108 of the material layer is parallel or approximately parallel to the substrate 100, i.e., the depth of the lower surface of the oxidized material layer 104 from the substrate 100 is consistent or approximately consistent, so that the interface between the oxidized material layer and the lower portion 108 of the material layer and the substrate 100 are parallel or approximately parallel. Illustratively, the oxidation treatment is performed on the tungsten material layer to obtain the oxide film 110. For example: tungsten is oxidized by means of rapid thermal oxidation. Wherein the working gas for rapid thermal oxidation is oxygen or oxygen plasma, the temperature is 300-1000 ℃, and the time is 10-3600 s. Of course, tungsten oxide may be used in other ways, but is not limited thereto.
As shown in FIGS. 4 and 5, the oxide film 110 formed by oxidizing the tungsten material layer has a thickness of
Figure BDA0002498902120000065
I.e. the upper part 106 of the material layer has a thickness of
Figure BDA0002498902120000066
At this time, the oxide film 110 is spaced from the lower portion 108 of the material layer or the upper surface of the substrate 100 by a certain distance, so that the substrate 100 is not damaged when the material layer 104 is subsequently planarized, and the structure formed in the substrate 100 is not damaged, thereby not affecting the performance of the subsequent memory device. Since the depth of the lower surface of the oxidized tungsten material layer from the substrate 100 is uniform, the interface between the formed oxide film 110 and the lower portion 108 of the material layer is parallel or nearly parallel to the substrate 100. On this basis, when the substrate 100 is subjected to the planarization treatment, the oxide film 110 can be removed easily. While removing the oxide film 110, the lower portion 108 of the material layer can be ensured to be planarized, and the planarized surface level is good. In the process of oxidizing the tungsten material surface layer, the grain boundary of the film material is weakened, and a material layer which is easier to remove in a flattening way is formed. Meanwhile, in the planarization process, the removal rate of the oxidized material is greater than that of the unoxidized material, so that the unoxidized material can play a role of a planarization stop layer, the height difference of the residual tungsten material layer is remarkably reduced, and the performance of the device is improved. For example, the thickness of the oxide film 110 formed by oxidizing the tungsten material layer may be set to
Figure BDA0002498902120000061
Or
Figure BDA0002498902120000062
However, the thickness of the oxide film 110 may be adjusted according to the actual application.
As shown in fig. 4 and 5, when the semiconductor material layer is formed by depositing a semiconductor material on the substrate 100, the above oxidation may also be used to form a semiconductor oxide layer on the upper portion 106 of the semiconductor material layer, and the thickness of the semiconductor oxide layer may be set as
Figure BDA0002498902120000063
Or
Figure BDA0002498902120000064
But not limited thereto, in practiceIn use, the thickness of the formed semiconductor oxide layer can be adjusted according to actual conditions.
And 4, step 4: as shown in fig. 4-6, the upper portion 106 of the material layer is removed with the lower portion 108 of the material layer as a stop layer, so that the substrate 100 is planarized. Because the upper portion 106 of the material layer is less rigid than the lower portion 108 of the material layer, the upper portion 106 of the material layer may be easily removed. Furthermore, since the interface between the upper portion 106 of the material layer and the lower portion 108 of the material layer is parallel or nearly parallel to the substrate 100, the levelness of the material layer after planarization is relatively good, and the surface level difference is close to zero.
As shown in fig. 4 to 6, for example, the oxide film 110 formed by oxidizing the tungsten material layer is removed when the planarization process is used. Since the upper portion 106 of the tungsten material layer is oxidized to form the oxide film 110, the hardness of the oxide film 110 is lower than the hardness of the lower portion 108 of the material layer, and the oxide film 110 is easily processed during Chemical Mechanical Planarization (CMP). By using the material removal selection ratio of the metal tungsten oxide film 110 and the unoxidized metal tungsten, the oxide film 110 can be effectively removed, and a metal tungsten film with the same residual height is formed. Note: CMP is a cyclic process of oxidation-removal; the pre-oxidation treatment is equivalent to weakening the effect of the metal large crystal particles on the CMP.
The embodiment of the invention also provides a semiconductor device. As shown in fig. 7, the semiconductor device may be various existing transistors. The semiconductor device includes: substrate 100, and a gate stack (not shown in fig. 7), a first active region 114, and a second active region 116. The semiconductor device provided by the embodiment of the invention is described below by taking a buried channel transistor as an example.
As shown in fig. 7, the selection of the substrate 100 can be referred to above, and is not described herein again. The substrate 100 further has a trench (not shown in fig. 7), and the first active region 114 and the second active region 116 may be located around the trench. Of course, the position and size of the trench and the active region may be set according to the type of the transistor and the practical application scenario, and are not limited in detail herein.
As shown in fig. 7, the gate stack includes a gate dielectric layer (not shown in fig. 7) and a gate conductor layer (not shown in fig. 7). The gate conductor layer includes a barrier layer (not shown in fig. 7) and a gate electrode 112. The gate electrode 112 is formed using a planarization layer (not shown in fig. 7) formed by the above-described planarization method. Namely, the gate electrode material is planarized by the planarization method, and then the planarization layer is etched back to obtain the gate electrode 112, and at this time, the gate electrode 112 is located in the trench, and a metal electrode with uniform height is formed. Of course, the etching-back manner may be dry etching, or may be selected according to actual situations.
Compared with the prior art, the semiconductor device provided by the invention has the same beneficial effect as the planarization method in the technical scheme, and the detailed description is omitted here.
The embodiment of the invention also provides a manufacturing method of the semiconductor device. Since the semiconductor device can be various existing transistors. The method for manufacturing a semiconductor device according to an embodiment of the present invention is described below by taking a buried channel transistor as an example. The manufacturing method of the semiconductor device comprises the following steps:
as shown in fig. 3, a substrate 100 is provided. As for the selection of the substrate 100, reference is made to the foregoing description, which is not repeated herein. For example: when the semiconductor device to be manufactured is a buried channel transistor, the substrate 100 has a trench 102, and a first active region 114 and a second active region 116 around the trench 102. It should be understood that the positions and sizes of the trench 102 and the active region may be set according to the transistor type and the practical application scenario, and are not limited in detail herein. On this basis, a gate stack (not shown in fig. 3) is formed on the substrate 100, wherein the gate stack includes a gate dielectric layer (not shown in fig. 3) and a gate conductor layer (not shown in fig. 3). Illustratively, a barrier layer (not shown in fig. 3) and a gate electrode 112 are formed in trench 102, where the barrier layer and gate electrode 112 form a gate conductor layer.
As shown in fig. 4 to 7, for example, a gate dielectric layer is formed in the trench 102, and the gate dielectric layer covers the inner wall of the trench 102, and a barrier layer is formed on the surface of the gate dielectric layer. Then, a conductive material layer (not shown in fig. 7) is formed in the substrate 100 and the trench 102, and the planarization method provided by the embodiment of the invention is used to planarize the conductive material layer, so as to remove the protrusions generated by the grain boundaries, thereby making the planarized surface flat. After the conductive material layer is planarized, the planarized conductive material layer has a certain distance from the upper surface of the substrate 100, so that the substrate 100 is not damaged when the conductive material layer is planarized, and the structure formed in the substrate 100 is not damaged, thereby not affecting the performance of the subsequent memory device. Finally, the layer of conductive material is etched back to obtain the gate electrode 112 formed in the trench 102.
As shown in fig. 6, a planarization layer is formed on the substrate 100 using the above-described planarization method. As for the process of forming the planarization layer, reference is made to the above description, and the description is omitted here. The planarization layer covers the trench 102.
As shown in fig. 7, the planarization layer is processed to obtain a gate electrode 112 formed on the substrate 100. Illustratively, the planarization layer is etched back such that a gate electrode 112 of uniform height is formed within trench 102. For the way of etching back the planarization layer, reference is made to the above, and the description is omitted here.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention has the same beneficial effects as the planarization method in the technical scheme, and the details are not repeated here.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (11)

1. A planarization method, comprising:
providing a substrate;
forming a material layer on the substrate;
modifying the entire surface of the upper portion of the material layer such that the surface roughness of the entire surface of the upper portion of the material layer after modification is less than the surface roughness of the entire surface of the upper portion of the material layer before modification; the upper hardness of the material layer is less than the lower hardness of the material layer;
removing an upper portion of the material layer such that the material layer is planarized; the interface of the upper part of the material layer and the lower part of the material layer is parallel to the substrate; the upper portion thickness of the material layer is 10-1000A.
2. The planarization method of claim 1, wherein modifying the entire surface of the upper portion of the material layer such that the surface roughness of the entire surface of the upper portion of the material layer after modification is less than the surface roughness of the entire surface of the upper portion of the material layer before modification comprises:
and carrying out surface treatment on the whole surface of the upper part of the material layer to form an oxide material layer.
3. The planarization method of claim 2, wherein the surface treatment comprises rapid thermal oxidation.
4. The planarization method of claim 3, wherein the working gas for rapid thermal oxidation is oxygen or oxygen plasma, and the temperature is 300 ℃ to 1000 ℃ and the time is 10s to 3600s.
5. The planarization method of claim 1, wherein the material layer is a conductive material layer or a semiconductor material layer.
6. The planarization method of claim 1, wherein the material layer is a tungsten material layer.
7. The planarization method of claim 1, wherein the removing the upper portion of the material layer to planarize the material layer comprises:
and taking the lower part of the material layer as a stopping layer, and removing the upper part of the material layer to ensure that the material layer is flattened.
8. A semiconductor device, comprising: a substrate and a gate electrode, wherein the gate electrode adopts a planarization layer formed by the planarization method according to any one of claims 1 to 7.
9. The semiconductor device according to claim 8, wherein a trench is further formed in the substrate, and the planarization layer is located in the trench;
the substrate has two active regions located around the trench.
10. A method for manufacturing a semiconductor device, comprising:
providing a substrate;
forming a layer of conductive material on the substrate;
flattening the conductive material layer by adopting the flattening method according to any one of claims 1 to 7 to form a flattening layer on the substrate;
and processing the planarization layer to obtain a gate electrode formed on the substrate.
11. The method for manufacturing a semiconductor device according to claim 10, wherein the substrate has a trench, and two active regions located around the trench;
the conductive material layer covers the groove and the surface of the substrate;
processing the planarization layer to obtain a gate electrode formed on the substrate includes:
and back etching the planarization layer to form a gate electrode in the groove.
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