CN111554682B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN111554682B CN111554682B CN202010421401.XA CN202010421401A CN111554682B CN 111554682 B CN111554682 B CN 111554682B CN 202010421401 A CN202010421401 A CN 202010421401A CN 111554682 B CN111554682 B CN 111554682B
- Authority
- CN
- China
- Prior art keywords
- step surface
- film
- material layer
- low step
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to solve the problem that cracks are generated on the surface of a porous membrane material in the process of flattening a flattening material layer. The semiconductor device includes: a substrate having a stepped surface, the stepped surface including a high step face and a low step face; a material layer formed on the low step surface; the material layer is positioned on the low step surface and is provided with an inclined surface; and a planarization layer covering the low step surface, the material layer and the high step surface. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
In a manufacturing process of a Dynamic Random Access Memory (DRAM), a cell region (cell) has a capacitor, so that a higher level difference exists between the cell region and a core region (peripheral). For the subsequent patterning process, it is necessary to deposit an oxide on the cell region and the core region to form a planarization material layer, and to planarize the planarization material layer by using a Chemical Mechanical Polishing (CMP) process.
However, after the oxide is deposited in the cell region and the core region, a porous film is likely to be formed in the boundary region between the corresponding cell region and the core region due to the higher step difference between the cell region and the core region and the step coverage difference. On the basis, when the planarization material layer is planarized by adopting a chemical mechanical polishing process, cracks can be generated on the surface of the porous membrane due to the friction between the polishing pad and the porous membrane, and the performance of the memory device can be influenced when a subsequent manufacturing process is carried out.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for avoiding the problem that cracks are generated on the surface of a porous film material in the process of flattening a flattening material layer.
In order to achieve the above object, the present invention provides a semiconductor device. The semiconductor device includes:
a substrate having a stepped surface, the stepped surface including a high step face and a low step face;
a material layer formed on the low step surface; the material layer is positioned on the low step surface and is provided with an inclined surface;
and a planarization layer covering the low step surface, the material layer and the high step surface.
Compared with the prior art, the semiconductor device provided by the invention has the advantages that the substrate is provided with the step-shaped surface, and the step-shaped surface comprises the high step surface and the low step surface. A material layer is formed on the low step surface, and the material layer has a slope at the low step surface. When the flattening material layer is formed on the high-step surface, the material layer and the low-step surface, the junction of the high-step surface and the low-step surface is smoother than that of the prior art under the action of the inclined surface, the compactness of the flattening material layer is improved, and the porous membrane quality generated at the position of the flattening material layer is reduced. At this time, the planarization material layer is planarized, so that cracks can be prevented from being generated on the planarized surface. Therefore, the semiconductor device provided by the invention can avoid cracks after planarization treatment, and further improve the performance of the memory device.
The invention also provides a manufacturing method of the semiconductor device. The manufacturing method of the semiconductor device comprises the following steps:
providing a substrate, wherein the substrate is provided with a step-shaped surface, and the step-shaped surface comprises a high step surface and a low step surface;
forming a material layer on the low step surface; the material layer is positioned on the low step surface and is provided with an inclined surface;
and covering the low step surface, the material layer and the high step surface to form a planarization layer.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention has the same beneficial effects as those of the semiconductor device in the technical scheme, and the detailed description is omitted here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic view showing the formation of a porous film material at a folded portion due to a level difference in the prior art;
FIG. 2 is a schematic diagram illustrating the formation of cracks on a porous membranous surface through planarization in the prior art;
FIG. 3 is a schematic diagram of a semiconductor memory device according to an embodiment of the present invention;
fig. 4 to 8 are schematic diagrams illustrating a structure of a semiconductor memory device in various stages in the semiconductor memory device provided by the embodiment of the present invention.
Reference numerals:
a planarization material layer 100, a step surface 102, a high step surface 104, a low step surface 106, a porous film material 108, a material layer 110, a substrate 112, a dielectric layer 114, a planar portion 116, a bevel portion 118, a semiconductor material film 120, a barrier material film 122, a metal seed film 124, a metal film 126, a mask pattern 128, an undercut hole 130, and a planarization layer 132.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
A Dynamic Random Access Memory (DRAM) belongs to a volatile Memory, and includes a cell region and a core region that may be disposed around the cell region. Each cell region includes a transistor (transistor) electrically connected to a capacitor (capacitor), and the transistor controls the storage or release of charge in the capacitor for the purpose of storing data. Each cell region can be positioned and data access controlled by Word Lines (WL) and Bit Lines (BL) electrically connected to the cell regions across the memory region.
As a result of analyzing the semiconductor device, in the prior art, when manufacturing a DRAM, as shown in fig. 1, after a capacitor is formed in a cell region of the DRAM, a height difference h may exist between the cell region and a core region due to a high capacitor, and the height difference may be
Therefore, the folded portion a of the capacitor is formed at the boundary between the cell region and the core region. For the subsequent patterning process, it is necessary to deposit oxide on the cell region and the core region to form the planarization material layer 100. The planarization material layer 100 formed after depositing the oxide is also a stepped surface having a level difference due to the level difference h.
As shown in fig. 1, the stepped surface includes a high step surface 104 and a low step surface 106, and a folded portion A1 is also formed at an overlapping area of the high step surface 104 and the low step surface 106. However, since the planarization material layer 100 has a step coverage performance difference in the step difference region between the cell region and the core region, the membrane material at the fold A1 on the planarization material layer 100 becomes loose and porous, and this part is referred to as the porous membrane material 108 by the embodiment of the present invention.
The porous film material is a porous film material in a broad sense, and may be a film material having characteristics such as a slit, a crack, a microporous structure, a porous structure, and the like. The porous film of the above characteristics may be produced by any reason. For example: after planarization by a chemical mechanical polishing process, a film with crack characteristics is produced. Another example is: loose porous film quality due to step coverage difference.
As shown in fig. 1 and fig. 2, after the planarization material layer 100 is formed, the planarization material layer 100 needs to be subjected to chemical mechanical polishing to implement planarization treatment, but since the membrane material of the planarization material layer 100 is the porous membrane material 108, when the planarization material layer 100 is polished by a polishing pad in a polishing apparatus, cracks are formed on the surface of the porous membrane material 108 of the folded portion A1 due to friction, so that the performance of the manufactured memory device is poor. The cracks generated after the surface of the porous film material 108 is planarized generate irregular-shaped cracks on the surface of the porous film material 108 due to friction when the polishing pad polishes the porous film material 108 due to the loose structure of the porous film material 108.
In order to solve the above problems, embodiments of the present invention provide a semiconductor device and a method of manufacturing the same, by forming a material layer on a low step surface, and the material layer has a slope at the low step surface. When the flattening material layer is formed on the high-step surface, the material layer and the low-step surface, the junction of the high-step surface and the low-step surface is smoother than that of the prior art under the action of the inclined surface, the compactness of the flattening material layer is improved, and the porous membrane quality generated at the position of the flattening material layer is reduced. At this time, the planarization material layer is planarized, so that cracks can be prevented from being generated on the planarized surface. Therefore, the semiconductor device provided by the invention can avoid cracks after planarization treatment, and further improve the performance of the memory device.
For convenience of description, only the differences between the semiconductor device provided by the embodiment of the present invention and the semiconductor device in the prior art are described below, and other structures not described may refer to the description in the prior art. Of course, those skilled in the art can also make modifications to the existing semiconductor devices based on the following description of the embodiments of the present invention.
In view of the above problems, embodiments of the present invention provide a semiconductor device. As shown in fig. 3 and 6, the semiconductor device includes: substrate 112, material layer 110, and planarization layer 132.
As shown in fig. 7, the substrate 112 has a stepped surface 102, and the stepped surface 102 includes a high step surface 104 and a low step surface 106. The substrate 112 may be a substrate 112 on which no film layer is formed, such as a bulk silicon substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, a silicon germanium substrate, or an epitaxial thin film substrate formed by epitaxial growth, or may be a substrate on which a partial film layer is formed.
As shown in fig. 6 to 8, the material layer 110 is formed on the low step surface 106. The material layer 110 has a slope at the low step surface 106. The slope 118 covering the low step surface 106 may be
Or
But is not limited thereto. The planar portion 116 can prevent not only leakage current of the capacitor but also copper diffusion.
As shown in fig. 7 and 8, the material layer 110 is also formed on the high step surface 104. The material layer 110 includes a planar portion 116 formed on the high step surface 104 and a sloped portion 118 formed on the low step surface 106, in terms of area division. The slope portion 118 covers the low step surface 106 in the range of
It should be understood that the range in which the above-described slope portion 118 covers the low step surface 106 may vary depending on the kind of the memory device, and is not limited to a certain value, a certain range.
As shown in fig. 7, the right-angled folded portion A1 at the boundary between the high step surface 104 and the low step surface 106 is smoothed by the slope, and the step coverage property of the folded portion A1 is improved. When the denseness of the flattening material layer 100 at the folded portion A1 is relatively high, the generation of the porous film substance 108 at the flattening material layer 100 is reduced. By performing the planarization process on the planarization material layer 100, cracks can be prevented from being generated on the planarized surface.
As shown in fig. 7, the included angle α between the inclined surface and the low step surface 106 may be 60 ° to 89.9 °, for example, the included angle α between the inclined surface and the low step surface 106 may be 60 °, 74 °, or 89.9 °, it should be understood that the included angle α between the inclined surface and the low step surface 106, and the size of the inclined surface portion 118 covering the low step surface 106 may also be set according to actual circumstances.
As shown in FIG. 7, when the inclined surface and the low step surface 106 form an angle α of 60 °, the inclined surface portion 118 may cover the low step surface 106
In the meantime, under the cooperation of the inclined surface portion 118 and the low step surface 106, a gentle folded portion A1 can be further formed at the boundary between the high step surface 104 and the low step surface 106, so that the step coverage characteristic of the folded portion A1 is improved, and the area of the inclined surface portion 118 covering the low step surface 106 is small, so that the step coverage characteristic of the folded portion A1 is improved and the material is saved.
Illustratively, during the fabrication of a DRAM, if portions of the film layers (e.g., bottom electrode and dielectric layer 114) that form the capacitor have been formed on substrate 112, substrate 112 is divided into a cell region and a core region. When the capacitor is a stacked capacitor, the surface of the substrate 112 has a cell region corresponding to the high step surface 104 and a core region corresponding to the low step surface 106. Based on this, when the material of the material layer 110 is a conductive material, the material layer 110, the bottom electrode on the substrate 112, and the dielectric layer 114 can form a top electrode of the capacitor.
At this time, as shown in fig. 6 and 7, the above-described material layer 110 includes a semiconductor material film 120, a barrier material film 122, a metal seed film 124, and a metal film 126, which are sequentially stacked on the high step face 104 and the low step face 106. That is, a semiconductor material film 120 is formed on the high step surface 104 and the low step surface 106, a barrier material film 122 is formed on the semiconductor material film 120, a metal seed film 124 is formed on the barrier material film 122, and a metal film 126 is formed on the metal seed film 124. The material layer 110 covers the core region and the dielectric layer 114.
For example, as shown in fig. 6 and 7, the semiconductor material film 120 is a silicon germanium material film, the barrier material film 122 is a copper barrier material film, the metal seed film 124 is a copper seed film, and the metal film 126 may be an elemental metal material film or an alloy material film. When the metal film 126 is a simple substance metal material film, the metal film 126 is a metal film 126 having a low resistivity such as a copper material film, a silver material film, or a gold material film. The use of the low resistivity metal film 126 described above can facilitate capacitor signal conduction. And since the metal film 126 is a part of the material layer 110 and the material layer 110 has a slope, the metal film 126 can prevent the planarization layer 132 from cracking while ensuring the capacitor performance. It is to be understood that the materials of the semiconductor material film 120, the barrier material film 122, the metal seed film 124, and the metal film 126 described above may be selected according to practical circumstances, and are not limited thereto.
As shown in fig. 6 to 8, the planarization layer 132 covers the low step surface 106, the material layer 110 and the high step surface 104, and the height of the top surface of the planarization layer 132 is greater than the height of the top surface of the material layer 110. The planarization layer 132 may be an aluminum oxide planarization layer, a silicon dioxide planarization layer, or a silicon nitride planarization layer. It should be understood that the material of the planarization layer 132 may also be selected according to practical situations, and is not limited thereto.
For example: as shown in fig. 6 to 8, a planarization material layer 100 may be formed on the low step surface 106, the material layer 110, and the high step surface 104, and then the planarization material layer 100 may be subjected to a planarization process. The planarization material layer 100 may be formed in the same thickness in the cell region and the core region, or in different thicknesses. For example, the thickness of the planarization material layer 100 may be
The thickness of the planarization material layer 100 is greater than the step h.
In the related art, the thickness of the planarization material layer 100 is usually about 1.2 times of the height difference h, and more planarization material is required, and the planarization material layer 100 has a larger thickness, which requires more CMP cost. In the embodiment of the present invention, the thickness of the planarization material layer 100 is reduced
Not only saveSaves materials and reduces the planarization cost.
It should be noted that, if the thickness of the planarization material layer 100 forming the planarization layer 132 is smaller than the height difference h, the top electrode of the capacitor in the cell region is easily damaged when the planarization material layer 100 is planarized, so that the oxide in the cell region and the oxide in the core region cannot be planarized at the same time. Based on this, the embodiment of the invention provides the planarization layer 132 with a height of the top surface larger than that of the material layer 110, which facilitates the subsequent fabrication of the memory device. It is understood that the thickness of the planarization layer 132 may be selected according to the actual situation.
The embodiment of the invention also provides a manufacturing method of the semiconductor device. As shown in fig. 4 to 8, the method for manufacturing the semiconductor device includes:
step 1: as shown in fig. 4-8, a substrate 112 is provided. The substrate 112 has a stepped surface 102, and the stepped surface 102 includes a high step surface 104 and a low step surface 106. The substrate 112 may be a substrate 112 on which no film layer is formed, such as a bulk silicon substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, a silicon germanium substrate, or an epitaxial thin film substrate formed by epitaxial growth, or may be a substrate on which a partial film layer is formed.
Step 2: as shown in fig. 4 to 6, a material layer 110 is formed on the low step surface 106. The material layer 110 has a slope on the low step surface 106.
And step 3: as shown in fig. 7 and 8, the low step surface 106, the material layer 110, and the high step surface 104 are covered to each form the planarization layer 132.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the embodiment of the invention has the same beneficial effects as those of the semiconductor device provided by the embodiment, and details are not repeated herein.
Illustratively, during the fabrication of a DRAM, if portions of the film layers (e.g., bottom electrode and dielectric layer 114) that form the capacitor have been formed on substrate 112, substrate 112 is divided into a cell region and a core region. When the capacitor is a stacked capacitor, the surface of the substrate 112 has a cell region corresponding to the high step surface 104 and a core region corresponding to the low step surface 106. Based on this, when the material of the material layer 110 is a conductive material, the material layer 110, the bottom electrode on the substrate 112, and the dielectric layer 114 can form a top electrode of the capacitor.
As one possible implementation, as shown in fig. 6, in view of the use of the material layer 110 as a top electrode, the material layer 110 may include a semiconductor material film 120, a barrier material film 122, a metal seed film 124, and a metal film 126. Of course, in some cases, only the metal seed film 124 and the metal film 126 may be included. It is to be understood that the semiconductor material film 120, the barrier material film 122, the metal seed film 124, the metal film 126, and the like described above may be selected according to actual circumstances, and are not limited thereto.
Illustratively, as shown in fig. 6, when the material layer 110 includes the metal seed film 124 and the metal film 126, forming the material layer 110 on the low step surface 106 and forming the material layer 110 on the high step surface 104 includes:
step 101: a metal seed film 124 is formed on the high step level 104 and the low step level 106. The metal seed film 124 is a copper seed film.
Step 102: a mask pattern 128 is formed on the metal seed film 124 of the low step surface 106. The mask pattern 128 is formed in an undercut manner, and the formed mask pattern 128 is a trapezoid having a large top and a small bottom. Since the mask pattern 128 is not formed against the high step surface 104, an undercut hole 130 is provided between the mask pattern 128 and the high step surface 104. The included angle alpha between the inclined plane of the undercut hole 130 and the low step surface 106 is 60-89.9 deg. Undercut hole 130 is used to accommodate the material from which metal film 126 is formed. It should be understood that the angle α between the slope of the undercut hole 130 and the low step surface 106 may be set according to practical circumstances.
As one possible implementation, as shown in fig. 6, before forming the metal seed film 124 on the high step surface 104 and the low step surface 106, forming the material layer 110 on the low step surface 106, and forming the material layer 110 on the high step surface 104 further includes: a semiconductor material film 120 is formed on the high step face 104 and the low step face 106. The semiconductor material film 120 is made of silicon germanium. A barrier material film 122 is formed on the semiconductor material film 120. The barrier material film 122 is a copper barrier material film.
The above-described semiconductor material film 120, barrier material film 122, and metal seed film 124 may be formed by any of various deposition techniques. For example, it may be formed by low-pressure Chemical Vapor Deposition (LPCVD), atmospheric Pressure Chemical Vapor Deposition (APCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), and other suitable Deposition techniques. In the embodiments of the present invention, the formation is performed by chemical vapor deposition, but it is understood that the formation may be performed by other practical methods.
Step 103: as shown in fig. 5 and 6, a metal film 126 is formed on the metal seed film 124 not covered by the mask pattern 128.
Illustratively, the metal film 126 may be a film of elemental metal material. For example: a metal film 126 having a low resistivity such as a copper material film, a silver material film, or a gold material film is used. The use of the low resistivity metal film 126 described above can facilitate capacitor signal conduction. And since the metal film 126 is a part of the material layer 110 and the material layer 110 has a slope, the metal film 126 can prevent the planarization layer 132 from cracking while ensuring the capacitor performance. It should be understood that the material for forming the metal film 126 may be selected according to actual circumstances, and is not limited thereto. As for the manner of forming the metal film 126, reference is made to the above description, and the description thereof is omitted.
The material layer 110 includes a planar portion 116 formed on the high step surface 104, and a sloped portion 118 formed on the low step surface 106.
Step 104: as shown in fig. 5 and 6, the mask pattern 128 and the metal seed film 124 covered with the mask pattern 128 are removed. Illustratively, the removing method may be dry etching or wet etching, or a combination of dry etching and wet etching, and it is understood that the mask pattern 128 and the metal seed film 124 covered by the mask pattern 128 may also be etched in other practical manners to obtain the final material layer 110.
As shown in fig. 5 and 6, the material layer 110 covers the core region and the dielectric layer 114. The material layer 110 is located on the low step surface 106 and has an inclined surface, and an included angle alpha between the inclined surface and the low step surface 106 is 60-89.9 degrees. Under the action of the inclined surface, the junction of the high step surface 104 and the low step surface 106 is more gentle than that of the prior art, and the step coverage characteristic of the folded portion A1 is improved. When the denseness of the flattening material layer 100 at the folded portion A1 is relatively high, the generation of the porous film substance 108 at the flattening material layer 100 is reduced. By performing the planarization process on the planarization material layer 100, cracks can be prevented from being generated on the planarized surface.
For example, the angle α between the inclined surface and the low step surface 106 may be 60 °. When the included angle α between the inclined surface and the low step surface 106 is 60 °, the inclined surface portion 118 covering the low step surface 106 may be
In the meantime, under the cooperation of the inclined surface portion 118 and the low step surface 106, a gentle folded portion A1 can be further formed at the boundary between the high step surface 104 and the low step surface 106, so that the step coverage characteristic of the folded portion A1 is improved, and the area of the inclined surface portion 118 covering the low step surface 106 is small, so that the step coverage characteristic of the folded portion A1 is improved and the material is saved. It should be understood that the included angle α between the inclined surface and the low step surface 106 can be set according to actual conditions.
As one possible implementation, as shown in fig. 7, forming the planarization layer 132 on each of the low step surface 106, the material layer 110, and the high step surface 104 includes:
as shown in fig. 6 and 7, a planarizing material layer 100 is formed on the low step surface 106, the material layer 110, and the high step surface 104. Of course, the planarization material layer 100 may be silicon oxide. The planarization material layer 100 is silicon oxide formed from a silicon source and an oxygen source. For example: the silicon source can be Tetraethoxysilane (TEOS) or SiH 4 One or two of them. The oxygen source may be O 3 、O 2 In (1)One or two. The thickness of the planarization material layer 100 may be
At this time, the thickness of the planarization material layer 100 is greater than the height difference h, and it should be understood that the thickness of the planarization material layer 100 can be set according to practical situations.
As shown in fig. 6 to 8, the planarization material layer 100 is subjected to a planarization process to obtain a planarization layer 132.
The top surface of the planarization layer 132 is higher than the top surface of the material layer 110, which facilitates the subsequent fabrication of the memory device. It should be understood that the thickness of the planarization layer 132 may be selected according to practical situations and is not particularly limited herein.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (20)
1. A semiconductor device, comprising:
a substrate having a stepped surface comprising a high step face and a low step face;
a material layer formed on the low step surface; the material layer is positioned on the low step surface and is provided with an inclined surface; the material layer comprises a metal seed crystal film and a metal film formed on the metal seed crystal film;
and a planarization layer covering the low step surface, the material layer, and the high step surface.
2. The semiconductor device according to claim 1, wherein the material layer is further formed on a high step surface;
the material layer comprises a plane part formed on the high step surface;
and a slope part formed on the low step surface.
3. The semiconductor device according to claim 2, wherein the slope portion covers the low step face in an area of
4. The semiconductor device of claim 1, wherein the slope includes an angle of 60 ° to 89.9 ° with the low step surface.
5. The semiconductor device of claim 2, wherein the material layer comprises:
a metal seed film formed on the high step surface and the low step surface;
and a metal film formed on the metal seed film.
6. The semiconductor device according to claim 5, wherein the metal film comprises a film of an elemental metal material or a film of an alloy material.
7. The semiconductor device according to claim 6, wherein the elemental metal material film comprises a copper material film, a silver material film, or a gold material film.
8. The semiconductor device according to claim 5, further comprising: a semiconductor material film and a barrier material film are further formed on the high step surface and the low step surface; the barrier material film is formed on the semiconductor material film; the metal seed film is formed on the barrier material film.
9. The semiconductor device according to any one of claims 1 to 8, wherein the planarization layer is an aluminum oxide planarization layer, a silicon dioxide planarization layer, or a silicon nitride planarization layer.
10. The semiconductor device according to any one of claims 1 to 8, wherein the substrate has a cell region and a core region; the high step surface is positioned in the unit area, and the low step surface is positioned in the core area;
the substrate comprises a dielectric layer and a bottom electrode which are positioned in the unit area; the material layer covers the core region and the dielectric layer.
11. A method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a step-shaped surface, and the step-shaped surface comprises a high step surface and a low step surface;
forming a material layer on the low step surface; the material layer is positioned on the low step surface and is provided with an inclined surface; the material layer comprises a metal seed crystal film and a metal film formed on the metal seed crystal film;
covering the low step surface, the material layer, and the high step surface to each form a planarization layer.
12. The method of manufacturing a semiconductor device according to claim 11, wherein an angle between the slope and the low step surface is 60 ° to 89.9 °.
13. The method of claim 11, wherein after providing a substrate, the method further comprises forming a material layer on the low step surface, and wherein the method further comprises:
forming a material layer on the high step surface;
the material layer comprises a plane part formed on the high step surface;
and a slope part formed on the low step surface.
14. The method of manufacturing a semiconductor device according to claim 13, wherein the forming of the material layer on the low step surface and the forming of the material layer on the high step surface comprise:
forming metal seed crystal films on the high step surface and the low step surface;
forming a mask pattern on the metal seed film of the low step surface; the mask pattern has an undercut hole in contact with the high step surface;
forming a metal film on the metal seed film not covered by the mask pattern;
and removing the mask pattern and the metal seed crystal film covered by the mask pattern.
15. The method for manufacturing a semiconductor device according to claim 14, wherein an included angle between the inclined surface of the undercut hole and the low step surface is 60 ° to 89.9 °; the undercut hole is for receiving a material forming the metal film.
16. The method of claim 14, wherein the forming a material layer on the low step surface before forming the metal seed film on the high step surface and the low step surface further comprises:
forming a semiconductor material film on the high step surface and the low step surface;
a barrier material film is formed on the semiconductor material film.
17. The method for manufacturing a semiconductor device according to claim 14, wherein the removing comprises: dry etching and/or wet etching.
18. The method of claim 11, wherein the covering the low step surface, the material layer, and the high step surface to each form a planarization layer comprises:
forming a planarization material layer on the low step surface, the material layer and the high step surface;
and processing the planarization material layer to obtain a planarization layer.
19. The method of claim 18, wherein the planarization material layer has a thickness of
The planarization material layer is formed from a silicon source and an oxygen source.
20. The method for manufacturing a semiconductor device according to any one of claims 11 to 19, wherein the substrate has a cell region and a core region; the high step surface is positioned in the unit area, and the low step surface is positioned in the core area;
the substrate comprises a dielectric layer and a bottom electrode positioned in the unit area; the material layer covers the core region and the dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010421401.XA CN111554682B (en) | 2020-05-18 | 2020-05-18 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010421401.XA CN111554682B (en) | 2020-05-18 | 2020-05-18 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111554682A CN111554682A (en) | 2020-08-18 |
| CN111554682B true CN111554682B (en) | 2023-03-21 |
Family
ID=72001959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010421401.XA Active CN111554682B (en) | 2020-05-18 | 2020-05-18 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111554682B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990026074A (en) * | 1997-09-22 | 1999-04-15 | 윤종용 | Planarization method of semiconductor device |
| CN103081103A (en) * | 2010-09-01 | 2013-05-01 | 甲骨文国际公司 | Manufacturing fixture for a ramp-stack chip package |
| CN104793802A (en) * | 2015-05-08 | 2015-07-22 | 厦门天马微电子有限公司 | Array substrate and manufacturing method, display panel and display device thereof |
| CN108376646A (en) * | 2017-12-14 | 2018-08-07 | 上海集成电路研发中心有限公司 | A kind of graphic method of step in semiconductor devices processing procedure |
| CN109920791A (en) * | 2019-03-15 | 2019-06-21 | 长江存储科技有限责任公司 | A kind of 3D nand memory part and its manufacturing method |
-
2020
- 2020-05-18 CN CN202010421401.XA patent/CN111554682B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990026074A (en) * | 1997-09-22 | 1999-04-15 | 윤종용 | Planarization method of semiconductor device |
| CN103081103A (en) * | 2010-09-01 | 2013-05-01 | 甲骨文国际公司 | Manufacturing fixture for a ramp-stack chip package |
| CN104793802A (en) * | 2015-05-08 | 2015-07-22 | 厦门天马微电子有限公司 | Array substrate and manufacturing method, display panel and display device thereof |
| CN108376646A (en) * | 2017-12-14 | 2018-08-07 | 上海集成电路研发中心有限公司 | A kind of graphic method of step in semiconductor devices processing procedure |
| CN109920791A (en) * | 2019-03-15 | 2019-06-21 | 长江存储科技有限责任公司 | A kind of 3D nand memory part and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111554682A (en) | 2020-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6165864A (en) | Tapered electrode for stacked capacitors | |
| US6174769B1 (en) | Method for manufacturing stacked capacitor | |
| US9478548B2 (en) | Semiconductor devices and methods of manufacturing semiconductor devices | |
| US6562679B2 (en) | Method for forming a storage node of a capacitor | |
| JPH08316430A (en) | Semiconductor storage device, its manufacture, and stacked capacitor | |
| JPH06232367A (en) | Dram based on silicon on insulator and manufacture thereof | |
| CN110061001B (en) | Semiconductor element and manufacturing method thereof | |
| US5066608A (en) | Method of making a DRAM cell with stacked trench capacitor | |
| JP3605493B2 (en) | Method for manufacturing semiconductor device | |
| CN111554682B (en) | Semiconductor device and manufacturing method thereof | |
| US7030442B2 (en) | Stack-film trench capacitor and method for manufacturing the same | |
| JPH10189895A (en) | Manufacture of semiconductor device | |
| US7553723B2 (en) | Manufacturing method of a memory device | |
| CN215600375U (en) | Semiconductor structure and semiconductor device | |
| US6964898B1 (en) | Method for fabricating deep trench capacitor | |
| CN211088261U (en) | Semiconductor structure | |
| CN113972208A (en) | Semiconductor device, manufacturing method thereof and electronic equipment | |
| JP2004134692A (en) | Semiconductor memory device and manufacturing method thereof | |
| US20060154435A1 (en) | Method of fabricating trench isolation for trench-capacitor dram devices | |
| TW201711169A (en) | Cell contact structure | |
| CN111554574B (en) | Planarization method, semiconductor device and manufacturing method thereof | |
| CN111554576B (en) | Planarization method | |
| CN113437134B (en) | Semiconductor structure, semiconductor structure preparation method and semiconductor device | |
| TW527718B (en) | Fabrication method of isolation air gap between bit line and capacitor | |
| TWI225688B (en) | Memory device with vertical transistors and deep trench capacitors and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |