CN113540027B - Bit line structure, manufacturing method thereof, semiconductor memory and electronic equipment - Google Patents
Bit line structure, manufacturing method thereof, semiconductor memory and electronic equipment Download PDFInfo
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- CN113540027B CN113540027B CN202010292274.8A CN202010292274A CN113540027B CN 113540027 B CN113540027 B CN 113540027B CN 202010292274 A CN202010292274 A CN 202010292274A CN 113540027 B CN113540027 B CN 113540027B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims 2
- 238000001259 photo etching Methods 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 229920005591 polysilicon Polymers 0.000 abstract description 10
- 150000004767 nitrides Chemical class 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000001459 lithography Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The present disclosure provides a bit line structure, a method of fabricating the same, a semiconductor memory, and an electronic device. The bit line structure of the present disclosure includes a semiconductor substrate; at least one bit line on the semiconductor substrate; the semiconductor substrate comprises at least one active region defined by a device isolation layer, the bit line is in contact with the active region, and the bit line comprises a metal layer and an insulating layer which are sequentially overlapped from the semiconductor substrate. The bit line structure overcomes the limitation of bit line structures at less than 7nm by changing the bit line from a polysilicon-barrier metal-tungsten structure to a metal structure. And after removal of the polysilicon, further stacking is possible.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a bit line structure, a manufacturing method thereof, a semiconductor memory and electronic equipment.
Background
Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory that generally includes an array of bit cells, each cell capable of storing a bit of information. A typical cell configuration consists of a capacitor for storing charge (i.e., bits of information) and an access transistor that provides an access signal to the capacitor during read and write operations. The access transistor is connected between the bit line and the capacitor and is gated (turned on or off) by the word line signal. During a read operation, bits of stored information are read from the cells via the associated bit lines. During a write operation, bits of information are stored in the cell from the bit line via the transistor. The cells are dynamic in nature (due to leakage) and must therefore be periodically refreshed.
The bit line structure of DRAM using buried gate structure is below sub-16 nm, and the current bit line structure is polysilicon-barrier metal-tungsten structure, and great difficulty is encountered in sub-16 nm process due to the limitations of tilt margin and aspect ratio. In addition, polysilicon bit line structures have limitations in that physical property changes occur when the critical dimension is less than 7 nm.
Disclosure of Invention
An object of the present disclosure is to provide a bit line structure, a method of manufacturing the same, a semiconductor memory, and an electronic device.
A first aspect of the present disclosure provides a bit line structure comprising:
a semiconductor substrate;
at least one bit line on the semiconductor substrate;
the semiconductor substrate comprises at least one active region defined by a device isolation layer, the bit line is in contact with the active region, and the bit line comprises a metal layer and an insulating layer which are sequentially overlapped from the semiconductor substrate.
A second aspect of the present disclosure provides a method for fabricating a bit line structure, including:
providing a semiconductor substrate; the semiconductor substrate includes at least one active region defined by a device isolation layer;
forming at least one bit line contact trench on the device isolation layer, the bit line contact trench exposing the active region;
and forming a metal layer and an insulating layer in the bit line contact groove, wherein the metal layer and the insulating layer are sequentially overlapped from the bit line contact groove, and the metal layer and the insulating layer form a bit line.
A third aspect of the present disclosure provides a semiconductor memory, comprising:
the bit line structure as described in the first aspect.
A fourth aspect of the present disclosure provides an electronic device, comprising:
the semiconductor memory as described in the third aspect.
Compared with the prior art, the utility model has the advantages that:
(1) The bit line is changed from a polysilicon-barrier metal-tungsten structure to a metal structure, and the limitation of the polysilicon bit line structure at less than 7nm can be overcome.
(2) After the polysilicon is removed, further stacking may be performed.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIGS. 1-7 are schematic diagrams illustrating various stages of implementation of fabricating a bit line structure provided by the present disclosure;
fig. 8 shows a schematic diagram of a bit line structure provided by the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
Existing bit line structures encounter significant difficulties in sub-16 nm processes.
In order to solve the above-mentioned problems in the prior art, embodiments of the present disclosure provide a bit line structure, a method for manufacturing the same, a semiconductor memory, and an electronic device, which are described below with reference to the accompanying drawings.
Referring to fig. 8, fig. 8 is a schematic cross-sectional view of a bit line structure according to the present disclosure.
As shown, the bit line structure includes: the semiconductor substrate 100, at least one bit line 200 on the semiconductor substrate 100. The bit line 200 includes a metal layer 210 and an insulating layer 220 stacked in this order from the semiconductor substrate 100.
It is appreciated that the bit line structure of the present disclosure changes the usual poly-barrier metal-tungsten structure to a metal structure so that the limitations of the poly bit line structure at less than 7nm can be overcome.
With continued reference to fig. 8, in accordance with one embodiment of the present invention, the metal layer 210 may include a wire metal layer 211 and a barrier metal layer 222 surrounding the bottom and sides of the wire metal layer 211.
According to an embodiment of the present invention, the material of the conductive metal layer 211 may be tungsten or cobalt; the barrier metal layer 222 may be made of metal or metal nitride, such as titanium, tantalum, titanium nitride, and tantalum nitride. The materials for producing the above layers may be selected according to actual conditions, and the present disclosure is not limited thereto.
According to an embodiment of the present invention, the insulating layer 220 may be provided as a nitride layer, and the material of the nitride layer may be silicon nitride, or may be other nitrides, which is not limited in this disclosure.
With continued reference to fig. 8, in accordance with one embodiment of the present invention, the semiconductor substrate 100 includes at least one active region 120 defined by the device isolation layer 110.
At least one bit line contact trench 130 is formed on the device isolation layer 100, the bit line contact trench 130 exposes the active region 120, a bit line 200 is formed in the bit line contact trench 130, and the bit line 200 is in contact with the active region 120.
Compared with the prior bit line structure, the bit line structure provided by the present disclosure can overcome the limitation of the bit line structure when the bit line structure is smaller than 7nm by changing the common polysilicon-blocking metal-tungsten structure into a metal structure. And after removal of the polysilicon, further stacking is possible.
The embodiment of the disclosure also provides a manufacturing method of the bit line structure, which is used for manufacturing the bit line structure in the embodiment; the manufacturing method is implemented as follows with reference to fig. 1 to 8:
referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including at least one active region 120 defined by a device isolation layer 110.
At least one bit line contact trench 130 is then etched on the device isolation layer 110, the bit line contact trench 130 exposing the active region 120.
Referring to fig. 2, an oxide layer 140, which may be an oxide such as silicon oxide, is deposited in the bit line contact trench 130. After the deposition is completed, the deposited oxide layer 140 is raised above the surface of the device isolation layer 110 by a certain height, for example, about 1000 angstroms (a).
Referring to fig. 3, after depositing the oxide layer 140, bit line contact holes and bit line trenches are etched in the oxide layer 140 where bit lines pass through by a damascene process. In the etching, a dual damascene process may be used, the pattern of the bit line contact hole is etched using a photoresist pattern, and then the pattern of the bit line trench is etched using a second photoresist pattern. The bit line contact hole plus bit line trench pattern a is shown in fig. 3. Specifically, the first lithography mask is used to etch the polysilicon and the nitride layer to form the bit line contact hole, and the second lithography mask is used to etch the polysilicon and the nitride layer to form the bit line trench.
Referring to fig. 4, in the pattern a, a wire metal layer 211 and a barrier metal layer 212 wrapping the bottom and side surfaces of the wire metal layer 211 are sequentially formed. The conductive line metal layer 211 and the barrier metal layer 212 constitute a metal layer 210. Specifically, the material for forming the conductive metal layer 211 may be tungsten; the barrier metal layer 222 may be made of titanium or titanium nitride. The materials for producing the above layers may be selected according to actual conditions, and the present disclosure is not limited thereto.
Referring to fig. 5, the metal layer 210 in the bit line trench is etched back to a depth that may be, for example, about 1000 angstroms above the surface of the device isolation layer 110 by the oxide layer 140. The grooves formed after the back etching are shown as B in the figure.
Referring to fig. 6, an insulating layer 220 is deposited on the etched back metal layer 210, such that the insulating layer 220 fills the recess B, and during the deposition process, excess insulating layer material is deposited outside the recess B, forming the structure shown in fig. 6. Specifically, the insulating layer 220 may be provided as a nitride layer, and the material of the nitride layer may be silicon nitride, or may be other nitrides, which is not limited in this disclosure.
Referring to fig. 7, excess insulating layer material deposited outside of the recess B is removed, forming the structure shown in fig. 7, after which planarization may be performed by Chemical Mechanical Polishing (CMP).
Referring to fig. 8, on the basis of fig. 7, the oxide layer 140 may be removed by a wet etching process and a plasma etching process to manufacture a silicon nitride layer for a storage node contact on top of tungsten to stack the storage layers, thereby further forming a semiconductor memory.
The bit line structure manufactured by the method changes the bit line from a polysilicon-blocking metal-tungsten structure to a metal structure, so that the limitation of the bit line structure when the bit line structure is smaller than 7nm can be overcome. And after removal of the polysilicon, further stacking is possible.
The embodiment of the disclosure also provides a semiconductor memory including the bit line structure in the above embodiment. The semiconductor memory may be, for example, a DRAM.
Referring to fig. 8, the bit line structure includes: the semiconductor substrate 100, at least one bit line 200 on the semiconductor substrate 100. The bit line 200 includes a metal layer 210 and an insulating layer 220 stacked in this order from the semiconductor substrate 100.
It is appreciated that the bit line structure of the present disclosure changes the usual poly-barrier metal-tungsten structure to a metal structure so that the limitations of the poly bit line structure at less than 7nm can be overcome.
With continued reference to fig. 8, in accordance with one embodiment of the present invention, the metal layer 210 may include a wire metal layer 211 and a barrier metal layer 222 surrounding the bottom and sides of the wire metal layer 211.
According to an embodiment of the present invention, the material of the conductive metal layer 211 may be tungsten; the barrier metal layer 222 may be made of titanium or titanium nitride. The materials for producing the above layers may be selected according to actual conditions, and the present disclosure is not limited thereto.
According to an embodiment of the present invention, the insulating layer 220 may be provided as a nitride layer, and the material of the nitride layer may be silicon nitride, or may be other nitrides, which is not limited in this disclosure.
With continued reference to fig. 8, in accordance with one embodiment of the present invention, the semiconductor substrate 100 includes at least one active region 120 defined by the device isolation layer 110.
At least one bit line contact trench 130 is formed on the device isolation layer 100, the bit line contact trench 130 exposes the active region 120, a bit line 200 is formed in the bit line contact trench 130, and the bit line 200 is in contact with the active region 120.
The present disclosure provides a semiconductor memory whose bit line structure may overcome the limitations of bit line structures at less than 7nm by changing the bit line from a tungsten-barrier metal-polysilicon structure to a metal structure. And after removal of the polysilicon, further stacking is possible.
The embodiment of the disclosure also provides an electronic device, which comprises the semiconductor memory in the embodiment. The electronic device comprises a smart phone, a computer, a tablet personal computer, a wearable intelligent device, an artificial intelligent device, a mobile power supply and the like.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (4)
1. A method for fabricating a bit line structure, comprising:
providing a semiconductor substrate; the semiconductor substrate includes at least one active region defined by a device isolation layer;
forming at least one bit line contact trench on the device isolation layer, the bit line contact trench exposing the active region;
forming a metal layer and an insulating layer in the bit line contact groove, wherein the metal layer and the insulating layer are sequentially overlapped from the bit line contact groove, and the metal layer and the insulating layer form a bit line;
the metal layer comprises a wire metal layer and a blocking metal layer wrapping the bottom surface and the side surface of the wire metal layer;
the metal layer and the insulating layer which are sequentially overlapped from the bit line contact groove are formed in the bit line contact groove, and the metal layer and the insulating layer comprise:
depositing an oxide layer in the bit line contact groove, wherein the oxide layer is higher than the surface of the device isolation layer by a preset height;
etching a bit line contact hole and a bit line groove in the oxide layer through a Damascus process;
and forming a wire metal layer and a blocking metal layer wrapping the bottom surface and the side surface of the wire metal layer in the bit line groove in sequence.
2. The method of manufacturing of claim 1, further comprising:
carrying out back etching on the metal layer in the bit line groove;
forming an insulating layer on the etched metal layer;
and removing the oxide layer.
3. The method of claim 2, wherein the depth of the etch back of the metal layer is the predetermined height.
4. The method of claim 1, wherein etching a bitline contact hole and a bitline trench in the oxide layer by a damascene process comprises:
etching the oxide layer by using a first photoetching mask to form a bit line contact hole;
and etching the oxide layer by using a second photoetching mask to form a bit line groove.
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Citations (2)
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CN101872745A (en) * | 2009-04-24 | 2010-10-27 | 海力士半导体有限公司 | Semiconductor memory device and method for manufacturing the same |
CN101882617A (en) * | 2010-06-12 | 2010-11-10 | 中国科学院上海微系统与信息技术研究所 | Schottky diode, semiconductor memory and manufacturing technology thereof |
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KR100599050B1 (en) * | 2004-04-02 | 2006-07-12 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
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CN101872745A (en) * | 2009-04-24 | 2010-10-27 | 海力士半导体有限公司 | Semiconductor memory device and method for manufacturing the same |
CN101882617A (en) * | 2010-06-12 | 2010-11-10 | 中国科学院上海微系统与信息技术研究所 | Schottky diode, semiconductor memory and manufacturing technology thereof |
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