CN113540027A - Bit line structure, manufacturing method thereof, semiconductor memory and electronic equipment - Google Patents

Bit line structure, manufacturing method thereof, semiconductor memory and electronic equipment Download PDF

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Publication number
CN113540027A
CN113540027A CN202010292274.8A CN202010292274A CN113540027A CN 113540027 A CN113540027 A CN 113540027A CN 202010292274 A CN202010292274 A CN 202010292274A CN 113540027 A CN113540027 A CN 113540027A
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China
Prior art keywords
bit line
metal layer
layer
line contact
semiconductor substrate
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CN202010292274.8A
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Chinese (zh)
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CN113540027B (en
Inventor
金镇泳
李俊杰
周娜
杨涛
李俊峰
王文武
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Publication of CN113540027A publication Critical patent/CN113540027A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

Abstract

The disclosure provides a bit line structure, a manufacturing method thereof, a semiconductor memory and an electronic device. The bit line structure of the present disclosure includes a semiconductor substrate; at least one bit line on the semiconductor substrate; the semiconductor substrate comprises at least one active region defined by a device isolation layer, the bit line is in contact with the active region, and the bit line comprises a metal layer and an insulating layer which are sequentially overlapped from the semiconductor substrate. The bit line structure changes the bit line from a polysilicon-barrier metal-tungsten structure to a metal structure, so that the limitation of the bit line structure when the bit line structure is less than 7nm can be overcome. And after removing the polysilicon, further stacking may be performed.

Description

Bit line structure, manufacturing method thereof, semiconductor memory and electronic equipment
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a bit line structure, a method for manufacturing the same, a semiconductor memory, and an electronic device.
Background
Dynamic Random Access Memory (DRAM) is a type of semiconductor Memory that typically includes an array of bit cells, each cell capable of storing a bit of information. A typical cell configuration consists of a capacitor for storing charge (i.e., a bit of information) and an access transistor that provides an access signal to the capacitor during read and write operations. The access transistor is connected between the bit line and the capacitor, and is gated (turned on or off) by a word line signal. During a read operation, a bit of stored information is read from the cell via the associated bit line. During a write operation, a bit of information is stored in the cell from the bit line via the transistor. The cells are dynamic in nature (due to leakage) and therefore must be refreshed periodically.
The bit line structure of the DRAM using the buried gate structure is sub-16 nm or less, and the current bit line structure is a polysilicon-barrier metal-tungsten structure, which may encounter great difficulty in sub-16 nm or less process due to the limitation of tilt margin and aspect ratio. In addition, the polysilicon bit line structure has a limitation in that physical properties thereof change when the critical dimension is less than 7 nm.
Disclosure of Invention
The present disclosure provides a bit line structure and a method for fabricating the same, a semiconductor memory and an electronic device.
A first aspect of the present disclosure provides a bit line structure, including:
a semiconductor substrate;
at least one bit line on the semiconductor substrate;
the semiconductor substrate comprises at least one active region defined by a device isolation layer, the bit line is in contact with the active region, and the bit line comprises a metal layer and an insulating layer which are sequentially overlapped from the semiconductor substrate.
A second aspect of the present disclosure provides a method for manufacturing a bit line structure, including:
providing a semiconductor substrate; the semiconductor substrate comprises at least one active region defined by a device isolation layer;
forming at least one bit line contact trench on the device isolation layer, the bit line contact trench exposing the active region;
and forming a metal layer and an insulating layer which are sequentially overlapped from the bit line contact groove in the bit line contact groove, wherein the metal layer and the insulating layer form a bit line.
A third aspect of the present disclosure provides a semiconductor memory comprising:
the bit line structure as described in the first aspect.
A fourth aspect of the present disclosure provides an electronic device, comprising:
the semiconductor memory as described in the third aspect.
This disclosure compares advantage with prior art and lies in:
(1) the bit line is changed from a polysilicon-barrier metal-tungsten structure to a metal structure, and the limitation of the polysilicon bit line structure when the bit line structure is less than 7nm can be overcome.
(2) After the polysilicon is removed, further stacking may be performed.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIGS. 1-7 illustrate schematic diagrams of various stages of fabrication of a bitline structure provided by the present disclosure;
FIG. 8 illustrates a schematic diagram of one bit line architecture provided by the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
The conventional bit line structure has great difficulty in sub-16 nm processing.
In order to solve the above-mentioned problems in the prior art, embodiments of the present disclosure provide a bit line structure and a method for manufacturing the same, a semiconductor memory and an electronic device, which are described below with reference to the accompanying drawings.
Referring first to fig. 8, fig. 8 is a schematic cross-sectional view illustrating a bit line structure according to the present disclosure.
As shown, the bit line structure includes: the semiconductor device includes a semiconductor substrate 100, and at least one bit line 200 on the semiconductor substrate 100. The bit line 200 includes a metal layer 210 and an insulating layer 220 stacked in sequence from the semiconductor substrate 100.
It is understood that the bitline structure of the present disclosure changes the general polysilicon-barrier metal-tungsten structure to a metal structure so that the limitation of the polysilicon bitline structure at less than 7nm can be overcome.
With continued reference to fig. 8, the metal layer 210 may include a conductive line metal layer 211 and a barrier metal layer 222 wrapping the bottom and side surfaces of the conductive line metal layer 211, according to a specific embodiment of the present invention.
According to an embodiment of the present invention, the material of the conductive line metal layer 211 may be tungsten or cobalt; the material of the barrier metal layer 222 may be metal or metal nitride, such as titanium, tantalum, titanium nitride, or tantalum nitride. The material for making the above layers may also be selected according to the actual situation, and the disclosure is not limited thereto.
According to an embodiment of the present invention, the insulating layer 220 may be a nitride layer, and the nitride layer may be made of silicon nitride or other nitride, which is not limited in the present disclosure.
With continued reference to fig. 8, in accordance with a specific embodiment of the present invention, the semiconductor substrate 100 includes at least one active region 120 defined by a device isolation layer 110.
At least one bit line contact trench 130 is formed on the device isolation layer 100, the bit line contact trench 130 exposes the active region 120, the bit line 200 is formed in the bit line contact trench 130, and the bit line 200 contacts the active region 120.
Compared with the existing bit line structure, the bit line structure provided by the disclosure changes the common polysilicon-barrier metal-tungsten structure into a metal structure, so that the limitation of the bit line structure in the time of being less than 7nm can be overcome. And after removing the polysilicon, further stacking may be performed.
The embodiment of the disclosure also provides a manufacturing method of the bit line structure, which is used for preparing the bit line structure in the above embodiment; the manufacturing method is implemented as follows with reference to fig. 1 to 8:
referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including at least one active region 120 defined by a device isolation layer 110.
At least one bit line contact trench 130 is then etched and formed on the device isolation layer 110, and the bit line contact trench 130 exposes the active region 120.
Referring to fig. 2, an oxide layer 140, which may be an oxide such as silicon oxide, is deposited in the bit line contact trench 130. After deposition, the deposited oxide layer 140 is a certain height, for example, about 1000 angstroms (a), above the surface of the device isolation layer 110.
Referring to fig. 3, after depositing the oxide layer 140, a bit line contact hole and a bit line trench are etched in the oxide layer 140 where a bit line passes through by using a damascene process. In the etching process, a dual damascene process can be adopted, a photoresist pattern is adopted to etch the pattern of the bit line contact hole, and then a second photoresist pattern is adopted to etch the pattern of the bit line groove. Shown in fig. 3 is a bit line contact hole plus bit line trench pattern a. Specifically, the polysilicon and the nitride layer may be etched by using a first photolithography mask to form a bit line contact hole, and then the polysilicon and the nitride layer may be etched by using a second photolithography mask to form a bit line trench.
Referring to fig. 4, in the pattern a, a conductive line metal layer 211 and a barrier metal layer 212 wrapping the bottom and side surfaces of the conductive line metal layer 211 are sequentially formed. The wire metal layer 211 and the barrier metal layer 212 constitute a metal layer 210. Specifically, the material of the conductive wire metal layer 211 may be tungsten; the barrier metal layer 222 may be made of titanium or titanium nitride. The material for making the above layers may also be selected according to the actual situation, and the disclosure is not limited thereto.
Referring to fig. 5, the metal layer 210 in the bit line trench is etched back to a depth that is about 1000 angstroms, for example, the height of the oxide layer 140 above the surface of the device isolation layer 110. The groove formed after the etch back is shown as B.
Referring to fig. 6, an insulating layer 220 is deposited on the etched-back metal layer 210, such that the insulating layer 220 fills the groove B, and during the deposition process, an excess insulating layer material is deposited outside the groove B, thereby forming the structure shown in fig. 6. Specifically, the insulating layer 220 may be a nitride layer, and the material of the nitride layer may be silicon nitride, or may be other nitrides, which is not limited in this disclosure.
Referring to fig. 7, excess insulating layer material deposited outside the recess B is removed to form the structure shown in fig. 7, and then planarization may be performed by Chemical Mechanical Polishing (CMP).
Referring to fig. 8, on the basis of fig. 7, the oxide layer 140 may be removed through a wet etching process and a plasma etching process to manufacture a silicon nitride layer for a storage node contact on the upper portion of tungsten to stack a storage layer, thereby further forming a semiconductor memory.
The bit line structure manufactured by the method changes the bit line from the polysilicon-barrier metal-tungsten structure into the metal structure, so that the limitation of the bit line structure when the bit line structure is less than 7nm can be overcome. And after removing the polysilicon, further stacking may be performed.
The embodiment of the present disclosure also provides a semiconductor memory, which includes the bit line structure in the above embodiments. The semiconductor memory may be, for example, a DRAM.
Referring to fig. 8, the bit line structure includes: the semiconductor device includes a semiconductor substrate 100, and at least one bit line 200 on the semiconductor substrate 100. The bit line 200 includes a metal layer 210 and an insulating layer 220 stacked in sequence from the semiconductor substrate 100.
It is understood that the bitline structure of the present disclosure changes the general polysilicon-barrier metal-tungsten structure to a metal structure so that the limitation of the polysilicon bitline structure at less than 7nm can be overcome.
With continued reference to fig. 8, the metal layer 210 may include a conductive line metal layer 211 and a barrier metal layer 222 wrapping the bottom and side surfaces of the conductive line metal layer 211, according to a specific embodiment of the present invention.
According to an embodiment of the present invention, the material of the conductive line metal layer 211 may be tungsten; the barrier metal layer 222 may be made of titanium or titanium nitride. The material for making the above layers may also be selected according to the actual situation, and the disclosure is not limited thereto.
According to an embodiment of the present invention, the insulating layer 220 may be a nitride layer, and the nitride layer may be made of silicon nitride or other nitride, which is not limited in the present disclosure.
With continued reference to fig. 8, in accordance with a specific embodiment of the present invention, the semiconductor substrate 100 includes at least one active region 120 defined by a device isolation layer 110.
At least one bit line contact trench 130 is formed on the device isolation layer 100, the bit line contact trench 130 exposes the active region 120, the bit line 200 is formed in the bit line contact trench 130, and the bit line 200 contacts the active region 120.
The semiconductor memory provided by the present disclosure has a bit line structure, in which the bit line structure is changed from a tungsten-barrier metal-polysilicon structure to a metal structure, so that the limitation of the bit line structure at less than 7nm can be overcome. And after removing the polysilicon, further stacking may be performed.
The embodiment of the present disclosure also provides an electronic device, which includes the semiconductor memory in the above embodiment. The electronic equipment comprises a smart phone, a computer, a tablet computer, wearable intelligent equipment, artificial intelligent equipment, a mobile power supply and the like.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to fall within the scope of the present disclosure.

Claims (13)

1. A bit line structure, comprising:
a semiconductor substrate;
at least one bit line on the semiconductor substrate;
the semiconductor substrate comprises at least one active region defined by a device isolation layer, the bit line is in contact with the active region, and the bit line comprises a metal layer and an insulating layer which are sequentially overlapped from the semiconductor substrate.
2. The bit line structure of claim 1, wherein the metal layer comprises:
a wire metal layer; and the number of the first and second groups,
and the barrier metal layer wraps the bottom surface and the side surface of the wire metal layer.
3. The bit line structure of claim 2, wherein the conductive metal layer is made of tungsten or cobalt; the barrier metal layer is made of titanium, tantalum, titanium nitride or tantalum nitride.
4. The bit line structure of claim 1, wherein the insulating layer is a silicon nitride layer.
5. The bit line structure of claim 1, wherein at least one bit line contact trench is formed on the device isolation layer, the bit line contact trench exposing the active region, the bit line being formed within the bit line contact trench.
6. A method for fabricating a bit line structure, comprising:
providing a semiconductor substrate; the semiconductor substrate comprises at least one active region defined by a device isolation layer;
forming at least one bit line contact trench on the device isolation layer, the bit line contact trench exposing the active region;
and forming a metal layer and an insulating layer which are sequentially overlapped from the bit line contact groove in the bit line contact groove, wherein the metal layer and the insulating layer form a bit line.
7. The method of manufacturing according to claim 6, wherein the metal layer comprises a wire metal layer and a barrier metal layer wrapping the bottom surface and the side surface of the wire metal layer;
the formation of the metal layer and the insulating layer in the bit line contact groove, which are sequentially overlapped from the bit line contact groove, includes:
depositing an oxide layer in the bit line contact groove, wherein the oxide layer is higher than the surface of the device isolation layer by a preset height;
etching a bit line contact hole and a bit line groove in the oxide layer by a Damascus process;
and sequentially forming a wire metal layer and a barrier metal layer wrapping the bottom surface and the side surface of the wire metal layer in the bit line groove.
8. The method of manufacturing according to claim 7, further comprising:
carrying out back etching on the metal layer in the bit line groove;
forming an insulating layer on the etched-back metal layer;
and removing the oxide layer.
9. The method of claim 8, wherein the etching back depth of the metal layer is the predetermined height.
10. The method of claim 7, wherein the etching bit line contact holes and bit line trenches in the oxide layer by a damascene process comprises:
etching the oxide layer by utilizing a first photoetching mask to form a bit line contact hole;
and etching the oxide layer by using a second photoetching mask to form a bit line groove.
11. A semiconductor memory, comprising:
the bit line structure of any of claims 1 to 5.
12. An electronic device, comprising:
the semiconductor memory as recited in claim 11.
13. The electronic device of claim 12, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.
CN202010292274.8A 2020-04-14 2020-04-14 Bit line structure, manufacturing method thereof, semiconductor memory and electronic equipment Active CN113540027B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050218408A1 (en) * 2004-04-02 2005-10-06 Yun Cheol-Ju Semiconductor devices having elongated contact plugs and methods of manufacturing the same
CN101872745A (en) * 2009-04-24 2010-10-27 海力士半导体有限公司 Semiconductor memory device and method for manufacturing the same
CN101882617A (en) * 2010-06-12 2010-11-10 中国科学院上海微系统与信息技术研究所 Schottky diode, semiconductor memory and manufacturing technology thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050218408A1 (en) * 2004-04-02 2005-10-06 Yun Cheol-Ju Semiconductor devices having elongated contact plugs and methods of manufacturing the same
CN101872745A (en) * 2009-04-24 2010-10-27 海力士半导体有限公司 Semiconductor memory device and method for manufacturing the same
CN101882617A (en) * 2010-06-12 2010-11-10 中国科学院上海微系统与信息技术研究所 Schottky diode, semiconductor memory and manufacturing technology thereof

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