CN114068537A

CN114068537A - Semiconductor memory, manufacturing method thereof and electronic equipment

Info

Publication number: CN114068537A
Application number: CN202010761200.4A
Authority: CN
Inventors: 全宗植; 吴容哲; 杨涛; 高建峰; 殷华湘
Original assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Current assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Priority date: 2020-07-31
Filing date: 2020-07-31
Publication date: 2022-02-18

Abstract

The present disclosure provides a semiconductor memory, a method of manufacturing the same, and an electronic apparatus. The semiconductor memory of the present disclosure includes: a bit line layer having at least one bit line; an active layer over the bit line layer and including at least one active region; a gate stack, sidewalls of the active region being surrounded by the gate stack; and a memory layer located above the active layer and including at least one memory region. The semiconductor memory vertically separates the layer where the bit line is located and the storage area to the upper part and the lower part of the active area, so that the two layers separated from each other in the upper part and the lower part and the contact connecting the middle active area are not on the same plane, the process margin on the plane is ensured, the limitation of the design level of the semiconductor memory can be improved, and the performance of the semiconductor memory is improved.

Description

Semiconductor memory, manufacturing method thereof and electronic equipment

Technical Field

The disclosure relates to the technical field of semiconductors, in particular to a semiconductor memory, a manufacturing method thereof and an electronic device.

Background

Dynamic Random Access Memory (DRAM) is a type of semiconductor Memory that generally includes an array of Memory cells, each cell capable of storing a bit of information. A typical memory cell configuration consists of a capacitor for storing charge (i.e., a bit of information) and an access transistor that provides an access signal to the capacitor during read and write operations. The access transistor is connected between the bit line and the capacitor, and is gated (turned on or off) by a word line signal. During a read operation, a bit of stored information is read from the cell via the associated bit line. During a write operation, a bit of information is stored in the cell from the bit line via the transistor. The memory cells are dynamic in nature (due to leakage) and therefore must be refreshed periodically.

In the conventional DRAM manufacturing method, an active region (a region where a transistor source/drain is located), a Bit Line (BL) and a storage region (a region where a capacitor is located) are sequentially formed from bottom to top, and the respective regions are separated from each other, so that a first contact (i.e., a Bit Line node contact) connecting the active region and the Bit Line and a second contact (i.e., a storage node contact) connecting the active region and the storage region are further provided. At this time, the second contact connecting the uppermost memory region passes through the first contact and the plane where the bit line exists to connect the electrodes of the memory regions.

Therefore, if there is a lack of sufficient process margin (margin) between the first contact and the second contact, leakage may occur, and if there is an insufficient separation distance between the second contact and the bit line, a current disturbance phenomenon may also occur, which causes difficulties in further scaling of the DRAM device.

Disclosure of Invention

The purpose of the present disclosure is to provide a semiconductor memory, a method of manufacturing the semiconductor memory, and an electronic apparatus.

A first aspect of the present disclosure provides a semiconductor memory comprising:

a bit line layer having at least one bit line;

an active layer over the bit line layer and including at least one active region;

a gate stack, sidewalls of the active region being surrounded by the gate stack; and the number of the first and second groups,

a storage layer located above the active layer and including at least one storage region.

A second aspect of the present disclosure provides a method for manufacturing a semiconductor memory, including:

providing a substrate;

forming at least one bit line on the substrate, and forming a bit line isolation film on the bit line;

forming a gate conductor layer on the bit line isolation film;

forming an active area groove penetrating through the gate conductor layer and the bit line isolation film until the bit line is exposed;

sequentially forming a gate dielectric layer, a side wall part of the active region and a plug part in the active region groove;

and forming a landing pad and a storage region on the top of the active region, wherein the top of the active region is in contact with the storage region through the landing pad.

A third aspect of the present disclosure provides an electronic device, comprising:

the semiconductor memory as described in the first aspect.

This disclosure compares advantage with prior art and lies in:

(1) no other conductive material is present on the bit line plane, which reduces parasitic capacitance.

(2) Since there is no other conductive material on the bit line plane, the width of the bit line can be increased to reduce the resistance of the bit line.

(3) The vertical channel is formed, so that the length of the channel can be conveniently adjusted.

(4) In the channel process, the bit line contact and the memory contact processes may be performed together, and thus the process may be simplified.

(5) The bit lines and the bit line contact and memory contact processes are not performed in the same plane, and thus, a separation process margin is not required to be considered.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1A illustrates a plan view of a semiconductor memory provided by the present disclosure;

FIG. 1B shows a cross-sectional view taken along line a in FIG. 1;

FIG. 1C shows a cross-sectional view taken along line b in FIG. 1;

FIG. 2 is a flow chart illustrating a method of fabricating a semiconductor memory provided by the present disclosure;

FIG. 3A illustrates a plan view of the semiconductor memory device of the present disclosure after a bit line formation stage;

FIG. 4A illustrates a plan view of the semiconductor memory device of the present disclosure after a stage in the formation of the gate conductor layer;

FIG. 5A is a plan view of the semiconductor memory of the present disclosure after an active area trench formation stage;

FIG. 6A is a plan view of the semiconductor memory of the present disclosure after the active region formation stage;

fig. 3B to 6B are cross-sectional views taken along line a of fig. 3A to 6A;

fig. 3C to 6C are cross-sectional views taken along line b of fig. 3A to 6A;

fig. 5D to 5F are sectional views of stages of forming an active region on the basis of fig. 5B.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

The conventional DRAM manufacturing method is to sequentially form, from bottom to top, a layer in which an active region is located, a layer in which a bit line is located, and a layer in which a storage region is located, and the regions are separated from each other, and thus, a first contact (i.e., a bit line node contact) connecting the active region and the bit line and a second contact (i.e., a storage node contact) connecting the active region and the storage region are provided. At this time, the second contact connecting the uppermost memory region passes through the first contact and the plane where the bit line exists to connect the electrodes of the memory regions.

Therefore, if a process margin (margin) is lacking between the first contact and the second contact, leakage may be caused, and if a separation distance between the second contact and the bit line is insufficient, current disturbance and the like may be caused.

In order to solve the above-mentioned problems in the prior art, embodiments of the present disclosure provide a semiconductor memory, a method for manufacturing the semiconductor memory, and an electronic device, which are described below with reference to the accompanying drawings.

Fig. 1A illustrates a plan view of a semiconductor memory provided by the present disclosure; FIG. 1B shows a cross-sectional view taken along line a in FIG. 1A; fig. 1C shows a cross-sectional view taken along line b in fig. 1A.

Referring to fig. 1A to 1C, the semiconductor memory includes: the bit line layer 100, the active layer 200, the memory layer 300, and the gate stack 210 are sequentially disposed from bottom to top in a vertical direction.

Specifically, the bit line layer 100 has at least one bit line 110. The active layer 200 is positioned above the bit line layer 100 and includes at least one active region 220, and sidewalls of the active region 220 are surrounded by the gate stack 210. The memory layer 300 is positioned above the active layer 200 and includes at least one memory region (not shown). In an embodiment of the present invention, the storage region includes a capacitor structure, which may be, for example, a lower electrode, a dielectric layer, and an upper electrode (not shown).

Specifically, the active region 220 is circular in horizontal cross-section, and as shown, the active region 220 is vertically cylindrical.

Specifically, the bit line layer 100 further includes: a bit line substrate 120, the at least one bit line 110 being located on the bit line substrate 120; and a bit line isolation film 130 covering the at least one bit line 110.

Specifically, the bit line substrate 120 may be made of silicon dioxide, the bit line 110 may be made of tungsten, and the bit line isolation film 130 may be made of silicon nitride. Of course, the material for making the above-mentioned parts may be other materials meeting the requirements, and the disclosure does not limit this.

With continued reference to fig. 1A-1C, the bottom of the active region 220 contacts the bit line 110 through the bit line isolation film 130. The top of the active area 220 is in contact with a storage region in the storage layer 300 through a landing pad 230.

Specifically, the active region 220 includes a plug 222 and a sidewall 221 surrounding the plug 222, a top of the plug 222 contacts the memory region in the memory layer 300 through the landing pad 230, and a bottom of the plug 222 contacts the bit line 110 through the bit line isolation film 130.

Specifically, the plug 222 of the active region 220 and the sidewall 221 surrounding the plug 222 may be made of doped polysilicon.

Specifically, the gate stack 210 includes a gate dielectric layer 211 and a gate conductor layer 212, the gate conductor layer 212 is lower than the active region 220, and the gate dielectric layer 211 is flush with the active region 220. One side of the gate dielectric layer 211 is attached to the sidewall and the bottom wall of the sidewall 221 of the active region 220, and the other side of the gate dielectric layer 211 is attached to the gate conductor layer 212. That is, the sidewalls of the active region 220 are surrounded by the gate dielectric layer 211.

Specifically, the gate conductor layer 212 and the landing pad 230 may be made of tungsten, and the gate dielectric layer 211 may be made of silicon dioxide.

Compared with the existing semiconductor memory, the semiconductor memory provided by the disclosure vertically separates the layer where the bit line is located and the memory region to the upper part and the lower part of the active region, so that the two layers separated from the upper part and the lower part and the contact connecting the middle active region are not on the same plane, the process margin on the plane is ensured, the limitation of the design level of the semiconductor memory can be improved, and the performance of the semiconductor memory is improved.

Referring to fig. 2, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor memory, which is used to manufacture the semiconductor memory in the above embodiment; fig. 3A to 6A and fig. 1A show various stages of an embodiment of a method of manufacturing a semiconductor memory. Fig. 3B to 6B and 1B are cross-sectional views taken along line a of fig. 3A to 6A and 1A; fig. 3C to 6C and 1C are cross-sectional views taken along line b in fig. 3A to 6A and 1A; fig. 5D to 5F are semiconductor structure diagrams based on fig. 5B.

The manufacturing method comprises the following steps:

step S101: a substrate 120 is provided.

Step S102: at least one bit line 110 is formed on a substrate 120, and a bit line isolation film 130 is formed on the bit line 110.

Specifically, referring to fig. 3A to 3C, the substrate 120 may be made of silicon dioxide and have a certain thickness. The bit line 110 may be patterned on the substrate 120 as shown in the figure, and the bit line isolation film 130 may be deposited on the bit line 110 through related processes, specifically, the bit line 110 may be made of tungsten, and the bit line isolation film 130 may be made of silicon nitride. Of course, the material for making the above-mentioned parts may be other materials meeting the requirements, and the disclosure does not limit this. It can be seen that since no other conductive species is disposed on the bit line plane, the bit line capacitance can be reduced and the resistance of the bit line can be reduced by increasing the width of the bit line.

Step S103: a gate conductor layer 212 is formed on the bit line isolation film 130.

Specifically, referring to fig. 4A to 4C, after the process of forming the bit line isolation film 130 is performed, the gate conductor layer 212 may be patterned on the bit line isolation film 130 as shown in the figure through a related process. Specifically, the gate conductor layer 212 may be made of tungsten. The gate conductor layer 212 is patterned, for example, by a damascene process and a photolithography process.

Step S104: an active region trench H penetrating the gate conductor layer 212 and the bit line isolation film 130 is formed until the bit line 110 is exposed.

Specifically, referring to fig. 5A to 5C, after the pattern of the gate conductor layer 212 is formed, an isolation layer made of silicon nitride may be deposited on the gate conductor layer 212, and a photolithography and etching process may be performed at the intersection of the bit line 110 pattern and the gate conductor layer 212 pattern to form a pattern of an active region trench H until the underlying bit line 110 is exposed, and the bottom of the active region trench H may be slightly recessed into the bit line 110 for the subsequent contact between the bit line and the active region.

Step S105: and sequentially forming a gate dielectric layer 211, a sidewall 221 of the active region and a plug 222 in the active region groove H.

The specific manufacturing process is illustrated on the basis of fig. 5B, and referring to fig. 5D, a gate dielectric layer 211 and a first layer of doped polysilicon 221 are sequentially deposited on the sidewall and the bottom wall of the active region trench H. Referring to fig. 5E, the gate dielectric layer 211 and the first layer of doped polysilicon 221 are etched to form the sidewalls 221 of the active region 220 and the bit lines 110 exposed at the bottom, which may be specifically manufactured by using a conventional sidewall process. Referring to fig. 5F, a second layer of doped polysilicon is deposited in the space surrounded by the sidewall 221, and then a Chemical Mechanical Planarization (CMP) process is used to remove the excess doped polysilicon outside the active region trench H, thereby forming the plug 222 of the active region. Specifically, in the semiconductor structure after the active region is formed, as shown in fig. 6A to 6C, in this step, a vertical active region is formed, so that the length of the active region is easily adjusted. And through this step, the active region and the bit line are directly connected without performing other contact processes, so that the process steps can be simplified.

Step S106: and forming a landing pad and a storage region on the top of the active region, wherein the top of the active region is contacted with the storage region through the landing pad. The storage region may include a capacitive structure.

Specifically, referring to fig. 1A to 1C, as shown, in order to form the memory region, a honeycomb-like Landing PAD (bonding PAD)230 is formed on the active region 220, the Landing PAD 230 may be made of tungsten, and silicon dioxide is filled between the Landing PADs. By this step, the top of the active area and the storage area are connected by the landing pad without performing other contact processes, and thus the process steps can also be simplified.

In the above method, in the active channel process, the bit line contact and the memory contact process are performed together, so that the process can be simplified. And the bit lines and the bit line contact and memory contact processes are not performed on the same plane, so that the separation margin is not required to be considered.

According to the semiconductor memory manufactured by the method, the layer where the bit line is located and the storage area are vertically separated to the upper part and the lower part of the active area, so that the two layers separated from the upper part and the lower part and the contact for connecting the middle active area are not on the same plane, the process margin on the plane is ensured, the limitation of the design level of the semiconductor memory can be improved, and the performance of the semiconductor memory is improved.

The embodiment of the present disclosure also provides an electronic device, which includes the semiconductor memory in the above embodiment. The semiconductor memory may be incorporated into at least one of a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.

Specifically, the gate stack 210 includes a gate dielectric layer 211 and a gate conductor layer 212, the gate conductor layer 212 is lower than the active region 220, and the gate dielectric layer 211 is flush with the active region 220. One side of the gate dielectric layer 211 is attached to the sidewall and the bottom wall of the sidewall 221 of the active region 220, and the other side of the gate dielectric layer 211 is attached to the gate conductor layer 212.

According to the electronic device, the layer where the bit line is located and the storage area are vertically separated to the upper part and the lower part of the active area, so that the two layers separated from the upper part and the lower part and the contact for connecting the middle active area are not on the same plane, the process margin on the plane is ensured, the limitation of the design level of the semiconductor memory can be improved, and the performance of the semiconductor memory is improved.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to fall within the scope of the present disclosure.

Claims

1. A semiconductor memory, comprising:

a bit line layer having at least one bit line;

2. The semiconductor memory according to claim 1, wherein the horizontal cross section of the active region is circular.

3. The semiconductor memory according to claim 2, wherein the bit line layer further comprises:

a bit line substrate on which the at least one bit line is located; and the number of the first and second groups,

a bit line isolation film covering the at least one bit line.

4. The semiconductor memory according to claim 3, wherein the active region bottom is in contact with a bit line through the bit line isolation film.

5. The semiconductor memory according to claim 4, wherein the top of the active region is in contact with the storage region through a landing pad.

6. The semiconductor memory according to claim 5, wherein the active region includes a plug and a sidewall surrounding the plug, a top of the plug contacts the memory region through a landing pad, and a bottom of the plug contacts the bit line through the bit line isolation film.

7. The semiconductor memory of claim 6, wherein the gate stack comprises a gate dielectric layer and a gate conductor layer, the gate dielectric layer being between the gate conductor layer and the active region;

the height of the gate conductor layer is lower than that of the active area, and the height of the gate dielectric layer is flush with that of the active area.

8. The semiconductor memory according to any one of claims 1 to 7, wherein the storage region includes a capacitance.

9. A method for manufacturing a semiconductor memory, comprising:

providing a substrate;

forming a gate conductor layer on the bit line isolation film;

sequentially forming a gate dielectric layer, a side wall of the active region and a plug in the active region groove;

10. The method of claim 9, wherein sequentially forming a gate dielectric layer, a sidewall spacer of the active region and a plug in the active region trench comprises:

depositing a gate dielectric layer and a first layer of doped polysilicon on the side wall and the bottom wall of the active area groove in sequence;

etching the gate dielectric layer and the first layer of doped polysilicon to form a side wall of the active region and expose the bit line;

and depositing a second layer of doped polysilicon in the space surrounded by the side wall to form a plug of the active region.

11. An electronic device, comprising:

the semiconductor memory according to any one of claims 1 to 8.

12. The electronic device of claim 11, wherein the semiconductor memory is incorporated into at least one of a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.