CN105161418A - Semiconductor device, manufacturing method thereof, and electronic device - Google Patents
Semiconductor device, manufacturing method thereof, and electronic device Download PDFInfo
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- CN105161418A CN105161418A CN201410260442.XA CN201410260442A CN105161418A CN 105161418 A CN105161418 A CN 105161418A CN 201410260442 A CN201410260442 A CN 201410260442A CN 105161418 A CN105161418 A CN 105161418A
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Abstract
The invention provides a semiconductor device, a manufacturing method thereof, and an electronic device. The manufacturing method comprises the steps: providing a semiconductor substrate, wherein fin structures are formed on the semiconductor substrate; forming a grid material layer over the semiconductor substrate and the fin structures through deposition, wherein multiple protrusions are formed on the surface of the grid material layer; forming a sacrificial material layer on the grid material layer through deposition; performing first chemical mechanical grinding, ending the grinding on the top surface of the grid material layer, and enabling part of the sacrificial material layer to remain among the adjacent protrusions; and performing second chemical mechanical grinding to fully remove the remaining sacrificial material layer. According to the method of the invention, the thickness of the grid material layer is better controlled by effectively monitoring grinding ending points, the flatness of the surface of the grid material layer is improved, steps are prevented, and then the performance and the yield rate of the device are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and preparation method thereof and electronic installation.
Background technology
The raising of performance of integrated circuits is mainly realized with the speed improving it by the size constantly reducing integrated circuit (IC)-components.At present, because in pursuit high device density, high-performance and low cost, semi-conductor industry has advanced to nanometer technology process node, particularly when dimensions of semiconductor devices drops to 22nm or be following, the challenge from manufacture and design aspect result in the development of three dimensional design as FinFET (FinFET).
Relative to existing planar transistor, described FinFET has more superior performance in raceway groove control and reduction shallow channel effect etc., planar gate is arranged at above described raceway groove, and gate loop is arranged around described fin in FinFET, therefore can control electrostatic from three faces, the performance in electrostatic control is also more outstanding; Simultaneously compacter again, improve the integrated level of device, be therefore used widely in analog circuit (analogcircuits) and static memory (SRAMs).
But, many problems are faced in the manufacturing process of FinFET, such as, after polysilicon gate material layer deposition, because the density degree of fin structure on substrate is different, cause the surface state of polysilicon gate material layer different, cause the cmp (ChemicalMechanicalPolishing afterwards, be called for short CMP) in process, be difficult to catch grinding endpoint, and the appearance of the rugged step problem in polysilicon gate material layer surface after being difficult to control grinding.
Therefore, be necessary to propose a kind of new manufacture method, to solve the deficiencies in the prior art.
Summary of the invention
For the deficiencies in the prior art, the embodiment of the present invention one provides a kind of manufacture method of semiconductor device, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with fin structure;
In described Semiconductor substrate and described fin structure, deposition forms gate material layers, and the surface of wherein said gate material layers is formed with multiple projection;
In described gate material layers, deposition forms sacrificial material layer;
Perform the first cmp, stop on the end face of described gate material layers, and residue there is the described sacrificial material layer of part between adjacent protrusion;
Perform the second cmp, to remove remaining described sacrificial material layer completely.
Further, described gate material layers is polysilicon layer.
Further, the material of described sacrificial material layer is oxide.
Further, control object height that the height of described gate material layers in rarefaction is greater than predetermined gate material layers and a polishing wheel height with.
Further, the thickness of described sacrificial material layer is 2000 ~ 3500 dusts.
Further, chemical vapour deposition technique is adopted to form described sacrificial material layer.
Further, the ground slurry with high selectivity is adopted to carry out described first cmp.
Further, optical end point detection or the grinding endpoint of current of electric end point determination to described first cmp is adopted to detect.
Further, low selectivity ground slurry is adopted to carry out described second cmp.
Further, as the grinding endpoint of described second cmp when adopting the remaining described sacrificial material layer of optical end point detection method seizure to be removed completely.
Further, when performing described second cmp, the excessive polishing process of certain hour can also be carried out, to make the surface of described gate material layers more smooth.
Further, after described second cmp, also comprise the step of execution the 3rd cmp, described 3rd cmp is chemical polishing process.
Further, between described fin structure, fleet plough groove isolation structure is formed with.
The embodiment of the present invention two provides a kind of semiconductor device adopting above-mentioned method to make, and described semiconductor device has smooth gate material layers.
The embodiment of the present invention three provides a kind of electronic installation, and it comprises above-mentioned semiconductor device.
In sum, according to method of the present invention, effectively can monitor grinding endpoint and realize the better control to grid material layer thickness, improve the evenness on gate material layers surface simultaneously, avoid the appearance of shoulder height, and then improve performance and the yield of device.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The schematic cross sectional view of the device that the step that the method that Figure 1A-1D is prior art is implemented successively obtains respectively;
The schematic cross sectional view of the device that Fig. 2 A-2E obtains respectively for the step implemented successively according to the method for the embodiment of the present invention one;
Fig. 3 is the flow chart of the step implemented successively according to the method for the embodiment of the present invention one.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, by following description, detailed structure is proposed, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Below, with reference to figure 1A-1D, brief description is carried out to the implementation step of the gate material layers deposition post-chemical mechanical polishing process of existing FinFET.
First as shown in Figure 1A, Semiconductor substrate 100 is provided, be formed with fin structure 101 on the semiconductor substrate, fleet plough groove isolation structure 102 is formed between described fin structure, on described fin structure 101 and fleet plough groove isolation structure 102, deposition forms polysilicon gate material layer 103, afterwards, polysilicon gate material layer surface defines three kinds of different patterns:
Region A: this region corresponds to the smaller compact district of the spacing of FinFET fin chip architecture, polysilicon gate material layer surface is mild, and peak (height) is positioned at the top of fin structure.
Region B: this region corresponds to the larger compact district of the gap ratio of FinFET fin chip architecture, and several island polysilicon peaks of the formation on polysilicon gate material layer surface, it is between fin and fleet plough groove isolation structure.
Region C: this region corresponds to the rarefaction of FinFET fin chip architecture, the polysilicon gate material layer above fleet plough groove isolation structure is easily subject to the impact of CMP dish (Dishing) effect.
As shown in Figure 1B, perform the first cmp, remove multiple peaks that polysilicon gate material layer 103 surface is outstanding, with planarization polysilicon gate material layer surface.In this step, add and have inhibitor 104 in lapping liquid, inhibitor can prevent grinding too fast.
As shown in Figure 1 C, perform the second cmp, further grinding and polishing is carried out, until be polished to desired value to polysilicon gate material layer 103.In this step, in lapping liquid, inhibitor 104 is inoperative.
As shown in figure ip, carry out chemical polishing, remove the defects such as surperficial cut or depression.
The surface of final polysilicon gate material layer has rugged step, and then affects performance and the yield of device.
Given this, the present invention proposes a kind of new manufacture method, to solve the problem.
Embodiment one
Below, with reference to Fig. 2 A ~ 2E, the step that the present invention implements successively is described in detail.
First, with reference to figure 2A, there is provided Semiconductor substrate 200, described Semiconductor substrate 200 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Described Semiconductor substrate 200 is formed with fin structure 201.Alternatively, described fin 201 is silicon fin, and the conventional method in this area can be adopted to form described silicon fin.Exemplarily, first on a semiconductor substrate semiconductor material layer is formed, described semiconductor material layer can Si, SiGe, Ge or III-V material, semiconductor material layer deposits pad oxide and pad nitride layer successively, then on described semiconductor material layer, form the mask layer of patterning, such as photoresist mask layer, described photoresist mask layer defines the width of described fin structure, length and position etc., then nitride layer is padded with described photoresist mask layer for described in mask etch, pad oxide and semiconductor material layer, to form fin, then described photoresist mask layer is removed, the method removing described photoresist mask layer can be oxidative ashing method.It should be noted that the formation of described fin structure 201 is only exemplary
Exemplarily, be divided into three regions according to the density degree of fin structure 201, wherein, the minimum compact district of fin pitch is called A district, and the compact district that fin pitch is relatively large is called B district, and the rarefaction that fin pitch is large is called C district.
Between described fin structure 201, be formed with fleet plough groove isolation structure 202, simple its forming process that describes is: between described fin structure, fill separator, the material of separator can be oxide, nitride or nitrogen oxide etc.Carry out etch back process afterwards with fin structure described in exposed portion, and then form the fleet plough groove isolation structure of the described fin structure of isolation.
Gate material layers 203 is formed at the disposed thereon of described fin structure 201 and fleet plough groove isolation structure 202.
The constituent material of gate material layers 203 comprise in polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide one or more, wherein, metal can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride comprises titanium nitride (TiN); Conductive metal oxide comprises yttrium oxide (IrO2); Metal silicide comprises titanium silicide (TiSi).When selecting the constituent material of polysilicon as gate material layers, low-pressure chemical vapor phase deposition (LPCVD) technique can be selected to form gate material layers, its process conditions comprise: reacting gas is silane (SiH4), and its flow is 100 ~ 200sccm, preferred 150sccm; Temperature in reaction chamber is 700 ~ 750 DEG C; Pressure in reaction chamber is 250 ~ 350mTorr, preferred 300mTorr; Described reacting gas can also comprise buffer gas, and described buffer gas is helium (He) or nitrogen (N2), and its flow is 5 ~ 20 liters/min (slm), preferred 8slm, 10slm or 15slm.Due to being uneven of semiconductor substrate structure, therefore be formed with multiple protruding 203a on the surface of the gate material layers formed.
When carrying out this step, control in rarefaction, C district (such as, the pad area that area is greater than 50 μm * 50 μm) height of interior deposition of gate material layer 203, ensure object height that the height of gate material layers is greater than the predetermined gate material layers formed and a polishing wheel height with.
As shown in Figure 2 B, sacrificial material layer 204 is formed at the surface deposition of described gate material layers 203.
Exemplarily, the material of described sacrificial material layer 204 can be oxide, nitride or nitrogen oxide etc.In one example, the material of described sacrificial material layer is oxide.Alternatively, the thickness of described sacrificial material layer is 2000 ~ 3500 dusts.Chemical vapour deposition technique (CVD) can be adopted, plasma activated chemical vapour deposition (PECVD), the methods such as such as sputter and physical vapour deposition (PVD) (PVD) also can be used to form described sacrificial material layer 204.
As shown in Figure 2 C, perform the first cmp, stop on the end face of gate material layers 203.
The ground slurry with high selectivity is adopted to carry out described first cmp.Exemplarily, the ground slurry that sacrificial material layer and gate material layers Selection radio are greater than 4 can be selected.In one example, gate material layers is polysilicon layer, and sacrificial material layer is oxide skin(coating), then can select the ground slurry comprising CeO2 and/or SiO2 abrasive grains, and have the inhibiting inhibitor of grinding by increasing in ground slurry to polysilicon, realize larger Selection radio, described inhibitor can be the ethylene oxide adduct or alkoxylate straight-chain fatty alcohol etc. of polyethylene glycol, acetylenic diol.Owing to having high selectivity, it is far longer than the grinding rate to gate material layers 203 to the grinding rate of sacrificial material layer 204.General CMP equipment is all equipped with end point determination device, to detect the terminal of grinding as required.When material is ground to a default target thickness or target material (target location), namely end point determination device sends the signal stopping grinding.In an example, optical end point detection or the grinding endpoint of current of electric end point determination to described first cmp is adopted to detect.
Because gate material layers 203 surface is uneven, after therefore the first cmp stops, between the adjacent protrusion 203a on the surface of gate material layers 203, also residue has the sacrificial material layer 204 of part.
As shown in Figure 2 D, perform the second cmp, to remove remaining sacrificial material layer completely.
Carry out the second cmp, to remove remaining sacrificial material layer completely.Preferably, low selectivity ground slurry is adopted to carry out the second cmp.This ground slurry has substantially identical grinding rate to remaining sacrificial material layer and gate material layers.Alternatively, described low selectivity ground slurry comprises pyrogenic silica, water, potassium hydroxide etc.In one example, gate material layers is polysilicon layer, and sacrificial material layer is oxide skin(coating), then can be reached the 1:1 grinding rate of oxide and polysilicon by adjustment dilution ratio.Use low optionally ground slurry that gate material layers 203 surface after the second cmp can be made very smooth.Exemplarily, employing optical end point detection method catches the grinding endpoint as the second cmp when remaining sacrificial material layer is removed completely.Alternatively, excessive polishing (overpolish, the OP) process of certain hour can also be carried out, to make the surface of gate material layers 203 more smooth.
As shown in Figure 2 E, perform the 3rd cmp, to improve the defect that gate material layers 203 surface exists.
Described 3rd cmp is chemical polishing process, chemical reactions such as corroding is there is by the chemical composition in ground slurry and gate material layers 203, reduce surface roughness, improve the defect such as cut, slight step that causes of grinding due to speed in early stage.In one example, ground slurry comprises pyrogenic silica, water, potassium hydroxide etc., can realize described 3rd cmp by adjustment dilution ratio.
In sum, according to method of the present invention, effectively can monitor grinding endpoint and realize the better control to grid material layer thickness, improve the evenness on gate material layers surface simultaneously, avoid the appearance of shoulder height, and then improve performance and the yield of device.
Fig. 3 is the flow chart of the step that in the embodiment of the present invention one, method is implemented successively, to schematically illustrate whole technical process, comprises the steps:
In step 301, provide Semiconductor substrate, described Semiconductor substrate is formed with fin structure;
In step 302, in described Semiconductor substrate and described fin structure, deposition forms gate material layers, and the surface of wherein said gate material layers is formed with multiple projection;
In step 303, in described gate material layers, deposition forms sacrificial material layer;
In step 304, perform the first cmp, stop on the end face of described gate material layers, and residue there is the described sacrificial material layer of part between adjacent protrusion;
In step 305, perform the second cmp, to remove remaining described sacrificial material layer completely;
Within step 306, the 3rd cmp is performed.
Embodiment two
The present invention also provides a kind of and adopts the semiconductor device that in embodiment one, method makes, and wherein, described semiconductor device has smooth gate material layers.
In the semiconductor device prepared by the method for the invention, gate material layers is smooth, all there is not surface height difference in compact district and rarefaction, therefore has excellent performance and yield.
Embodiment three
The present invention also provides a kind of electronic installation in addition, and it comprises aforesaid semiconductor device.
Because the semiconductor device comprised has higher yield and performance, this electronic installation has above-mentioned advantage equally.
This electronic installation, can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be the intermediate products with above-mentioned semiconductor device, such as: the cell phone mainboard etc. with this integrated circuit.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (15)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with fin structure;
In described Semiconductor substrate and described fin structure, deposition forms gate material layers, and the surface of wherein said gate material layers is formed with multiple projection;
In described gate material layers, deposition forms sacrificial material layer;
Perform the first cmp, stop on the end face of described gate material layers, and residue there is the described sacrificial material layer of part between adjacent protrusion;
Perform the second cmp, to remove remaining described sacrificial material layer completely.
2. method according to claim 1, is characterized in that, described gate material layers is polysilicon layer.
3. method according to claim 1, is characterized in that, the material of described sacrificial material layer is oxide.
4. method according to claim 1, is characterized in that, control object height that the height of described gate material layers in rarefaction is greater than predetermined gate material layers and a polishing wheel height with.
5. method according to claim 1, is characterized in that, the thickness of described sacrificial material layer is 2000 ~ 3500 dusts.
6. method according to claim 1, is characterized in that, adopts chemical vapour deposition technique to form described sacrificial material layer.
7. method according to claim 1, is characterized in that, adopts the ground slurry with high selectivity to carry out described first cmp.
8. method according to claim 1, is characterized in that, adopts optical end point detection or the grinding endpoint of current of electric end point determination to described first cmp to detect.
9. method according to claim 1, is characterized in that, adopts low selectivity ground slurry to carry out described second cmp.
10. method according to claim 1, is characterized in that, as the grinding endpoint of described second cmp when adopting the remaining described sacrificial material layer of optical end point detection method seizure to be removed completely.
11. methods according to claim 1, is characterized in that, when performing described second cmp, can also carry out the excessive polishing process of certain hour, to make the surface of described gate material layers more smooth.
12. methods according to claim 1, is characterized in that, after described second cmp, also comprise the step of execution the 3rd cmp, and described 3rd cmp is chemical polishing process.
13. methods according to claim 1, is characterized in that, between described fin structure, be formed with fleet plough groove isolation structure.
14. 1 kinds of semiconductor device adopting the method described in claim 1-13 to make, it is characterized in that, described semiconductor device has smooth gate material layers.
15. 1 kinds of electronic installations, it comprises the semiconductor device described in claim 14.
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Cited By (6)
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| CN105957818A (en) * | 2016-05-17 | 2016-09-21 | 上海华力微电子有限公司 | Film thickness introducing method in chemical mechanical polishing process model calibration and verification process |
| CN107437565A (en) * | 2016-05-31 | 2017-12-05 | 三星电子株式会社 | Semiconductor devices and the method being used for producing the semiconductor devices |
| CN108228943A (en) * | 2016-12-21 | 2018-06-29 | 中国科学院微电子研究所 | A kind of CMP process modeling method of FinFET |
| CN109987575A (en) * | 2017-12-29 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS device and preparation method, electronic device |
| CN111554574A (en) * | 2020-05-19 | 2020-08-18 | 中国科学院微电子研究所 | Planarization method, semiconductor device and manufacturing method thereof |
| CN114038755A (en) * | 2021-10-25 | 2022-02-11 | 上海华力集成电路制造有限公司 | Etching method |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105957818A (en) * | 2016-05-17 | 2016-09-21 | 上海华力微电子有限公司 | Film thickness introducing method in chemical mechanical polishing process model calibration and verification process |
| CN105957818B (en) * | 2016-05-17 | 2018-08-24 | 上海华力微电子有限公司 | Chemical mechanical milling tech model calibration verifies film thickness introducing method in flow |
| CN107437565A (en) * | 2016-05-31 | 2017-12-05 | 三星电子株式会社 | Semiconductor devices and the method being used for producing the semiconductor devices |
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| CN108228943A (en) * | 2016-12-21 | 2018-06-29 | 中国科学院微电子研究所 | A kind of CMP process modeling method of FinFET |
| CN109987575A (en) * | 2017-12-29 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS device and preparation method, electronic device |
| CN111554574A (en) * | 2020-05-19 | 2020-08-18 | 中国科学院微电子研究所 | Planarization method, semiconductor device and manufacturing method thereof |
| CN111554574B (en) * | 2020-05-19 | 2023-03-21 | 中国科学院微电子研究所 | Planarization method, semiconductor device and manufacturing method thereof |
| CN114038755A (en) * | 2021-10-25 | 2022-02-11 | 上海华力集成电路制造有限公司 | Etching method |
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Effective date of registration: 20200302 Address after: 201203 5th floor, building 3, No. 18, Zhangjiang Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Zhongxin Nanfang integrated circuit manufacturing Co., Ltd Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corp. |