CN113745162B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113745162B
CN113745162B CN202010473447.6A CN202010473447A CN113745162B CN 113745162 B CN113745162 B CN 113745162B CN 202010473447 A CN202010473447 A CN 202010473447A CN 113745162 B CN113745162 B CN 113745162B
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forming
device region
source
channel
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CN113745162A (en
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陈蓉峰
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a first device region and a second device region, the substrate comprises a substrate and a channel structure separated on the substrate, the extending direction of the channel structure is the same as the extending direction of the junction of the first device region and the second device region, and the substrate further comprises a grid structure crossing the channel structure; forming a first source-drain doping layer in the channel structure of the first device region; forming a shielding layer which is positioned on the first source-drain doping layer and exposes the second device region; forming a protective layer on the side wall of the shielding layer and the side wall of the grid structure; and forming a second source-drain doping layer in the channel structure of the second device region. According to the method, in the epitaxial growth process, the side wall of the gate structure and the first source-drain doped layer do not have an epitaxial growth basis, the impurity epitaxial layer is not easy to form on the gate structure and the first source-drain doped layer, and bridging risks caused by the impurity epitaxial layer can be reduced.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short channel effect (SCE-CHANNEL EFFECTS) is more likely to occur.
Accordingly, to better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; the gate structure is also changed from the original polysilicon gate structure to a metal gate structure, and the work function layer in the metal gate structure can adjust the threshold voltage of the semiconductor structure.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device region and a second device region, the first device region is used for forming a first type transistor, the second device region is used for forming a second type transistor, the substrate comprises a substrate and a channel structure which is separated on the substrate, the extending direction of the channel structure is the same as the extending direction of the junction of the first device region and the second device region, the substrate further comprises a grid structure which spans the channel structure, and the grid structure covers part of the top wall and part of the side wall of the channel structure; forming a first source-drain doping layer in the channel structure at two sides of the gate structure of the first device region; forming a shielding layer which is positioned on the first source-drain doping layer and exposes the second device region; forming a protective layer on the side wall of the shielding layer and the side wall of the grid structure; and forming a second source-drain doping layer in the channel structure of the second device region, wherein the conductivity types of the second source-drain doping layer and the first source-drain doping layer are different.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate comprising a first device region for forming a first type transistor and a second device region for forming a second type transistor; the channel structure is separated on the substrate, and the extending direction of the channel structure is the same as the extending direction of the junction of the first device region and the second device region; a gate structure crossing the channel structure and covering a portion of a top wall and a portion of a side wall of the channel structure; the first source-drain doped layer is positioned in the channel structure at two sides of the grid structure of the first device region; the shielding layer is positioned in the first device region and covers the grid structure, the first source drain doping layer and the channel structure of the first device region; and the protective layer is positioned on the side wall of the shielding layer and the side wall of the grid structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the method for forming the semiconductor structure provided by the embodiment of the invention, the protective layer is formed on the shielding layer and the side wall of the gate structure, the second source-drain doped layer is usually formed by adopting a selective epitaxial growth process in the second device region, and the protective layer enables the side wall of the gate structure and the first source-drain doped layer in the shielding layer to be not easy to be exposed, so that the protective layer can enable the side wall of the gate structure and the first source-drain doped layer in the shielding layer to not easily have an epitaxial growth basis in the epitaxial growth process, and an impurity epitaxial layer is not easy to be formed on the gate structure at the junction of the first device region and the second device region and on the first source-drain doped layer, so that bridging risk caused by the impurity epitaxial layer can be reduced, the probability of leakage current of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is favorable to be optimized.
Drawings
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
Fig. 4 to 8 are schematic structural views corresponding to steps in another method for forming a semiconductor structure;
Fig. 9 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 18 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The semiconductor structure formed at present still has the problem of poor performance. The reason for the poor performance of the semiconductor structure is analyzed by combining a forming method of the semiconductor structure.
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.
As shown in fig. 1, a substrate is provided, the substrate includes a first device region I and a second device region II, the first device region I is used for forming a first type transistor, the second device region II is used for forming a second type transistor, the substrate includes a substrate 1, a fin 2 separated on the substrate 1, an extension direction of the fin 2 is the same as an extension direction of a junction between the first device region I and the second device region II, and the substrate further includes a gate structure (not shown) crossing the fin 2, the gate structure covers a part of a top wall and a part of a side wall of the fin 2; forming a first source-drain doped layer 3 in the fin part 2 at two sides of the gate structure of the first device region I; forming a side wall material layer 5 of the substrate covering the first device region I and the second device region II; and forming a shielding layer 4 which is positioned on the first source-drain doped layer 3 and exposes the second device region II.
As shown in fig. 2, the side wall material layers 5 on both sides of the gate structure of the second device region II and the fin portion 2 with partial thickness are etched, a recess 6 is formed in the fin portion 2,
As shown in fig. 3, a second source-drain doped layer 7 is formed in the groove 6; and after the second source-drain doped layer 7 is formed, removing the shielding layer 4.
The step of forming the shielding layer 4 generally comprises: forming a shielding material layer covering the first device region I and the second device region II; patterning the shielding material layer, wherein the remaining shielding material layer located in the first device region I is used as a shielding layer 4, in the actual patterning process, an overlay error exists, a part of the sidewall material layer 5 on the first source/drain doped layer 3 is easy to be exposed, in the step of forming a groove 6 in the gate structure of the second device region II by etching, the sidewall material layer 5 on the first source/drain doped layer 3 exposed by the shielding layer 4 is easy to be removed, so that a part of the area of the first source/drain doped layer 3 is exposed, in the step of forming a second source/drain doped layer 7 in the groove 6, an impurity epitaxial layer 8 (as shown in fig. 3) is easy to be formed on the first source/drain doped layer 3 exposed by the shielding layer 4, and the impurity epitaxial layer 8 is easy to bridge with other devices, thereby resulting in poor electrical performance of the semiconductor structure.
Fig. 4 to 8 are schematic structural views corresponding to steps in another method for forming a semiconductor structure.
As shown in fig. 4 and 5, fig. 5 is a cross-sectional view of fig. 4 at aa, providing a substrate including a first device region I and a second device region II for forming devices of different conductivity types, the substrate including a substrate 50, a fin 30 on the substrate 50, and a gate structure 10 across the fin 30 and covering a portion of a top wall and a portion of a side wall of the fin 30, the gate structure 10 across the fin 30 of the first device region I and the second device region II and covering a portion of a top wall and a portion of a side wall of the fin 30; forming an offset sidewall layer 80 on the sidewall of the gate structure 10; after forming the offset sidewall layer 80, forming a first sidewall material layer 20 conformally covering the offset sidewall layer 80 and the gate structure 10; etching the fin portion 30 of the second device region II, and forming a first recess (not shown in the figure) in the fin portion 30; a first source drain doped layer (not shown) is formed in the first recess.
The forming step of the first source-drain doped layer includes: and forming a first epitaxial layer in the first groove by adopting a selective epitaxial growth process, and performing in-situ self-doping on the first epitaxial layer to form a first source-drain doped layer (not shown in the figure). In the in-situ self-doping process, a small amount of the first type ions 70 are easily formed on the sidewalls of the offset sidewall 80 and the sidewalls of the first sidewall material layer 20.
As shown in fig. 6, after the first source-drain doped layer is formed, a second sidewall material layer 40 is formed to conformally cover the gate structure 10, the offset sidewall 80, and the first sidewall material layer 20.
As shown in fig. 7, a shielding layer (not shown) is formed to cover the first device region I and expose the second device region II; in the second device region II, the fin portions 30 on both sides of the gate structure 10 are etched with the shielding layer as a mask, and a second recess (not shown in the drawing) is formed in the fin portions 30.
As shown in fig. 8, a second source-drain doped layer (not shown in the drawing) is formed in the second groove, and the forming method of the second source-drain doped layer is the same as the forming direction of the first source-drain doped layer, which is not described herein.
The step of forming the barrier layer generally includes: forming a shielding material layer covering the first device region I and the second device region II, patterning the shielding material layer, wherein the remaining shielding material layer located in the first device region I is used as a shielding layer, in order to avoid the influence of an overlay error in the actual patterning process, the shielding layer also generally covers the second device region II of a partial region, in the process of forming the second groove, the remaining second side wall material layer 40 is easy to expose the first type ions 70 (as shown in B) remained on the side wall of the first side wall material layer 20, correspondingly, in the step of forming the second source/drain doped layer, the first type ions 70 are easy to provide a good interface state for selective epitaxial growth, so that an impurity epitaxial layer 90 is easy to form on the side wall of the first side wall material layer 20 in the exposed part of the shielding layer, and in the subsequent process of forming an interlayer dielectric layer on the substrate 50 on two sides of the gate structure 10, the impurity epitaxial layer 90 is easy to block the formation of the interlayer dielectric layer, and thus the semiconductor structure is easy to exist in the easy to form a void.
In order to solve the technical problem, the embodiment of the invention provides a method for forming a semiconductor structure, wherein a protective layer is formed on the shielding layer and the side wall of the gate structure, and in the second device region, the second source-drain doped layer is generally formed by adopting a selective epitaxial growth process, and the protective layer enables the side wall of the gate structure and the first source-drain doped layer in the shielding layer to be difficult to expose.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 9 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 9 and 10, fig. 10 is a top view of fig. 9, providing a substrate comprising a first device region I for forming a first type transistor and a second device region II for forming a second type transistor, the substrate comprising a substrate 100, a channel structure 101 separated from the substrate 100, the channel structure 101 extending in the same direction as the intersection of the first device region I and the second device region II, and a gate structure 102 crossing the channel structure 101, the gate structure 102 covering a portion of the top wall and a portion of the side wall of the channel structure 101.
In this embodiment, the first device region I is a PMOS (Positive CHANNEL METAL Oxide Semiconductor) device region, and the second device region II is an NMOS (NEGATIVE CHANNEL METAL Oxide Semiconductor) device region. In other embodiments, the first device region may also be an NMOS device region, and the second device region may also be a PMOS device region.
The substrate 100 provides a process platform for the subsequent formation of semiconductor structures. In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The semiconductor structure formed in this embodiment is exemplified by a fin field effect transistor (FinFET). Correspondingly, the channel structure 101 is a fin. In other embodiments, the semiconductor structure formed is a fully-enclosed transistor (GAA), and correspondingly, the channel structure is a stacked structure including a sacrificial layer and a channel layer on the sacrificial layer.
In this embodiment, the material of the channel structure 101 is silicon. In other embodiments, the material of the channel structure may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the gate structure 102 is a dummy gate structure, and occupies a process space for forming a metal gate structure later.
In this embodiment, the gate structure 102 is a stacked structure. Specifically, the gate structure 102 includes a gate oxide layer (not shown) and a gate layer (not shown) on the gate oxide layer.
In this embodiment, the gate oxide layer is made of silicon oxide, and the gate layer is made of polysilicon.
It should be noted that, the extending direction of the gate structure 102 is perpendicular to the extending direction at the junction of the first device region I and the second device region II.
In the step of providing a substrate, a protective sidewall layer 104 is also formed on the sidewalls of the gate structure 102.
The protection sidewall layer 104 is used for defining the formation regions of the subsequent first source-drain doped layer and the second source-drain doped layer, and protecting the sidewall of the gate structure 102 during the formation of the semiconductor structure.
In this embodiment, the material of the protection sidewall layer 104 is a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9). The protection sidewall layer 104 is used to reduce the capacitive coupling effect of the gate structure 102 and the first source-drain doped layer and the second source-drain doped layer, thereby improving the electrical performance of the semiconductor structure.
In this embodiment, the materials for protecting the sidewall layer 104 include: carbon doped SiN or oxygen doped SiN. In other embodiments, the material for protecting the sidewall layer includes: siON, siBCN, or SiCN.
The substrate further comprises: an isolation structure 103 is located on the substrate 100 at the side of the channel structure 101, the isolation structure 103 covers part of the sidewall of the channel structure 101, and the top surface of the isolation structure 103 is lower than the top surface of the channel structure 101. The isolation structures 103 are used to electrically isolate the respective channel structures 101 from one another.
In this embodiment, the material of the isolation structure 103 is a dielectric material. Specifically, the material of the isolation structure 103 includes one or more of silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation structure 103 includes silicon oxide.
Isolation structures 103 are formed prior to forming gate structures 102.
The step of providing a substrate further comprises: a first sidewall material layer (not shown) is formed to cover the first device region I and the second device region II.
The first sidewall material layer and the protection sidewall layer 104 together define a formation region of a first source-drain doped layer formed later, and in a process of forming the first source-drain doped layer in the channel structure 101 at two sides of the gate structure 102 later, the first sidewall material layer can make the protection sidewall layer 104 not easily damaged.
Specifically, the material of the first side wall material layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron nitride carbon silicon. In this embodiment, the material of the first sidewall material layer includes silicon nitride. The silicon nitride has higher hardness and density, so that the first side wall material layer is not easy to be mistakenly etched in the subsequent process, and a growth interface is not easy to be provided by the silicon nitride in the subsequent process of forming the first epitaxial layer through a selective epitaxial growth process, so that the formed semiconductor structure is not easy to have the problems of bridging and the like.
In this embodiment, the first sidewall material layer is formed using an atomic layer deposition process (Atomic layer deposition, ALD). An atomic layer deposition process is selected, so that the uniformity of the thickness of the first side wall material layer is improved, and the thickness of the first side wall material layer can be accurately controlled; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the first side wall material layer is correspondingly improved. In other embodiments, the first sidewall material layer may also be formed using a chemical vapor deposition process (Chemical Vapor Deposition, CVD) or a low-pressure furnace process.
Referring to fig. 11 and 12, fig. 12 is a top view of fig. 11, and a first source-drain doped layer 107 is formed in the channel structure 101 at both sides of the gate structure 102 of the first device region I.
In operation of the semiconductor structure, the first source-drain doped layer 107 is configured to provide stress to the channel in the first device region I, and to increase the mobility of carriers in the channel.
In this embodiment, the first device region I is used to form PMOS. In operation of the semiconductor structure, the first source drain doped layer 107 applies compressive stress (compression stress) to the channel under the gate structure, which can improve hole mobility. Specifically, the material of the first source-drain doped layer 107 is P-type ion doped silicon germanium or silicon. Specifically, the P-type ions include one or more of B, ga and In.
In other embodiments, the first source-drain doped layer is used as the source and drain of the NMOS. When the semiconductor structure works, the first source-drain doping layer applies tensile stress (TENSILE STRESS) to a channel below the gate structure, and the tensile channel can improve the migration rate of electrons. Specifically, the material of the first source-drain doped layer is silicon carbide doped with N-type ions, silicon phosphide or silicon. Specifically, the N-type ions include one or more of P, as and Sb.
Specifically, the step of forming the first source-drain doped layer 107 includes: forming a first groove (not shown) in the channel structure at both sides of the gate structure 102 in the first device region I; a first epitaxial layer is formed in the first groove by adopting a selective epitaxial growth process, and ion doping is performed on the first epitaxial layer to form a first source-drain doped layer 107.
The first groove provides space for forming a first source-drain doped layer.
The step of forming the first groove includes: forming a first shielding layer (not shown) on the substrate, wherein the first shielding layer covers the substrate positioned in the second device region II and exposes the substrate positioned in the first device region; and etching the channel structures 101 at two sides of the gate structure 102 by taking the first shielding layer as a mask to form the first groove.
Specifically, the first shielding layer exposes the channel structures 101 on both sides of the gate structure 102 of the first device region I, and the first grooves are formed in the channel structures 101 on both sides of the gate structure 102.
The step of forming the first groove includes: forming a first shielding layer (not shown) on the substrate, wherein the first shielding layer covers the substrate and the gate structure 102 in the second device region II, and exposes the channel structures 101 on two sides of the gate structure 102 in the first device region I; and etching the channel structure 101 by taking the first shielding layer and the first side wall material layer as masks to form the first groove.
Specifically, the first shielding layer exposes the channel structures 101 on both sides of the gate structure 102 of the first device region I, and the first grooves are formed in the channel structures 101 on both sides of the gate structure 102.
In this embodiment, the material of the first shielding layer is a material that is easy to be removed, and in the subsequent process of removing the first shielding layer, damage to the substrate and the gate structure 102 is not easy to occur.
In this embodiment, the channel structures 101 on both sides of the gate structure 102 are etched by using a dry etching process, and a first groove is formed in the channel structures 101 on both sides of the gate structure 102. The dry etching process has the characteristic of anisotropic etching, has good etching profile controllability, is favorable for enabling the appearance of the first groove to meet the process requirement, and is favorable for accurately controlling the depth of the first groove.
The method for forming the semiconductor structure further comprises the following steps: after the first recess is formed, the first shielding layer is removed before the first source-drain doped layer 107 is formed.
In this embodiment, an ashing process is used to remove the first shielding layer.
It should be noted that, in the process of forming the first recess, in the first device region I, the first sidewall material layer on the sidewall of the gate structure 102 is easily etched and removed, and the remaining first sidewall material layer located in the second device region II is used as the first sidewall layer 108.
In this embodiment, a selective epitaxial growth process (SELECTIVE EPITAXY GROWTH, SEG) is used to form a first epitaxial layer (not shown in the figure) in the first recess, and the first epitaxial layer is ion doped to form the first source-drain doped layer 107. The first epitaxial layer is formed through a selective epitaxial growth process, and has high film purity, few growth defects and high formation quality, so that the performance of the semiconductor structure is optimized.
In this embodiment, the first epitaxial layer is ion doped by an in-situ self-doping process to form the first source-drain doped layer 107. By adopting the in-situ self-doping mode, uniformity of doping ion concentration in the first source-drain doped layer 107 is improved, and quality and performance of the first source-drain doped layer 107 are improved. In other embodiments, after the first epitaxial layer is formed, ion implantation may be used to perform ion doping on the first epitaxial layer to form a first source-drain doped layer.
It should be noted that, in the process of performing ion doping on the first epitaxial layer by using the in-situ self-doping process, P-type ions are easily doped on the sidewall of the gate structure 102.
Referring to fig. 13 and 14, a blocking layer is formed on the first source drain doping layer 107 and exposes the second device region II.
The shielding layer is used for protecting the first source-drain doped layer 107 from being damaged in the process of forming the second groove in the second device region II.
In this embodiment, the shielding layer that is located on the first source-drain doped layer 107 and exposes the second device region II is used as the second shielding layer 108.
In this embodiment, the material of the second shielding layer 108 is a material that is easy to be removed, and in the subsequent process of removing the second shielding layer 108, damage to the substrate and the gate structure 102 is not easy to occur.
Specifically, the second shielding layer 108 includes an organic material layer 1081, a hard mask layer 1082 on the organic material layer 1081, a bottom anti-reflective coating 1083 on the hard mask layer 1082, and a photoresist layer 1084 on the bottom anti-reflective coating 1083.
In this embodiment, the material of the organic material layer 1081 includes ODL (organic dielectriclayer ) material, photoresist, spin On Carbon (SOC) layer, DUO (Deep UV Light Absorbing Oxide, deep ultraviolet light absorbing oxide) material, or APF (ADVANCED PATTERNING FILM ) material.
In this embodiment, the material of the hard mask layer 1082 includes silicon oxide or silicon nitride.
The method for forming the semiconductor structure further comprises the following steps: after the first source-drain doped layer 107 is formed, before the second shielding layer is formed, a sidewall material layer covering the substrate of the first device region I and the second device region II is formed.
In this embodiment, the sidewall material layer formed after the first source/drain doped layer 107 is formed is used as the second sidewall material layer 106.
The second sidewall material layer 106, the protection sidewall layer 104 and the subsequently formed protection layer together define a subsequently formed formation region of the second source-drain doped layer, and in a process of subsequently forming the second source-drain doped layer in the channel structure 101 at two sides of the gate structure 102, the second sidewall material layer 106 can make the protection sidewall layer 104 not easily damaged.
Specifically, the material of the second sidewall material layer 106 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron nitride carbon silicon. In this embodiment, the material of the second sidewall material layer 106 includes silicon nitride. The silicon nitride has higher hardness and density, so that the second side wall material layer 106 is not easy to be etched by mistake in the subsequent process, and the silicon nitride is not easy to provide a growth interface in the subsequent process of forming the second epitaxial layer through a selective epitaxial growth process, so that the formed semiconductor structure is not easy to have the problems of bridging and the like.
In this embodiment, an atomic layer deposition process (Atomic layer deposition, ALD) is used to form the second sidewall material layer 106. In other embodiments, the second sidewall material layer may also be formed by a chemical vapor deposition process or a low-pressure furnace tube process.
It should be noted that, correspondingly, the second shielding layer 108 is formed on the second sidewall material layer 106.
Referring to fig. 15 and 16, a protective layer 109 (shown in fig. 16) is formed on sidewalls of the second shielding layer 108 and sidewalls of the gate structure 102.
In the second device region II, the second source/drain doped layer is generally formed by a selective epitaxial growth process, and the protective layer 109 makes the sidewall of the gate structure 102 and the first source/drain doped layer 107 in the second shielding layer 108 not easy to be exposed, so that the protective layer 109 can make the sidewall of the gate structure 102 and the first source/drain doped layer 107 in the second shielding layer 108 not have an epitaxial growth basis in the epitaxial growth process, and an impurity epitaxial layer is not easy to be formed on the gate structure 102 at the junction of the first device region I and the second device region II and on the first source/drain doped layer 107, which can reduce bridging risk caused by the impurity epitaxial layer, reduce the probability of leakage current of the semiconductor structure, and is beneficial to optimizing the electrical performance of the semiconductor structure.
The protective layer 109 is preferably not too thick or too thin. If the protective layer 109 is too thick, the process time required for forming the protective layer 109 is too long, so that the formation efficiency of the semiconductor structure is not easy to be improved; the channel structure 101 is a thin and high structure, and if the protective layer 109 is too thick, the protective layer 109 is also prone to squeeze the channel structure 101, and the protective layer 109 is prone to bending or deformation, resulting in poor electrical performance of the semiconductor structure. If the protective layer 109 is too thin, in the subsequent process of forming the second source-drain doped layer in the second device region II, the protective layer 109 may not well protect the gate structure 102 and the second shielding layer 108, which may easily cause exposure of the sidewall of the gate structure 102 and the first source-drain doped layer 107 in the second shielding layer 108, and an impurity doped layer may easily be formed on the sidewall of the gate structure 102 and the sidewall of the second shielding layer 108, and the impurity epitaxial layer may easily cause a bridging problem, and the semiconductor structure may easily have leakage current, which is not beneficial to optimizing the electrical performance of the semiconductor structure. In this embodiment, the thickness of the protective layer 109 isTo the point of
The step of forming the protective layer 109 includes: a layer of conformal capping protection material 110 (shown in fig. 15) over the second masking layer 108 and the substrate of the second device region II; after the protective material layer 110 is formed, the protective material layer 110 on both sides of the gate structure 102 of the second device region II and the channel structure 101 with a partial thickness are etched, a groove is formed in the channel structure 101, and the remaining protective material layer 110 serves as the protective layer 109.
In this embodiment, the protective material layer 110 is formed by an atomic layer deposition process. An atomic layer deposition process is selected, so that the uniformity of the thickness of the protective material layer 110 is improved, and the thickness of the protective material layer 110 can be accurately controlled; in addition, the gap filling performance and the step coverage of the atomic layer deposition process are good, and the conformal coverage capability of the protective material layer 110 is correspondingly improved. In other embodiments, the protective material layer may also be formed using a chemical vapor deposition process.
Specifically, in this embodiment, the groove in the channel structure 101 in the second device region II is used as the second groove 111, and the second groove 111 provides a process space for forming the second source-drain doped layer later.
In this embodiment, during the process of etching the protective material layer 110 and the channel structure 101 with partial thickness on both sides of the gate structure 102 of the second device region II, the second sidewall material layer 106 is also etched, and the second recess 111 is surrounded by the second sidewall material layer 106 and the channel structure 101.
In the process of etching the second sidewall material layer 106 of the second device region II, the etching difficulty of the protective material layer 110 is greater than the etching difficulty of the second sidewall material layer 106. In addition, in the subsequent step of forming the second epitaxial layer by the selective epitaxial growth process, the protective layer 109 is not easy to provide a good growth interface, and accordingly, an impurity epitaxial layer is not easy to be formed.
Thus, the material of the protective layer 109 includes one or more of silicon oxide, silicon oxynitride, silicon carbide nitride, boron nitride silicon, and boron carbon nitride silicon. In this embodiment, the material of the protective layer 109 includes silicon oxide. The silicon oxide has higher process compatibility, and is also a material with common process and lower cost, so that the difficulty and cost of the process are reduced by selecting the silicon oxide.
In this embodiment, the second shielding layer 108 is used as a mask, and a dry etching process is used to etch the protective material layer 110 and a portion of the thickness of the channel structure 101 on two sides of the gate structure 102 of the second device region II, so as to form a second groove 111 in the channel structure 101. The anisotropic etching characteristic and the better etching profile control are achieved, the appearance of the second groove 111 can meet the process requirement, the dry etching process is beneficial to accurately controlling the removal thickness of the channel structure 101, and damage to other film structures is reduced. And by changing the etching gas, the protective material layer 110, the second side wall material layer and the channel structure 101 can be etched in the same etching equipment, so that the process steps are simplified.
In this embodiment, a dry etching process is used, and in the process of forming the second recess 111, the etching gas includes HF, HBr, and CF 4.
It should be noted that, in the process of forming the second recess 111, the second sidewall material layer 106 exposed by the second shielding layer 108 is easily etched and removed.
In the step of forming the protective layer 109, the protective layer 109 is further formed on the second sidewall material layer 106 on the sidewall of the channel structure 101 in the second device region II.
The method for forming the semiconductor structure further comprises the following steps: after the second recess 111 is formed, the second shielding layer 108 is removed.
The second shielding layer 108 is made of an organic material, and after the second groove 111 is formed, the second shielding layer 108 is removed, so that the second shielding layer 108 is not easy to pollute a machine.
In this embodiment, an ashing process is used to remove the second shielding layer 108.
Referring to fig. 17, a second source-drain doped layer 112 is formed in the channel structure 101 of the second device region II, the second source-drain doped layer 112 and the first source-drain doped layer 107 being different in conductivity type.
During operation of the semiconductor structure, the second source-drain doped layer 112 is configured to provide stress to the channel in the second device region II, thereby increasing the mobility of carriers in the channel.
In this embodiment, the second device region II is used to form an NMOS. After the gate structure 102 is replaced with a metal gate structure, the second source-drain doped layer 112 applies a tensile stress to the channel under the metal gate structure during operation of the semiconductor structure, and the tensile stress may improve the electron mobility. Specifically, the material of the second source-drain doped layer 112 is silicon carbide doped with N-type ions, silicon phosphide or silicon. Specifically, the N-type ions include one or more of P, as and Sb.
In other embodiments, the second device region II may also be used to form a PMOS, where the first source-drain doped layer applies compressive stress to the channel under the metal gate structure during operation of the semiconductor structure, and the compressive channel may improve hole mobility. Specifically, the material of the second source-drain doped layer is silicon germanium or silicon doped with P-type ions. Specifically, the P-type ions include one or more of B, ga and In.
In the process of forming the second epitaxial layer by epitaxial growth, the protection layer 109 makes the sidewall of the gate structure 102 and the first source-drain doped layer 107 in the second shielding layer 108 not have the basis of epitaxial growth, so that an impurity epitaxial layer is not easy to form on the gate structure 102 and the first source-drain doped layer 107 at the junction of the first device region I and the second device region II, bridging risk caused by the impurity epitaxial layer can be reduced, probability of leakage current of the semiconductor structure is reduced, and optimization of electrical performance of the semiconductor structure is facilitated.
Correspondingly, referring to fig. 18, the embodiment of the invention further provides a semiconductor structure.
The semiconductor structure includes: a substrate 200, the substrate 200 comprising a first device region I for forming a first type transistor and a second device region II for forming a second type transistor; a channel structure 201, which is separated on the substrate 200, wherein the extending direction of the channel structure 201 is the same as the extending direction of the junction of the first device region I and the second device region II; a gate structure (not shown) that spans the channel structure 201 and covers a portion of the top wall and a portion of the side walls of the channel structure 201; a first source-drain doped layer 207 located in the channel structure 201 at two sides of the gate structure of the first device region I; a shielding layer 208 located in the first device region I, where the shielding layer 208 covers the gate structure, the first source-drain doped layer 207, and the channel structure 201 of the first device region I; and a protective layer 209 on the sidewall of the shielding layer 208 and the sidewall of the gate structure.
In the semiconductor structure provided in this embodiment of the present invention, the protection layer 209 is located on the sidewall of the shielding layer 208 and on the sidewall of the gate structure, and then a second source-drain doped layer is formed in the channel structure 201 at two sides of the gate structure in the second device region II, where the second source-drain doped layer is usually formed by a selective epitaxial growth process, and the protection layer 209 makes the sidewall of the gate structure and the first source-drain doped layer 207 in the shielding layer 208 not easy to be exposed, so that in the epitaxial growth process, the protection layer 209 can make the sidewall of the gate structure and the first source-drain doped layer 207 in the shielding layer 208 not have an epitaxial growth basis, and an impurity epitaxial layer is not easy to be formed on the first source-drain doped layer 207 at the junction of the first device region I and the second device region II, which can reduce the bridging risk caused by the impurity epitaxial layer, reduce the probability of the leakage current of the semiconductor structure, and is favorable to optimize the electrical performance of the semiconductor structure.
In this embodiment, the first device region I is a PMOS device region, and the second device region II is an NMOS device region. In other embodiments, the first device region I may also be an NMOS device region, and the second device region II may also be a PMOS device region.
The substrate 200 provides a process platform for the subsequent formation of semiconductor structures. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, a fin field effect transistor (FinFET) is taken as an example of the semiconductor structure. Accordingly, the channel structure 201 is a fin. In other embodiments, the semiconductor structure formed is a fully-enclosed transistor (GAA), and correspondingly, the channel structure is a stacked structure including a sacrificial layer and a channel layer on the sacrificial layer.
In this embodiment, the material of the channel structure 201 is silicon. In other embodiments, the material of the channel structure may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the gate structure is a dummy gate structure, and occupies a process space for forming a metal gate structure later.
In this embodiment, the gate structure is a stacked structure. Specifically, the gate structure includes a gate oxide layer (not shown) and a gate layer (not shown) on the gate oxide layer.
In this embodiment, the gate oxide layer is made of silicon oxide, and the gate layer is made of polysilicon.
It should be noted that, the extending direction of the gate structure is perpendicular to the extending direction of the junction of the first device region I and the second device region II.
The semiconductor structure further includes: and a protective sidewall layer (not shown) on the sidewalls of the gate structure.
The protection sidewall layer is used to define the forming regions of the first source-drain doped layer 207 and the second source-drain doped layer formed later.
In this embodiment, the material for protecting the sidewall layer is a low-k dielectric material. The protection side wall layer is used for reducing the capacitive coupling effect between the subsequent metal gate structure and the first source-drain doped layer 207 and the capacitive coupling effect between the metal gate structure and the second source-drain doped layer, so that the electrical performance of the semiconductor structure is improved.
In this embodiment, the material for protecting the sidewall layer includes: carbon doped SiN or oxygen doped SiN. In other embodiments, the material for protecting the sidewall layer includes: siON, siBCN, or SiCN.
The substrate further comprises: and an isolation structure 203 on the substrate 200 at a side of the channel structure 201, the isolation structure 203 covering a portion of the sidewall of the channel structure 201, a top surface of the isolation structure 203 being lower than a top surface of the channel structure 201. The isolation structures 203 are used to electrically isolate the individual channel structures 201 from each other.
In this embodiment, the material of the isolation structure 203 is a dielectric material. Specifically, the material of the isolation structure 203 includes one or more of silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation structure 203 includes silicon oxide.
The first source-drain doped layer 207 is used to provide stress to the channel in the first device region I during operation of the semiconductor structure, and to increase the mobility of carriers in the channel.
In this embodiment, the first device region I is used to form PMOS. In operation of the semiconductor structure, the first source drain doped layer 207 applies compressive stress to the channel under the metal gate structure, which can improve hole mobility. Specifically, the material of the first source-drain doped layer 207 is P-type ion doped silicon germanium or silicon. Specifically, the P-type ions include one or more of B, ga and In.
In other embodiments, the first source-drain doped layer is used as the source and drain of the NMOS. When the semiconductor structure works, the first source-drain doped layer applies tensile stress to a channel below the metal gate structure, and the tensile channel can improve the migration rate of electrons. Specifically, the material of the first source-drain doped layer is silicon carbide doped with N-type ions, silicon phosphide or silicon. Specifically, the N-type ions include one or more of P, as and Sb.
The shielding layer 208 is used to protect the first source-drain doped layer 207 from damage during the process of forming the second recess 211 in the second device region II.
In this embodiment, the material of the shielding layer 208 is a material that is easy to be removed, and in the subsequent process of removing the shielding layer 208, damage to the substrate and the gate structure is not easy to occur.
Specifically, the shielding layer 208 includes an organic material layer 2081, a hard mask layer 2082 on the organic material layer 2081, a bottom anti-reflective coating layer 2083 on the hard mask layer 2082, and a photoresist layer 2084 on the bottom anti-reflective coating layer 2083.
In this embodiment, the material of the organic material layer 2081 includes ODL (organic dielectriclayer ) material, photoresist, spin On Carbon (SOC) layer, DUO (DeepUVLight Absorbing Oxide, deep ultraviolet light absorbing oxide) material, or APF (ADVANCED PATTERNING FILM ) material.
In this embodiment, the material of the hard mask layer 2082 includes silicon oxide or silicon nitride.
Specifically, the material of the protective layer 209 includes one or more of silicon oxide, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron carbon nitride silicon. In this embodiment, the material of the protective layer 209 includes silicon oxide. The silicon oxide has higher process compatibility, and is also a material with common process and lower cost, so that the difficulty and cost of the process are reduced by selecting the silicon oxide.
The protective layer 209 is not too thick or too thin. If the protective layer 209 is too thick, the process time required for forming the protective layer 209 is too long, so that the formation efficiency of the semiconductor structure is not easily improved; the channel structure 201 is a thin and high structure, if the protective layer 209 is too thick, the protective layer 209 is also easy to squeeze the channel structure 201, and the protective layer 209 is easy to bend or deform, resulting in poor electrical performance of the semiconductor structure. If the protective layer 209 is too thin, in the process of forming the second source-drain doped layer in the second device region II, the protective layer 209 cannot well protect the gate structure and the shielding layer 208, which easily results in exposure of the sidewall of the gate structure and the first source-drain doped layer 207 in the shielding layer 208, an impurity doped layer is easily formed on the sidewall of the gate structure and the sidewall of the second shielding layer 208, and the impurity epitaxial layer easily causes a bridging risk, and leakage current easily occurs in the semiconductor structure, which is unfavorable for optimizing the electrical performance of the semiconductor structure. In this embodiment, the thickness of the protective layer 209 isTo/>
In the first region I, the sidewall material layer 206 is further located between the isolation structure 203 and the shielding layer 208, between the channel structure 201 and the shielding layer 208, between the first source/drain doped layer 207 and the gate structure, and between the gate structure and the shielding layer 208.
Note that the protective layer 209 is further located on the sidewall material layer 206 of the sidewall of the channel structure 201 in the second device region II.
The semiconductor structure further includes: and the grooves are positioned in the channel structures 201 at two sides of the gate structure in the second device region II.
In this embodiment, the grooves in the channel structure 201 on both sides of the gate structure in the second region II are used as the second grooves 211. The second recess 211 provides a process space for forming a second source-drain doped layer later.
The semiconductor structure further includes: and a sidewall material layer 206, which is located between the protection layer 209 and the channel structure 201, between the protection layer 209 and the gate structure, and the first source-drain doped layer 207 and the shielding layer 208.
The sidewall material layer 206 is used to protect the protective sidewall layer from being damaged.
The side wall material layer 206 and the protective layer 209 have an etching selectivity ratio, specifically, the etching difficulty of the side wall material layer 206 is smaller than that of the protective layer 209, so that in the process of etching the channel structures 201 on two sides of the gate structure in the second device region II to form the second groove 211, the protective layer 209 protects the side wall of the shielding layer 208 and the side wall of the gate structure, and further, the first source drain doped layer 207 is not easy to expose, doped ions formed on the side wall of the gate structure are not easy to expose, and in the process of forming the second epitaxial layer through a selective epitaxial growth process, impurity epitaxial layers are not easy to form on the first source drain doped layer 207 and the side wall of the gate structure, thereby reducing the bridging probability.
Specifically, the material of the sidewall material layer 206 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron nitride carbon silicon. In this embodiment, the material of the sidewall material layer 206 includes silicon nitride. The silicon nitride has higher hardness and density, so that the side wall material layer 206 is not easy to be etched by mistake in the subsequent process, and the silicon nitride is not easy to provide a growth interface in the subsequent process of forming the first epitaxial layer through the selective epitaxial growth process, so that the formed semiconductor structure is not easy to have the problems of bridging and the like.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
Providing a substrate, wherein the substrate comprises a first device region and a second device region, the first device region is used for forming a first type transistor, the second device region is used for forming a second type transistor, the substrate comprises a substrate and a channel structure which is separated on the substrate, the extending direction of the channel structure is the same as the extending direction of the junction of the first device region and the second device region, the substrate further comprises a grid structure which spans the channel structure, and the grid structure covers part of the top wall and part of the side wall of the channel structure;
forming a first source-drain doping layer in the channel structure at two sides of the gate structure of the first device region;
forming a shielding layer which is positioned on the first source-drain doping layer and exposes the second device region;
forming a protective layer on the side wall of the shielding layer and the side wall of the grid structure, wherein the protective layer prevents the side wall of the grid structure and the first source-drain doped layer in the shielding layer from being exposed;
And forming a second source-drain doping layer in the channel structure of the second device region, wherein the conductivity types of the second source-drain doping layer and the first source-drain doping layer are different.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming a protective layer comprises:
Conformally covering a protective material layer on the shielding layer and the substrate of the second device region;
And after the protective material layer is formed, etching the protective material layer on two sides of the gate structure of the second device region and the channel structure with partial thickness, forming a groove in the channel structure, and taking the rest of the protective material layer as the protective layer.
3. The method of claim 2, wherein the protective material layer is formed using an atomic layer deposition process or a chemical vapor deposition process.
4. The method of forming a semiconductor structure according to claim 1, wherein the protective layer has a thickness ofTo/>
5. The method of forming a semiconductor structure of claim 1, wherein the material of the protective layer comprises one or more of silicon oxide, silicon oxynitride, silicon carbide nitride, boron nitride silicon, and boron carbon nitride silicon.
6. The method of forming a semiconductor structure of claim 2, further comprising: forming a side wall material layer of the substrate covering the first device region and the second device region after forming the first source-drain doped layer and before forming the shielding layer;
In the step of forming the protective material layer, the protective material layer is formed on the shielding layer and the side wall material layer of the second device region;
And in the process of forming the groove, the side wall material layer of the second device region is also etched, and the groove is surrounded by the side wall material layer and the channel structure.
7. The method of claim 6, wherein the difficulty of etching the protective material layer is greater than the difficulty of etching the sidewall material layer in the second device region.
8. The method of forming a semiconductor structure of claim 2, wherein a recess is formed in said channel structure using a dry etching process with a masking layer as a mask.
9. The method of claim 8, wherein the etching gas comprises HF, HBr, and CF 4 during the forming of the recess using a dry etching process.
10. The method of forming a semiconductor structure of claim 1, wherein the forming of the second source drain doped layer comprises: and forming an epitaxial layer by adopting a selective epitaxial growth process, and carrying out in-situ doping on the epitaxial layer to form the second source-drain doped layer.
11. The method of forming a semiconductor structure of claim 1, wherein in the step of providing the substrate, the channel structure is a fin;
or the channel structure is a channel stack comprising a sacrificial layer and a channel layer on the sacrificial layer.
12. The method of forming a semiconductor structure of claim 1, wherein In the step of forming the first source-drain doped layer, one or more of B, ga and In are doped In the first source-drain doped layer;
in the step of forming the second source-drain doped layer, P, as is doped in the second source-drain doped layer
And one or more of Sb;
Or alternatively
In the step of forming the first source-drain doped layer, P, as is doped in the first source-drain doped layer
And one or more of Sb;
In the step of forming the second source-drain doped layer, B, ga is doped in the second source-drain doped layer
And one or more of In.
13. A semiconductor structure, comprising:
a substrate comprising a first device region for forming a first type transistor and a second device region for forming a second type transistor;
The channel structure is separated on the substrate, and the extending direction of the channel structure is the same as the extending direction of the junction of the first device region and the second device region;
A gate structure crossing the channel structure and covering a portion of a top wall and a portion of a side wall of the channel structure; the first source-drain doped layer is positioned in the channel structure at two sides of the grid structure of the first device region;
The shielding layer is positioned in the first device region and covers the grid structure, the first source drain doping layer and the channel structure of the first device region;
The protective layer is positioned on the side wall of the shielding layer and the side wall of the grid structure, and the protective layer enables the side wall of the grid structure and the first source-drain doped layer in the shielding layer not to be exposed.
14. The semiconductor structure of claim 13, wherein the material of the protective layer comprises: one or more of silicon oxide, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron carbon nitride silicon.
15. The semiconductor structure of claim 13, wherein the protective layer has a thickness ofTo/>
16. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: and the side wall material layer is positioned between the protective layer and the channel structure, between the protective layer and the grid structure and between the first source-drain doping layer and the shielding layer.
17. The semiconductor structure of claim 16, wherein the sidewall material layer and the protective layer have an etch selectivity.
18. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: and the grooves are positioned in the channel structures at two sides of the grid structure in the second device region.
19. The semiconductor structure of claim 13, wherein the channel structure is a fin;
Or alternatively
The channel structure is a channel stack including a sacrificial layer and a channel layer on the sacrificial layer.
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