CN104103589A - Method for manufacturing transistor - Google Patents
Method for manufacturing transistor Download PDFInfo
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- CN104103589A CN104103589A CN201310124029.6A CN201310124029A CN104103589A CN 104103589 A CN104103589 A CN 104103589A CN 201310124029 A CN201310124029 A CN 201310124029A CN 104103589 A CN104103589 A CN 104103589A
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 238000005530 etching Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 43
- 230000008569 process Effects 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 161
- 239000000463 material Substances 0.000 claims description 35
- 239000011241 protective layer Substances 0.000 claims description 35
- 238000005516 engineering process Methods 0.000 claims description 14
- 229920000642 polymer Polymers 0.000 claims description 13
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 239000003595 mist Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229920000058 polyacrylate Polymers 0.000 claims description 5
- CERQOIWHTDAKMF-UHFFFAOYSA-M methacrylate group Chemical group C(C(=C)C)(=O)[O-] CERQOIWHTDAKMF-UHFFFAOYSA-M 0.000 claims description 4
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 26
- 238000011049 filling Methods 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 230000007797 corrosion Effects 0.000 description 8
- 238000005260 corrosion Methods 0.000 description 8
- UHOVQNZJYSORNB-UHFFFAOYSA-N Benzene Chemical compound C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 2
- MWPLVEDNUUSJAV-UHFFFAOYSA-N anthracene Chemical compound C1=CC=CC2=CC3=CC=CC=C3C=C21 MWPLVEDNUUSJAV-UHFFFAOYSA-N 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010297 mechanical methods and process Methods 0.000 description 2
- 230000005226 mechanical processes and functions Effects 0.000 description 2
- 125000001997 phenyl group Chemical group [H]C1=C([H])C([H])=C(*)C([H])=C1[H] 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- -1 silicon nitrides Chemical class 0.000 description 2
- 238000012800 visualization Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JYVXNLLUYHCIIH-UHFFFAOYSA-N (+/-)-mevalonolactone Natural products CC1(O)CCOC(=O)C1 JYVXNLLUYHCIIH-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JYVXNLLUYHCIIH-ZCFIWIBFSA-N R-mevalonolactone, (-)- Chemical compound C[C@@]1(O)CCOC(=O)C1 JYVXNLLUYHCIIH-ZCFIWIBFSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229940057061 mevalonolactone Drugs 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a method for manufacturing a transistor. The method includes forming a Barc layer and a patterned photoresist layer in sequence above a semiconductor substrate and a gate structure on the semiconductor substrate, and before forming the Barc layer above the gate structure located on the semiconductor substrate, forming a protection layer above the gate structure first. Afterwards, in a process of using the photoresist layer as a mask and using gas containing HBr as etching gas to remove the Barc layer, the photoresist layer is guaranteed not to be exceesively corroded, so that the size of an opening on the photoresist layer is guaranteed, and a hard mask layer and side walls of the gate structure can be effectively prevented from being damaged by excessive etching of the etching gas containing HBr, thereby protecting a gate electrode layer of the gate structure, and ensuring smooth proceeding of subsequent manufacturing processes of a semiconductor device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, especially relate to a kind of transistor fabrication process.
Background technology
Along with the development of ic manufacturing technology, the characteristic size of integrated circuit constantly reduces, in order to ensure device size reduce semiconductor device itself is not caused damage, the operating voltage of integrated circuit is also constantly done corresponding reducing.In order to ensure that integrated circuit keeps good performance under less operating voltage, in ic manufacturing process, conventionally adopt strained silicon technology (Strained Silicon) on nmos pass transistor, to form the channel region with tensile stress, on PMOS transistor, form the channel region of compression, increase nmos pass transistor and the transistorized carrier mobility of PMOS, thereby increase drive current, the response speed of raising integrated circuit.In strained silicon technology, embedded stress transistor is the focus of strained silicon technology application.
In the transistorized stressor layers forming process of existing PMOS, shown in figure 1, comprise step: first provide the Semiconductor substrate 100 that comprises PMOS region and territory, nmos area, and form grid structure 10 on described Semiconductor substrate 100 surfaces, described grid structure 10 comprises the gate dielectric layer 17 that is positioned in described Semiconductor substrate 100, is positioned at the gate electrode layer 11 on described gate dielectric layer 17 surfaces, hard mask layer 12 on described gate electrode layer 11 surfaces, and forms side wall 13 on the sidewall of described gate dielectric layer 17 and gate electrode layer 11;
Afterwards, with photoresist 14(in conjunction with reference to figure 2) cover Semiconductor substrate 100, remove the photoresist in PMOS region by photoetching process; And to be retained in the photoresist in territory, described nmos area, and described side wall 13 and hard mask layer 12 are mask, first adopt to be dry-etched in Semiconductor substrate 100 and form opening, with wet etching, described longitudinal opening inner transverse is extended again, form the filling opening 15 of " Σ " shape, for filling as SiGe iso-stress material, strengthen the transistorized compression of PMOS of follow-up formation;
Finally, the stress material in described filling opening 15 carries out ion doping, forms source area and drain region.
But, in actual mechanical process, form in described Semiconductor substrate PMOS region, there will be shift phenomenon for the opening of filling stress material, the opening that is only positioned at PMOS region originally can extend to territory, nmos area.In the semiconductor device of 28nm is manufactured, the span d that described photoresist 14 openings increase can reach 30～40nm(with reference to shown in figure 2).In the opening to PMOS region, fill stress material and form after stressor layers, changed the transistorized carrier mobility of PMOS.This phenomenon directly affects the performance of the final semiconductor device forming.
Thereby, in the each transistorized stressor layers manufacture process of semiconductor, how to guarantee to offer in Semiconductor substrate for filling position and the size of opening of stress material, be the problem that those skilled in the art need solution badly.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistor fabrication process, in stressor layers preparation process, guarantees opening size and position for filling stress material.
For addressing the above problem, the invention provides a kind of transistor fabrication process, comprising:
In described Semiconductor substrate, form grid structure, described Semiconductor substrate comprises PMOS region and territory, nmos area;
On the surface of described Semiconductor substrate and grid structure, form from the bottom to top the first mask layer, protective layer, Barc layer;
Cover photoresist layer in territory, described nmos area;
Taking described photoresist layer as mask, adopt contain HBr mist etching described in Barc layer, to remove the Barc layer that is positioned at described PMOS region;
Continue taking described photoresist layer as mask, protective layer and the first mask layer described in etching successively, until expose described Semiconductor substrate;
Taking described grid structure as Semiconductor substrate described in mask etching, in the Semiconductor substrate of described grid structure both sides, form opening;
In described opening, fill stress material, form stressor layers.
Alternatively, the material of described protective layer is Al
2o
3, ZrO
2, HfO
2, La
2o
3, Ta
2o
5, TiO
2or SiO
2.
Alternatively, the technique that forms described protective layer is CVD technique.
Alternatively, the material of described protective layer is SiO
2, the technique that forms described protective layer is O
2plasma gas oxidation technology.
Alternatively, described O
2plasma gas oxidation technology is: be 10mTorr～500mTorr at pressure, power is under 5100～21000W condition, continues to pass into and comprise O with 50～500sccm flow
2plasma gas 30～600 seconds, be oxidized described the first mask layer.
Alternatively, the thickness of described protective layer is 10～50 dusts.
Alternatively, described mist also comprises O
2, wherein, HBr and O
2flow-rate ratio be 40:1～200:1.
Alternatively, the thickness of described the first mask layer is 5～20 nanometers.
Alternatively, the material of described stressor layers is SiGe.
Alternatively, also comprise: forming before described the first mask layer, form layer of oxide layer on the surface of described Semiconductor substrate and grid structure.
Alternatively, the material of described photoresist layer is methacrylate polymers or styrene polymer.
Alternatively, the material of described Barc layer is polyacrylate polymers.
Compared with prior art, technical scheme of the present invention has the following advantages:
In transistor fabrication process, the etching gas etching Barc layer that employing contains HBr, while removing Barc layer, the etching gas that contains HBr can excessive corrosion photoresist layer, thereby can guarantee follow-up position and the size that is formed for the opening of filling stress material in Semiconductor substrate.And; be covered in the protective layer forming between first mask layer on Semiconductor substrate and grid structure surface and described Barc layer; etching barrier layer while can be used as Barc layer described in etching; avoid the first mask layer described in overetch; to protect the grid structure of described the first mask layer and described the first mask layer below, guarantee carrying out smoothly of semiconductor device subsequent manufacturing processes.
Brief description of the drawings
Fig. 1 is a kind of CMOS transistor arrangement schematic diagram of the prior art;
Fig. 2 be COMS transistor in Fig. 1 along A-A to sectional structure schematic diagram;
Fig. 3 to Fig. 9 is the schematic diagram of the transistor fabrication process that provides of one embodiment of the invention.
Embodiment
As described in background, in the transistorized stressor layers forming process of PMOS of strained silicon technology application, the opening for filling stress material forming in described Semiconductor substrate PMOS region can be offset to territory, nmos area, make the PMOS stressor layers forming extend to territory, nmos area, thereby changed the transistorized carrier mobility of PMOS, and the performance of the final semiconductor device forming of impact.Analyze its reason, inventor thinks: shown in figure 1, in above-mentioned PMOS stressor layers forming process, before photoresist 14 depositions, can first above grid structure 10 and Semiconductor substrate 100, deposit one deck bottom antireflective coating (Bottom Anti-reflective coating is called for short Barc) 16 to reduce standing wave effect and to strengthen graphic correlation degree.But existing Barc layer mostly is polyacrylate polymers, is difficult to remove by visualization way, often needs to adopt and contain SO
2and O
2mist as dry etching agent remove described Barc layer 16.But SO
2can react with the composition such as O atom in photoresist, cause the photoresist corrosion that is covered in territory, nmos area, and further decompose, make the increase of photoresist opening.Make the opening that is only formed at PMOS region originally extend to territory, nmos area, and cause the PMOS stressor layers of follow-up formation to expand to territory, nmos area.
In order to overcome above-mentioned defect, study discovery through inventor, the etching gas that comprises HBr of employing, effectively etching Barc layer, and can not cause much corrosion to photoresist layer.Analyze its reason, inventor thinks, in the etching gas etching Barc layer process that employing contains HBr, HBr can react with photoresist, and on the contact-making surface of photoresist, form one deck Stability Analysis of Structures ground passivation layer, further react with photoresist thereby effectively suppress etching gas, avoid the excessive corrosion of photoresist.Can guarantee so follow-uply taking photoresist and grid structure as mask, in the Semiconductor substrate of grid structure both sides, form, for filling the opening size of stress material.
But in actual mechanical process; inventor further finds; the etching gas that contains HBr can not cause excessive corrosion to photoresist layer; but can cause the hard mask layer damage that is covered in gate electrode layer top forming with materials such as silicon nitrides; and affect hard mask layer and side wall in integrated circuit subsequent manufacturing processes and, for the protection of gate electrode layer, even stain the gate electrode layer in grid structure.
For above-mentioned defect, the invention provides a kind of transistor fabrication process.Below Barc layer, form protective layer, using the etching barrier layer as described Barc layer, comprise that in employing the etching gas of HBr carries out in Semiconductor substrate etching process, described protective layer can effectively protect the hard mask layer of Barc layer below to avoid corrosion.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 3 to Fig. 9 is the structure chart of the transistor fabrication process that provides of one embodiment of the invention.Shown in figure 3, provide Semiconductor substrate 100.Described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or amorphous silicon, can be also silicon, germanium, GaAs or silicon Germanium compound.Described Semiconductor substrate 100 can have the structure such as silicon on epitaxial loayer or insulating barrier, and existing Semiconductor substrate all can be used as Semiconductor substrate of the present invention, will not enumerate at this.
In described Semiconductor substrate 100, be formed with isolation structure and be isolated the active area that structure is isolated, (isolation structure can isolation structure of shallow trench (Shallow Trench Isolation, STI).As shown in the figure, the active area of described Semiconductor substrate 100 comprises territory, nmos area and PMOS region, and wherein, territory, described nmos area and PMOS region are isolated by sti structure (not shown).
Continue with reference to shown in figure 3, form grid structure 20 in the surfaces of active regions of described Semiconductor substrate 100.Described grid structure 20 is common gate structure, and it is across PMOS region and territory, nmos area, and the follow-up nmos pass transistor forming on territory, described nmos area and PMOS region and PMOS transistor share a grid.Particularly, described grid structure 20 comprises the gate electrode hard mask layer 24 that is positioned at the gate dielectric layer 21 on described Semiconductor substrate 100 surfaces, the gate electrode layer 22 that is positioned at described gate dielectric layer 21 tops, gate electrode layer 22 tops, and is positioned at the side wall 23 of the both sides formation of Semiconductor substrate 100 surfaces, described gate dielectric layer 21 and gate electrode layer 22.
Particularly, the material of described gate dielectric layer 21 is the contour k dielectric material of silicon oxynitride or hafnium oxide; The material of described gate electrode layer 22 is polysilicon, metal or other electric conducting materials.The material of described gate electrode hard mask layer 24 can silicon nitride or silicon oxynitride.In this enforcement, the material of described gate electrode hard mask layer 24 is preferably silicon nitride.The material of described side wall 23 can be silica, silicon nitride or silicon oxynitride, and described side wall 23 can be the sidewall structure of multiple-level stack, and in the present embodiment, described side wall 23 is preferably the silicon nitride side wall of single layer structure.The formation method of described grid structure 20 can form technique with reference to existing grid structure, does not repeat them here.
Shown in figure 4, on the surface of described Semiconductor substrate 100 and described grid structure 20, form successively from the bottom to top the first mask layer 25, protective layer 26.Described the first mask layer 25 is preferably silicon nitride layer, and it can adopt chemical vapor deposition (CVD) technique to form, and its thickness is preferably 5～20nm.Described protective layer 26 is protective oxide film, and thickness is 10～50 dusts.In the present embodiment, described protective layer 26 is preferably to adopt and comprises and contain O
2plasma gas be oxidized described the first mask layer 25 and form silicon dioxide layer.
Particularly, described silicon dioxide layer 26 forms step and is:
Be 10mTorr～500mTorr at pressure, power is 5100～21000W, continues with 50～500sccm(mark condition milliliter per minute) flow passes into and comprises O
2plasma gas 30～600 seconds, to be oxidized described the first mask layer 25, thereby form described silicon dioxide layer 26 above described the first mask layer 25.Now, described silicon oxide layer 26 thickness of formation are 10～50 dusts.Remove in described Barc layer 27 process in subsequent etching; described protective layer 26 can be used as the etching barrier layer of Barc layer 27; after etching Barc layer 27; described protective layer 26 can stop etching gas further to infiltrate described the first mask layer 25; avoid the corrosion of described the first mask layer 25 and gate electrode hard mask layer 24; to protect described gate electrode layer 22, and guarantee carrying out smoothly of the follow-up manufacturing process of semiconductor.
Certainly, the material of described protective layer 26 is not limited to SiO
2, and it forms technique and is not limited to above-mentioned employing plasma gas and is oxidized described the first mask layer 25.As described in protective layer 26 can be also to adopt such as CVD and ALD(Atomic layer deposition, ald) etc. technique, what above described the first mask layer 25, form comprises Al
2o
3, ZrO
2, HfO
2, La
2o
3, Ta
2o
5, TiO
2or SiO
2for the protective layer 26 of material.
In conjunction with reference to shown in figure 5, above described protective layer 26, cover one deck Barc layer 27 and photoresist layer.And through polishing, developing process, remove the photoresist layer that is covered in described PMOS region, retain the photoresist layer 28 that is covered in territory, described nmos area.In the present embodiment, described photoresist layer 28 is preferably the styrene polymer of 248nm, or the methacrylate polymer without " C=C " and benzene ring structure of 193nm, as 2-methyl-2 adamantanol propylene acid alcohol, mevalonolactone acrylate.Described Barec layer 27 covers described grid structure 20 completely, and its surface is flat end face structure.Described Barc layer 27 is preferably polyacrylate polymers, and in described polyacrylate polymers, can be added with and can absorb the material that absorbs corresponding wavelength in follow-up lithography development process, the material of this absorbing wavelength is corresponding with follow-up photoresist character used.As, if photoresist adopts the styrene polymer of 248nm, described Barc layer 27 preferably adds as anthracene, naphthalene, and many benzene material such as derivative is with absorbing wavelength; If described photoresist layer 27 adopts the methacrylate polymer without " C=C " and phenyl ring of 193nm, in described Barc layer 27, can add single benzene material with absorbing wavelength.Described Barc layer 27 can adopt CVD technique to form.Described photoresist layer 28 is carried out in developing process, described Barc layer 27 can effectively prevent " standing wave phenomena ", thereby increases lithographic process window, improve the wide control of photoetching bar.
In conjunction with reference to shown in figure 6 and Fig. 7, wherein, Fig. 6 be in Fig. 5 B-B to generalized section, Fig. 7 be in Fig. 5 C-C to generalized section.Taking described photoresist layer 28 as mask, etching is positioned at the Barc layer 27 in described PMOS region.In existing semiconductor fabrication, described Barc layer 27 cannot be removed by visualization way, thereby after the described photoresist layer in PMOS region is removed, exposes described Barc layer 27.In the present embodiment, preferably adopt and contain HBr and O
2gas be etching gas, etching is removed described Barc layer, until expose the described protective layer 26 that is positioned at described Semiconductor substrate 100 tops.
Its concrete technology can be: be that 2mTorr～50mTorr, power are 100～1000W at pressure, adopt under polarization voltage 50V～500V condition, HBr flow is 2059sccm, O
2flow is under 10～500sccm condition, removes exposed described Barc layer 27.In practical operation, inventor's discovery, described protective layer 26 can effectively stop HBr and O
2the further etching of etching gas and infiltration, described protective layer 26 has effectively been protected the first mask layer 25 that is positioned at described protective layer 26 belows.
Described etching gas also can further comprise Cl
2, NF
3, SF
6, CF
4with one or more in CO, thereby further improve the etching effect for Semiconductor substrate 100.Wherein, preferably, Cl
2, NF
3, SF
6, CF
4with the flow-rate ratio of CO total amount and HBr be 0.1～2:5.Within the scope of this, both can improve the etch rate of etching gas for described Barc layer 27, the described photoresist layer 28 of simultaneously guaranteeing to be covered in territory, nmos area can excessive corrosion.In addition, when Barc, can pass into He and/or Ar described in described etching gas etching simultaneously.Wherein, He, as diluent gas, can effectively improve the etching uniformity, thereby improves stability and the fail safe of etching technics, and Ar can effectively increase the bombarding energy of etching gas to improve dry etching speed.Preferably, the total amount of He and Ar and the volume ratio of HBr are 10～30:1.
After described Barc layer 27 is removed, detect through scanning electron microscopy, the photoresist layer 28 that is covered in territory, nmos area with the quantity not sufficient 10nm(that PMOS region adjacent is corroded is, in Fig. 2, the numerical value of d is less than 10nm), this deviation can meet the error requirements of the semiconductor device of critical size 28nm completely.And described the first mask layer 25 structures are without damage.This result proves, the described protective layer 26 of described the first mask layer 25 tops effectively stops and comprises HBr and O
2the further etching of etching gas to the first mask layer 25.
Afterwards, continue taking described photoresist layer 28 as mask, adopt and comprise CF
4, CHF
3, O
2, Ar, one or more gas etchings in He are removed described protective layer 26, expose described the first mask layer 25.
It should be noted that; in this example; described Barc layer 27 and protective layer 26 all adopt dry etching mode to remove; in actual use procedure; also can only on described Barc layer 27 and protective layer 26, form corresponding opening for the follow-up patterns of openings forming in described Semiconductor substrate 100, to ensure follow-up carrying out smoothly for Semiconductor substrate 100 etchings.Only otherwise the performance of the final semiconductor device forming of impact, described Barc layer 27 and the protective layer 26 of part may be retained in the semiconductor device of final formation, and these are all those skilled in the art's common technology, do not repeat them here.
In conjunction with reference to shown in figure 8, taking described side wall 23, gate electrode hard mask layer 24 and the photoresist layer 28 that is covered in territory, nmos area as mask, adopt and comprise CF
4, CHF
3, CH
2f
2, CHF
3, O
2, He, one or more gases in Ar, as etching gas, are removed described the first mask layer 25 until expose Semiconductor substrate 20 with anisotropic etch process.It should be noted that, now, based on anisotropic etch process characteristic, described in etching, the first mask layer 25 exposes behind described Semiconductor substrate 100 surfaces, on described side wall 23, also retain described first mask layer 32 of a little thickness, the side wall 33 that formation thickens, with respect to original side wall 23, described side wall 33 is in the coverage having expanded in described Semiconductor substrate 100.After completing the etching technics of described the first mask layer 25, again taking described side wall 33, gate electrode hard mask layer 24 and the photoresist layer 28 that is covered in territory, nmos area as Semiconductor substrate 100 described in mask dry etching, in described Semiconductor substrate 100, be positioned at the formation opening 29 of the both sides of the side wall 33 of the grid structure 20 in PMOS region.In the present embodiment, the linearly shape of opening 29 forming by dry etching, and in subsequent technique, shown in figure 9, can further adopt opening 29 described in the further etching of wet-etching technology, be the filling opening 30 of " Σ " shape to form, and to interior fillings of filling opening 30 SiGe of described " Σ " shape, formation PMOS stressor layers.
Wherein, in Semiconductor substrate described in dry etching 20, to form in opening 29 processes, after complete described the first mask layer 25 of etching, side wall 33 after thickening can effectively regulate the drift angle of filling opening 30 of " Σ " shape of follow-up formation with respect to the position of grid, thereby the filling opening 30 of avoiding etching to form excessively gos deep into grid, electric leakage is caused in below.
In another embodiment of the present invention, before described the first mask layer 25 forms, first above described Semiconductor substrate 20, form one deck oxide skin(coating), described oxide skin(coating) can form by thermal oxidation technology or CVD technique, using the etching barrier layer as the first mask layer 25 described in etching.In the etching technics of described the first mask layer 25, effectively avoid the damage for described gate electrode hard mask layer 24.
Wherein, the gate electrode hard mask layer 24 of described the first mask layer 25 and described grid structure 10 all adopts silicon nitride as material, and described oxide layer materials between described the first mask layer 25 and gate electrode hard mask layer 24 is preferably SiO
2.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. a transistor fabrication process, is characterized in that, comprising:
In described Semiconductor substrate, form grid structure, described Semiconductor substrate comprises PMOS region and territory, nmos area;
On the surface of described Semiconductor substrate and grid structure, form from the bottom to top the first mask layer, protective layer, Barc layer;
Cover photoresist layer in territory, described nmos area;
Taking described photoresist layer as mask, adopt contain HBr mist etching described in Barc layer, to remove the Barc layer that is positioned at described PMOS region;
Continue taking described photoresist layer as mask, protective layer and the first mask layer described in etching successively, until expose described Semiconductor substrate;
Taking described grid structure as Semiconductor substrate described in mask etching, in the Semiconductor substrate of described grid structure both sides, form opening;
In described opening, fill stress material, form stressor layers.
2. transistor fabrication process as claimed in claim 1, is characterized in that, the material of described protective layer is Al
2o
3, ZrO
2, HfO
2, La
2o
3, Ta
2o
5, TiO
2or SiO
2.
3. transistor fabrication process as claimed in claim 2, is characterized in that, the technique that forms described protective layer is CVD technique.
4. transistor fabrication process as claimed in claim 2, is characterized in that, the material of described protective layer is SiO
2, the technique that forms described protective layer is O
2plasma gas oxidation technology.
5. transistor fabrication process as claimed in claim 4, is characterized in that, described O
2plasma gas oxidation technology is: be 10mTorr～500mTorr at pressure, power is under 5100～21000W condition, continues to pass into and comprise O with 50～500sccm flow
2plasma gas 30～600 seconds, be oxidized described the first mask layer.
6. the transistor fabrication process as described in claim 1～5 any one, is characterized in that, the thickness of described protective layer is 10～50 dusts.
7. transistor fabrication process as claimed in claim 1, is characterized in that, described mist also comprises O
2, wherein, HBr and O
2flow-rate ratio be 40:1～200:1.
8. transistor fabrication process as claimed in claim 1, is characterized in that, the thickness of described the first mask layer is 5～20 nanometers.
9. transistor fabrication process as claimed in claim 1, is characterized in that, the material of described stressor layers is SiGe.
10. transistor fabrication process as claimed in claim 1, is characterized in that, also comprises: forming before described the first mask layer, form layer of oxide layer on the surface of described Semiconductor substrate and grid structure.
11. transistor fabrication process as claimed in claim 1, is characterized in that, the material of described photoresist layer is methacrylate polymers or styrene polymer.
12. transistor fabrication process as claimed in claim 1, is characterized in that, the material of described Barc layer is polyacrylate polymers.
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