CN101577252A - Shallow trench isolation structure and method for forming same - Google Patents
Shallow trench isolation structure and method for forming same Download PDFInfo
- Publication number
- CN101577252A CN101577252A CNA2008101059331A CN200810105933A CN101577252A CN 101577252 A CN101577252 A CN 101577252A CN A2008101059331 A CNA2008101059331 A CN A2008101059331A CN 200810105933 A CN200810105933 A CN 200810105933A CN 101577252 A CN101577252 A CN 101577252A
- Authority
- CN
- China
- Prior art keywords
- area
- stressor layers
- groove
- isolation structure
- fleet plough
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Element Separation (AREA)
Abstract
The invention relates to a method for forming a shallow trench isolation structure. The method comprises the following steps: a semiconductor substrate is provided, wherein the semiconductor substrate is provided with a first area and a second area which are respectively provided with at least one trench; a first stress layer is respectively formed on the first area and the second area, and the first stress layer at least fills the trench in the first area; the first stress layer of the second area is removed; a second stress layer is respectively formed on the first stress layer of the first area and the second area, and the second stress layer at least fills the trench in the second area; the second stress layer and the first stress layer are flatted; and the first stress layer and the second stress layers on the first area and the second area are removed. The invention also provides the shallow trench isolation structure and can simultaneously improve the performance for forming an NMOS and a PMOS.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of fleet plough groove isolation structure and forming method thereof.
Background technology
Fleet plough groove isolation structure by form groove on the Semiconductor substrate and in groove the technology of filled media material form.Publication number be the Chinese patent application file of CN 1649122A disclose a kind of shallow trench isolation from manufacture method.Fig. 1 to Fig. 5 be the disclosed shallow trench isolation of described Chinese patent application file from each step corresponding structure generalized section of manufacture method.
As shown in Figure 1, Semiconductor substrate 12 is provided, on described Semiconductor substrate 12, form pad oxide 12A, then on described pad oxide 12A, form silicon nitride layer as first hard mask layer 14, on described first hard mask layer 14, form the second hard mask layer 14B, on the described second hard mask layer 14B, form photoresist layer 16A, and the described photoresist layer 16A of patterning forms the opening 16B that the described second hard mask layer 14B is exposed in the bottom.
As shown in Figure 2, the second hard mask layer 14B, first hard mask layer 14 and the pad oxide 12A of the described opening 16B of etching bottom form opening 16C, and the surface of described Semiconductor substrate 12 is exposed in the bottom of described opening 16C.
As shown in Figure 3, remove described photoresist layer 16A, the Semiconductor substrate 12 of the described opening 16C of etching bottom forms groove 18 in described Semiconductor substrate 12, and forms cushion oxide layer 20 on described groove 18 surfaces.
As shown in Figure 4, filling oxide layer 22 in described groove 18 is removed the described second hard mask layer 14B by cmp then and is gone up unnecessary oxide layer 22 and the described second hard mask layer 14B.
As shown in Figure 5, first hard mask layer 14 as described in removing by wet etching (as phosphoric acid), and remove described pad oxide 12A by hydrofluoric acid solution.Promptly form fleet plough groove isolation structure.
In the manufacture method of described fleet plough groove isolation structure, the technology of filling oxide layer 22 is generally finished by chemical vapor deposition method, can cause oxide layer 22 to produce compression in deposition process.This compression helps to improve the performance of the PMOS device of formation, but can influence the performance of nmos device.Existing way is by the stress in the annealing process release oxide layer 22.
Yet,, be helpless to improve the performance of PMOS device though the stress in the release oxide layer 22 reduces the Effect on Performance to nmos device.
Summary of the invention
The invention provides a kind of fleet plough groove isolation structure and forming method thereof, can improve the performance of the NMOS and the PMOS device of formation simultaneously.
The formation method of a kind of fleet plough groove isolation structure provided by the invention comprises:
Semiconductor substrate is provided, and described Semiconductor substrate has first area and second area, and each has a groove at least in described first area and second area;
Form first stressor layers on described first area and second area, described first stressor layers is filled up the groove in the described first area at least;
Remove first stressor layers of second area;
Form second stressor layers with second area on first stressor layers of described first area, described second stressor layers is filled up the groove in the described second area at least;
Remove part second stressor layers and part first stressor layers by flatening process, keep second stressor layers in the groove of first stressor layers in the groove of described first area and second area;
Wherein, when described first area was used to form PMOS or nmos device, described first stressor layers was respectively compressive stress film or tensile stress film;
When described second area was used to form PMOS or nmos device, described second stressor layers was respectively compressive stress film or tensile stress film.
Optionally, the step of first stressor layers of removal second area is as follows:
Covering barrier layer on first stressor layers of described first area;
Etching is removed first stressor layers of described second area;
Remove described barrier layer.
Optionally, described first stressor layers is a silica.
Optionally, described etching is dry etching or wet etching.
Optionally, the etching gas of described dry etching is the gas of fluorine-containing or chlorine or bromine.
Optionally, the etching liquid of described wet etching is a hydrofluoric acid solution.
Optionally, form before first stressor layers, form pad silicon oxide layer in described flute surfaces.
Optionally, described first stressor layers is the compression silica, and its formation method is the high density plasma chemical vapor deposition method.
Optionally, described second stressor layers is the tensile stress silica, and its formation method is a thermal chemical vapor deposition method.
The present invention also provides a kind of formation method of fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has first area and second area, and each has a groove at least in described first area and second area;
On described first area and second area, form first stressor layers, the groove in the partially filled described first area of described first stressor layers;
Remove first stressor layers of second area;
Form second stressor layers with second area on first stressor layers of described first area, described second stressor layers is filled up the groove in the described second area at least;
Remove part second stressor layers and part first stressor layers by flatening process, keep second stressor layers in the groove of first stressor layers, second stressor layers and second area in the groove of described first area;
Wherein, when described first area was used to form PMOS or nmos device, described first stressor layers was respectively compressive stress film or tensile stress film;
When described second area was used to form PMOS or nmos device, described second stressor layers was respectively compressive stress film or tensile stress film.
Optionally, further comprise: before the planarization,
Remove second stressor layers on the described first area;
On second stressor layers of first stressor layers of described first area and second area, deposit first stressor layers once more, and fill up the groove of described first area at least.
Optionally, described first stressor layers is the compression silica, and second stressor layers is the tensile stress silica.
The present invention also provides a kind of formation method of fleet plough groove isolation structure, comprising:
A1, provide Semiconductor substrate, described Semiconductor substrate has first area and second area, and each has a groove at least in described first area and second area;
A2, on described first area and second area, form first stressor layers, the groove in the partially filled described first area of described first stressor layers;
First stressor layers of A3, removal second area;
A4, on first stressor layers of described first area and second area, form second stressor layers, the groove in the partially filled described second area of described second stressor layers;
A5, repeated execution of steps A2 to A4, when the groove of described first area and second area all is filled till;
A6, remove part second stressor layers and part first stressor layers, keep second stressor layers in the groove of first stressor layers in the groove of described first area and second area by flatening process;
Wherein, when described first area was used to form PMOS or nmos device, described first stressor layers was respectively compressive stress film or tensile stress film;
When described second area was used to form PMOS or nmos device, described second stressor layers was respectively compressive stress film or tensile stress film.
Optionally, described first stressor layers is the compression silica, and second stressor layers is the tensile stress silica.
The present invention also provides a kind of fleet plough groove isolation structure, comprising: the Semiconductor substrate with first area and second area; Each has a groove at least in described first area and second area; Also comprise:
First stressor layers that is arranged in the groove of described first area and fills up this groove; Second stressor layers that is arranged in the groove of described second area and fills up this groove;
Wherein, when described first area was used to form PMOS or nmos device, described first stressor layers was respectively compressive stress film or tensile stress film;
When described second area was used to form PMOS or nmos device, described second stressor layers was respectively compressive stress film or tensile stress film.
Optionally, described first stressor layers is the compression silica; Described second stressor layers is the tensile stress silica.
Compared with prior art, in the technique scheme has the following advantages:
By in the groove of the groove of first area and second area, filling the stressor layers of dissimilar stress respectively, when being respectively applied for when forming different MOS devices with second area in the first area, can autotelicly in groove, be filled with the stressor layers that helps improve this MOS device performance, thereby improve the performance of the device that forms.For example, when the first area is used to form PMOS, can in the groove of described first area, fill the compression rete, when second area is used to form NMOS, in the groove of described second area, fill the tensile stress rete; The tensile stress rete of described filling and compression rete and the fleet plough groove isolation structure that forms all help the raising of performance of the MOS device of its respective regions, and the performance of other regional MOS device are not exerted an influence;
One of them of technique scheme has advantage:
By changing the thickness of first stressor layers, changing this first stressor layers, thereby can change the performance of the device of formation to stress influence in the conducting channel of the device that forms; The method of the stress in a kind of conducting channel of the device of controlling formation by the thickness that changes first stressor layers is provided;
One of them of technique scheme has advantage:
In addition, be divided into multistep by filling and carry out, and reduce the thickness of each step deposition, can guarantee the compactness of the rete of filling groove first stressor layers and second stressor layers, help to improve the electrical stability of the fleet plough groove isolation structure of formation, improve the performance of the device that forms.
Description of drawings
Fig. 1 to Fig. 5 be the disclosed shallow trench isolation of described Chinese patent application file from each step corresponding structure generalized section of manufacture method;
Fig. 6 to Figure 17 is each step corresponding structure generalized section of first embodiment of fleet plough groove isolation structure formation method of the present invention;
Figure 18 to Figure 21 is each step corresponding structure generalized section of second embodiment of fleet plough groove isolation structure formation method of the present invention;
Figure 19 to Figure 26 is each step corresponding structure generalized section of the 3rd embodiment of fleet plough groove isolation structure formation method of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Embodiment one
Please refer to Fig. 9, Semiconductor substrate 100 has first area 102 and second area 202, has a groove 108 in described first area 102 at least, has a groove 208 in described second area 202 at least.
Among the embodiment therein, the technology that forms groove 108 and 208 is as follows:
Please refer to Fig. 6, at first, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon, described Semiconductor substrate 100 also can be a kind of in silicon Germanium compound, the silicon gallium compound, described Semiconductor substrate 100 can also comprise silicon on epitaxial loayer or the insulating barrier (Silicon On Insulator, SOI) structure.
Described Semiconductor substrate 100 has first area 102 and second area 202.Wherein, first area 102 is used to form PMOS, and second area is used to form NMOS.
Be formed with N trap (figure does not show) in described first area 102, it can form by ion implantation technology.Can also further carry out ion implantation technology and the resistance of adjusting threshold voltage to described N trap and wear ion implantation technology, repeat no more here.
Be formed with P trap (figure does not show) in described second area 202, it can form by ion implantation technology.Can also further carry out ion implantation technology and the resistance of adjusting threshold voltage to described P trap and wear ion implantation technology, repeat no more here.
In a further embodiment, pad oxide 300 also can form by the method for chemical vapour deposition (CVD).
In addition, before forming pad oxide 300, can clean,, strengthen the adhesion of pad oxide 300 on Semiconductor substrate 100 surfaces to remove impurity particle or other pollutant on described Semiconductor substrate 100 surfaces to Semiconductor substrate 100 surfaces.
Then, form hard mask layer 302 on described pad oxide 300, hard mask layer described in the present embodiment 302 is a silicon nitride.
The method that forms described silicon nitride can be chemical vapour deposition (CVD).
The hard mask of described hard mask layer 302 during on the one hand as etching groove in described Semiconductor substrate 100 is on the other hand as the layer that stops of the cmp planarization of the dielectric material of filling in groove.
In other embodiments, described hard mask layer can be a multilayer.
Please refer to Fig. 7, spin coating photoresist layer 303 on described hard mask layer 302, and in the photoresist layer of first area 102, form one first opening 104 at least by exposure imaging technology, in the photoresist layer of second area 202, form one second opening 204 at least.
Wherein, the surface of all exposing described hard mask layer 302, the bottom of described first opening 104 and second opening 204.
In other embodiments, before the described photoresist layer 303 of spin coating, can form the anti-reflecting layer (not shown) earlier on described hard mask layer 302, described anti-reflecting layer can be an inorganic material, for example silicon oxynitride, or organic material; And then form photoresist layer 303 on described anti-reflecting layer, and exposure imaging forms first opening 104 and second opening 204.
Then, the hard mask layer 302 and the pad oxide 300 of described first opening 104 of etching and second opening, 204 bottoms, 102 form the 3rd opening 106 in the first area, form the 4th opening 206, the surface that described Semiconductor substrate 100 is all exposed in the bottom of described the 3rd opening 106 and the 4th opening 206 at second area 202.Described etching is the anisotropic etching, for example is the plasma dry etching, and the etching gas of this plasma dry etching can be CF4.
Continue the Semiconductor substrate 100 of described the 3rd opening 106 of etching and the 4th opening 206 bottoms, in the first area 102 of described Semiconductor substrate 100, form groove 108, form groove 208 at second area 202, as shown in Figure 8.
Described groove 108 of etching and 208 method are the plasma dry etching, the etching gas that described plasma dry etching is selected for use will make the sidewall of described groove 108 and 208 comparatively smooth, has less silicon crystal lattice defective, and make the corner, bottom of described groove 108 and 208 comparatively level and smooth, described etching gas also will make described groove 108 and 208 sidewalls have the comparatively profile of inclination, for example can be 70 to 90 degree.The etching gas of described etching can be Cl
2Or the mist of HBr or HBr and other gas, for example can be HBr and O
2And Cl
2Mist, or HBr and NF
3Mist with He.The degree of depth of the groove 160 that etching forms is by the time control of etching.
After forming described groove 108 and 208, remove described photoresist layer 303, promptly form structure as shown in Figure 9.
Please refer to Figure 10, clean the surface of described groove 108 and 208, generate layings 110 and 210 with thermal oxidation method at described groove 108 and 208 surfaces then with hydrofluoric acid solution.
Wherein, cleaning by described hydrofluoric acid solution, can remove the natural oxidizing layer that described groove 108 and 208 surfaces generate, the laying 110 and 210 that helps forming has density comparatively uniformly, make described laying 110 and 210 as the comparatively stable interlayer of characteristic between the dielectric material of Semiconductor substrate 100 and filling in described groove 108 and 208, and increase adhesiveness between the two, reduce device leakage current in the Semiconductor substrate 100 when work.
In addition, described hydrofluoric acid solution cleans the part pad oxide 300 that also can remove described groove 108 and 208 top, make described pad oxide 300 sidewalls a little contraction be arranged to described hard mask layer 302 bottoms, thereby the corner of described groove 108 and 208 top is exposed, generate described laying 110 and at 210 o'clock carrying out thermal oxidation, can make the corner at the top of described groove 108 and 208 have comparatively level and smooth profile.Described level and smooth profile can reduce stress build up on the one hand, can reduce when device is worked charge carrier on the other hand and gather influence to opening feature.
Then, form first stressor layers 304 in described first area 102 and second area 202, wherein, described first stressor layers 304 is filled up the groove 108 in the described first area 102 at least.
Among the embodiment therein, described first stressor layers 304 is compression rete (compressive film), concrete, can be the compression silicon oxide layer, the method that forms described compression silicon oxide layer can be the high density plasma CVD method.
In a further embodiment, described first stressor layers 304 also can be tensile stress rete (tensile film), concrete, it can be the tensile stress silicon oxide layer, the method that forms this tensile stress silicon oxide layer is a thermal chemical vapor deposition method, for example, aumospheric pressure cvd method, Low Pressure Chemical Vapor Deposition etc.
After forming described first stressor layers 304, spin coating photoresist layer 306 on institute's first stressor layers 304 please refer to Figure 11.
Please refer to Figure 12, remove the photoresist layer 306 of described second area 202, first stressor layers, 304 surfaces of described second area 202 are exposed by exposure and developing process.
Please refer to Figure 13, remove first stressor layers 304 of described second area 202 by etching technics.Wherein, described etching technics can be dry etching or wet etching, perhaps dry method and the wet method etching technics that combines.When described first stressor layers 304 was stress (comprising tensile stress and compression) membranous layer of silicon oxide, the etching gas of dry etching can be the gas of fluorine-containing or chlorine or bromine; Wet etching can be a hydrofluoric acid solution.In dry method and wet method combined technology, the plasma with the gas of fluorine-containing or chlorine or bromine carried out dry etching earlier, cleans with hydrofluoric acid solution, thereby removes first stressor layers 304 of described second area 202 clean.
After removing first stressor layers 304 of described second area 202, etching is removed described photoresist layer 306, as shown in figure 14.The method of removing described photoresist layer 306 can be known oxygen gas plasma ashing.
Please refer to Figure 15, form laying 211 once more on groove 208 surfaces of described second area 202.Because when etching was removed described stressor layers 304, the plasma of dry etching and the etching solution of wet etching all can cause damage to 210 in the described groove 208, thereby need form laying once more.
Please refer to Figure 16, then, forming second stressor layers 308 on first stressor layers 304 of described first area 102 and on the hard mask layer 302 of second area 202, laying 211.
Wherein, described second stressor layers 308 is filled up the groove 208 of described second area 202 at least.
When described first stressor layers 304 was the compression rete, described second stressor layers 308 was the tensile stress rete.Concrete, this tensile stress rete is the tensile stress silicon oxide layer.The method that forms this tensile stress silicon oxide layer is a thermal chemical vapor deposition method, for example, and aumospheric pressure cvd method, Low Pressure Chemical Vapor Deposition etc.
When described first stressor layers 304 was the tensile stress rete, described second stressor layers 308 was the compression rete.Concrete, this compression rete is the compression silicon oxide layer.The method that forms described compression silicon oxide layer can be the high density plasma CVD method.
Please refer to Figure 17, carry out flatening process, remove above first stressor layers 304 and second stressor layers 308 in hard mask layer 302 surfaces of described first area 102 and second area 202.
Then, remove described hard mask layer 302 and cushion oxide layer 300 by wet etching, and keep second stressor layers 308 in the groove 208 of first stressor layers 304 in the groove 108 of described first area 102 and second area 202, form fleet plough groove isolation structure as shown in figure 12.
In the present embodiment, by in the groove 208 of the groove 108 of first area 102 and second area 202, filling the stressor layers of dissimilar stress respectively, when being respectively applied for when forming different MOS devices with second area in the first area, can autotelicly in groove, be filled with the stressor layers that helps improve this MOS device performance, thereby improve the performance of the device that forms.For example, when first area 102 is used to form PMOS, can in the groove 108 of described first area 102, fill the compression rete, when second area 202 is used to form NMOS, in the groove 208 of described second area 202, fill the tensile stress rete.The tensile stress rete of described filling and compression rete and the fleet plough groove isolation structure that forms all help the raising of performance of the MOS device of its respective regions, and the performance of other regional MOS device are not exerted an influence.
Embodiment two
Please refer to Fig. 9, Semiconductor substrate 100 is provided, Semiconductor substrate 100 has first area 102 and second area 202, has a groove 108 in described first area 102 at least, has a groove 208 in described second area 202 at least.
Among one of them embodiment, the technology that forms groove 108 and 208 repeats no more here with the technology that forms groove among the embodiment one.
Then, please refer to Figure 18, form first stressor layers 404 in described first area 102 and second area 202, wherein, the groove 108 in the described first stressor layers 404 partially filled described first areas.
Among the embodiment therein, described first stressor layers 404 is the compression rete, and is concrete, can be the compression silicon oxide layer, and the method that forms described compression silicon oxide layer can be a high density plasma CVD.
In a further embodiment, described first stressor layers 404 also can be the tensile stress rete, and is concrete, it can be the tensile stress silicon oxide layer, the method that forms this tensile stress silicon oxide layer is a thermal chemical vapor deposition method, for example, and aumospheric pressure cvd method, Low Pressure Chemical Vapor Deposition etc.
In this step, first stressor layers, 404 thickness are thin than first embodiment.
After forming described first stressor layers 404, remove first stressor layers 404 of described second area 202, please refer to Figure 19.
Among the embodiment therein, the step of first stressor layers 404 of removing described second area 202 is as follows: spin coating photoresist layer (not shown) on described first stressor layers 404; Remove the photoresist layer of described second area 202 by exposure and developing process; Remove first stressor layers 404 that is not covered by dry etching or wet etching by photoresist; Remove described photoresist layer.
Then, please refer to Figure 20, groove 208 surfaces at described second area 202 form laying 211 once more, because when etching is removed described stressor layers 404, the plasma of dry etching and the etching solution of wet etching all can cause damage to 210 in the described groove 208, thereby need form laying once more.Then, forming second stressor layers 408 on first stressor layers 404 of described first area 102 and on the hard mask layer 302 of second area 202, laying 211.
Wherein, described second stressor layers 408 is filled up the groove 208 of described second area 202 at least.
When described first stressor layers 404 was the compression rete, described second stressor layers 408 was the tensile stress rete.Concrete, this tensile stress rete is the tensile stress silicon oxide layer.The method that forms this tensile stress silicon oxide layer is a thermal chemical vapor deposition method, for example, and aumospheric pressure cvd method, Low Pressure Chemical Vapor Deposition etc.
When described first stressor layers 404 was the tensile stress rete, described second stressor layers 408 was the compression rete.Concrete, this compression rete is the compression silicon oxide layer.The method that forms described compression silicon oxide layer can be the high density plasma CVD method.
Then, carry out flatening process, remove above first stressor layers 404 and second stressor layers 408 in hard mask layer 302 surfaces of described first area 102 and second area 202.
Then, remove described hard mask layer 302 and cushion oxide layer 300 by wet etching, and keep second stressor layers 408 in the groove 208 of first stressor layers 404 in the groove 108 of described first area 102 and second area 202, form fleet plough groove isolation structure as shown in figure 21.
In other embodiments, before carrying out flatening process, can remove second stressor layers 408 of described first area 102 by selective etch, and deposit first stressor layers once more in described first area 102 and second area 202, first stressor layers of deposition is filled up the groove 108 of described first area 102 at least, and then the execution flatening process, repeat no more here.
In the present embodiment, by in the groove 208 of the groove 108 of first area 102 and second area 202, filling the stressor layers of dissimilar stress respectively, when being respectively applied for when forming different MOS devices with second area in the first area, can autotelicly in groove, be filled with the stressor layers that helps improve this MOS device performance, thereby improve the performance of the device that forms.For example, when first area 102 is used to form PMOS, can in the groove 108 of described first area 102, fill the compression rete, when second area 202 is used to form NMOS, in the groove 208 of described second area 202, fill the tensile stress rete.The tensile stress rete of described filling and compression rete and the fleet plough groove isolation structure that forms all help the raising of performance of the MOS device of its respective regions, and the performance of other regional MOS device are not exerted an influence.
In addition, in the present embodiment, change the thickness of first stressor layers, changing this first stressor layers, thereby can change the performance of the device of formation stress influence in the conducting channel of the device that forms; Present embodiment provides the method for the stress in a kind of conducting channel of the device of controlling formation by the thickness that changes first stressor layers.
Embodiment three
Please refer to Fig. 9, Semiconductor substrate 100 is provided, Semiconductor substrate 100 has first area 102 and second area 202, has a groove 108 in described first area 102 at least, has a groove 208 in described second area 202 at least.
Among one of them embodiment, the technology that forms groove 108 and 208 repeats no more here with the technology that forms groove among the embodiment one.
Then, please refer to Figure 22, form first stressor layers 504 in described first area 102 and second area 202, wherein, the groove 108 in the described first stressor layers 504 partially filled described first areas.
Among the embodiment therein, described first stressor layers 504 is the compression rete, and is concrete, can be the compression silicon oxide layer, and the method that forms described compression silicon oxide layer can be a high density plasma CVD.
In a further embodiment, described first stressor layers 504 also can be the tensile stress rete, and is concrete, can be the tensile stress silicon oxide layer, and the method that forms this tensile stress silicon oxide layer is a thermal chemical vapor deposition method.
In this step, first stressor layers, 504 thickness are thin than first embodiment.
After forming described first stressor layers 504, remove first stressor layers 504 of described second area 202, please refer to Figure 23.
Then, please refer to Figure 24, groove 208 surfaces at described second area 202 form laying 211 once more, because when etching is removed described stressor layers 504, the plasma of dry etching and the etching solution of wet etching all can cause damage to 210 in the described groove 208, thereby need form laying once more.
Then, forming second stressor layers 508 on first stressor layers 504 of described first area 102 and on the hard mask layer 302 of second area 202, laying 211.
Wherein, the groove 208 of described second stressor layers, 508 partially filled described second areas 202.
When described first stressor layers 504 was the compression rete, described second stressor layers 508 was the tensile stress rete.Concrete, this tensile stress rete is the tensile stress silicon oxide layer.The method that forms this tensile stress silicon oxide layer is a thermal chemical vapor deposition method.
When described first stressor layers 504 was the tensile stress rete, described second stressor layers 508 was the compression rete.Concrete, this compression rete is the compression silicon oxide layer.The method that forms described compression silicon oxide layer can be the high density plasma CVD method.
Please refer to Figure 25, remove second stressor layers 508 of described first area 102.
Then, repeat and above-mentioned 102 form the step that first stressor layers 504 and second area form second stressor layers 508, till the groove 206 of the groove 106 of described first area 102 and second area 202 is filled in the first area.
Carry out flatening process, remove above first stressor layers 404 and second stressor layers 408 in hard mask layer 302 surfaces of described first area 102 and second area 202.
Then, remove described hard mask layer 302 and cushion oxide layer 300 by wet etching, and keep second stressor layers 508 in the groove 208 of first stressor layers 504 in the groove 108 of described first area 102 and second area 202, form fleet plough groove isolation structure as shown in figure 26.
In the present embodiment, by in the groove 208 of the groove 108 of first area 102 and second area 202, filling the stressor layers of dissimilar stress respectively, when being respectively applied for when forming different MOS devices with second area in the first area, can autotelicly in groove, be filled with the stressor layers that helps improve this MOS device performance, thereby improve the performance of the device that forms.For example, when first area 102 is used to form PMOS, can in the groove 108 of described first area 102, fill the compression rete, when second area 202 is used to form NMOS, in the groove 208 of described second area 202, fill the tensile stress rete.The tensile stress rete of described filling and compression rete and the fleet plough groove isolation structure that forms all help the raising of performance of the MOS device of its respective regions, and the performance of other regional MOS device are not exerted an influence.
In addition, in the present embodiment, the filling of first stressor layers and second stressor layers is divided into multistep carries out, and reduce the thickness of each step deposition, can guarantee the compactness of the rete of filling groove, help to improve the electrical stability of the fleet plough groove isolation structure of formation, improve the performance of the device that forms.
The present invention also provides a kind of fleet plough groove isolation structure.Figure 17 is the cross-sectional view of the embodiment of fleet plough groove isolation structure of the present invention.
As shown in figure 17, described fleet plough groove isolation structure comprises the Semiconductor substrate 100 with first area 102 and second area 202, at least have a groove 108 in the first area 102 of described Semiconductor substrate 100, in the second area 202 of described Semiconductor substrate 100, have a groove 202 at least.
Wherein, be filled with first stressor layers 304 in the groove 108 of described first area 102, this first stressor layers 304 is filled up described groove 108; Be filled with second stressor layers 308 in the groove 208 of described second area 202, this second stressor layers 308 is filled up described groove 208.Between described groove 108 surfaces and described first stressor layers 304, also have laying 110, between described groove 208 and described second stressor layers 308, also have laying 211.
Described first stressor layers 304 is tensile stress rete or compression rete; Accordingly, described second stressor layers 308 is compression rete and tensile stress rete.
Among the embodiment therein, described first stressor layers 304 is the compression silicon oxide layer, and described second stressor layers 308 is the tensile stress silicon oxide layer.
In the fleet plough groove isolation structure of the present invention, in the groove 108 of first area 102 with in the groove 208 of second area 202, has different stress retes, for example, has first stressor layers 304 in the groove 108 of first area 102, has second stressor layers 308 in the groove 208 of second area 202, when 102 being respectively applied for when forming different MOS devices with second area 202 in the first area, can autotelicly in corresponding groove, be filled with the stressor layers that helps improve this MOS device performance, thereby improve the performance of the device that forms.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (16)
1, a kind of formation method of fleet plough groove isolation structure is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has first area and second area, and each has a groove at least in described first area and second area;
Form first stressor layers on described first area and second area, described first stressor layers is filled up the groove in the described first area at least;
Remove first stressor layers of second area;
Form second stressor layers with second area on first stressor layers of described first area, described second stressor layers is filled up the groove in the described second area at least;
Remove part second stressor layers and part first stressor layers by flatening process, keep second stressor layers in the groove of first stressor layers in the groove of described first area and second area;
Wherein, when described first area was used to form PMOS or nmos device, described first stressor layers was respectively compressive stress film or tensile stress film;
When described second area was used to form PMOS or nmos device, described second stressor layers was respectively compressive stress film or tensile stress film.
2, the formation method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that: the step of first stressor layers of removal second area is as follows:
Covering barrier layer on first stressor layers of described first area;
Etching is removed first stressor layers of described second area;
Remove described barrier layer.
3, the formation method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that: described first stressor layers is a silica.
4, the formation method of fleet plough groove isolation structure as claimed in claim 3 is characterized in that: described etching is dry etching or wet etching.
5, the formation method of fleet plough groove isolation structure as claimed in claim 4 is characterized in that: the etching gas of described dry etching is the gas of fluorine-containing or chlorine or bromine.
6, the formation method of fleet plough groove isolation structure as claimed in claim 5 is characterized in that: the etching liquid of described wet etching is a hydrofluoric acid solution.
7, the formation method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that: form before first stressor layers, form pad silicon oxide layer in described flute surfaces.
8, the formation method of fleet plough groove isolation structure as claimed in claim 4 is characterized in that: described first stressor layers is the compression silica, and its formation method is the high density plasma chemical vapor deposition method.
9, the formation method of fleet plough groove isolation structure as claimed in claim 8 is characterized in that: described second stressor layers is the tensile stress silica, and its formation method is a thermal chemical vapor deposition method.
10, a kind of formation method of fleet plough groove isolation structure is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has first area and second area, and each has a groove at least in described first area and second area;
On described first area and second area, form first stressor layers, the groove in the partially filled described first area of described first stressor layers;
Remove first stressor layers of second area;
Form second stressor layers with second area on first stressor layers of described first area, described second stressor layers is filled up the groove in the described second area at least;
Remove part second stressor layers and part first stressor layers by flatening process, keep second stressor layers in the groove of first stressor layers, second stressor layers and second area in the groove of described first area;
Wherein, when described first area was used to form PMOS or nmos device, described first stressor layers was respectively compressive stress film or tensile stress film;
When described second area was used to form PMOS or nmos device, described second stressor layers was respectively compressive stress film or tensile stress film.
11, the formation method of fleet plough groove isolation structure as claimed in claim 10 is characterized in that, further comprises: before the planarization,
Remove second stressor layers on the described first area;
On second stressor layers of first stressor layers of described first area and second area, deposit first stressor layers once more, and fill up the groove of described first area at least.
12, as the formation method of claim 10 or 11 described fleet plough groove isolation structures, it is characterized in that: described first stressor layers is the compression silica, and second stressor layers is the tensile stress silica.
13, a kind of formation method of fleet plough groove isolation structure is characterized in that, comprising:
A1, provide Semiconductor substrate, described Semiconductor substrate has first area and second area, and each has a groove at least in described first area and second area;
A2, on described first area and second area, form first stressor layers, the groove in the partially filled described first area of described first stressor layers;
First stressor layers of A3, removal second area;
A4, on first stressor layers of described first area and second area, form second stressor layers, the groove in the partially filled described second area of described second stressor layers;
A5, repeated execution of steps A2 to A4, when the groove of described first area and second area all is filled till;
A6, remove part second stressor layers and part first stressor layers, keep second stressor layers in the groove of first stressor layers in the groove of described first area and second area by flatening process;
Wherein, when described first area was used to form PMOS or nmos device, described first stressor layers was respectively compressive stress film or tensile stress film;
When described second area was used to form PMOS or nmos device, described second stressor layers was respectively compressive stress film or tensile stress film.
14, the formation method of fleet plough groove isolation structure as claimed in claim 13 is characterized in that: described first stressor layers is the compression silica, and second stressor layers is the tensile stress silica.
15, a kind of fleet plough groove isolation structure comprises: the Semiconductor substrate with first area and second area; Each has a groove at least in described first area and second area; It is characterized in that, also comprise:
First stressor layers that is arranged in the groove of described first area and fills up this groove; Second stressor layers that is arranged in the groove of described second area and fills up this groove;
Wherein, when described first area was used to form PMOS or nmos device, described first stressor layers was respectively compressive stress film or tensile stress film;
When described second area was used to form PMOS or nmos device, described second stressor layers was respectively compressive stress film or tensile stress film.
16, fleet plough groove isolation structure as claimed in claim 15 is characterized in that: described first stressor layers is the compression silica; Described second stressor layers is the tensile stress silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101059331A CN101577252B (en) | 2008-05-05 | 2008-05-05 | Shallow trench isolation structure and method for forming same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101059331A CN101577252B (en) | 2008-05-05 | 2008-05-05 | Shallow trench isolation structure and method for forming same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101577252A true CN101577252A (en) | 2009-11-11 |
| CN101577252B CN101577252B (en) | 2011-10-05 |
Family
ID=41272133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101059331A Active CN101577252B (en) | 2008-05-05 | 2008-05-05 | Shallow trench isolation structure and method for forming same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101577252B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543821A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolating structure |
| CN103871951A (en) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Channel filling method |
| CN104103589A (en) * | 2013-04-10 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing transistor |
| CN104517846A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN107393875A (en) * | 2016-04-25 | 2017-11-24 | 英飞凌科技股份有限公司 | The method for manufacturing semiconductor devices |
| CN107993982A (en) * | 2017-11-30 | 2018-05-04 | 上海华虹宏力半导体制造有限公司 | CMOS device and forming method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100230431B1 (en) * | 1997-07-25 | 1999-11-15 | 윤종용 | Method of forming trench isolation using two kinds of oxides films |
| US7288451B2 (en) * | 2005-03-01 | 2007-10-30 | International Business Machines Corporation | Method and structure for forming self-aligned, dual stress liner for CMOS devices |
-
2008
- 2008-05-05 CN CN2008101059331A patent/CN101577252B/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543821A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolating structure |
| CN102543821B (en) * | 2010-12-22 | 2014-08-06 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolating structure |
| CN103871951A (en) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Channel filling method |
| CN103871951B (en) * | 2012-12-18 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | Channel filling method |
| CN104103589A (en) * | 2013-04-10 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing transistor |
| CN104103589B (en) * | 2013-04-10 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of transistor fabrication process |
| CN104517846A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN107393875A (en) * | 2016-04-25 | 2017-11-24 | 英飞凌科技股份有限公司 | The method for manufacturing semiconductor devices |
| CN107993982A (en) * | 2017-11-30 | 2018-05-04 | 上海华虹宏力半导体制造有限公司 | CMOS device and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101577252B (en) | 2011-10-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI511234B (en) | Semiconductor structures and methods for forming isolation between fin structures of finfet devices | |
| CN101459116B (en) | Shallow groove isolation construction manufacturing method | |
| JP5230737B2 (en) | Method for manufacturing adjacent silicon fins of different heights | |
| CN100539069C (en) | Shallow trench isolation from manufacture method | |
| US8329547B2 (en) | Semiconductor process for etching a recess into a substrate by using an etchant that contains hydrogen peroxide | |
| CN101459115A (en) | Shallow groove isolation construction manufacturing method | |
| CN101577252B (en) | Shallow trench isolation structure and method for forming same | |
| WO2015089951A1 (en) | Method for preparing quasi soi source/drain field effect transistor device | |
| CN101770974A (en) | Method for fabricating shallow-trench isolation structure | |
| TW202009986A (en) | Semiconductor-on-insulator (SOI) substrate and method for forming same | |
| KR101205066B1 (en) | Method for isolation in semiconductor device | |
| JP4834304B2 (en) | Manufacturing method of semiconductor device | |
| CN108878361A (en) | Semiconductor devices and its manufacturing method | |
| CN103545185A (en) | Method of producing semiconductor device by pseudo-gate | |
| JP5506248B2 (en) | Method for forming triple gate of semiconductor device | |
| CN101740462A (en) | Manufacturing method of shallow trench isolation structure | |
| US8269307B2 (en) | Shallow trench isolation structure and method for forming the same | |
| CN103165461B (en) | Make the method for semiconductor device | |
| CN103531476A (en) | Manufacturing method for semiconductor device | |
| CN103594412A (en) | Manufacturing method of shallow trench isolation structure and shallow trench isolation structure | |
| CN103137467A (en) | Semiconductor manufacturing process for removing oxide layer | |
| CN104517884B (en) | A kind of method for making semiconductor devices | |
| CN103839792B (en) | Method, semi-conductor device manufacturing method | |
| CN109755172B (en) | Shallow trench isolation structure, semiconductor device and manufacturing method thereof | |
| KR100875170B1 (en) | Recess gate of semiconductor device and method for forming thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |