CN113745162A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN113745162A
CN113745162A CN202010473447.6A CN202010473447A CN113745162A CN 113745162 A CN113745162 A CN 113745162A CN 202010473447 A CN202010473447 A CN 202010473447A CN 113745162 A CN113745162 A CN 113745162A
Authority
CN
China
Prior art keywords
layer
forming
source
drain doping
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010473447.6A
Other languages
Chinese (zh)
Other versions
CN113745162B (en
Inventor
陈蓉峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202010473447.6A priority Critical patent/CN113745162B/en
Priority claimed from CN202010473447.6A external-priority patent/CN113745162B/en
Publication of CN113745162A publication Critical patent/CN113745162A/en
Application granted granted Critical
Publication of CN113745162B publication Critical patent/CN113745162B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a first device area and a second device area, the substrate comprises a substrate and a channel structure separated on the substrate, the extending direction of the channel structure is the same as the extending direction of the junction of the first device area and the second device area, and the substrate further comprises a gate structure crossing the channel structure; forming a first source-drain doping layer in a channel structure of the first device region; forming a shielding layer which is positioned on the first source drain doping layer and exposes the second device area; forming a protective layer on the side wall of the shielding layer and the side wall of the grid structure; and forming a second source-drain doping layer in the channel structure of the second device region. In the epitaxial growth process, the side wall of the grid structure and the first source drain doping layer are not provided with the epitaxial growth foundation by the protective layer, an impurity epitaxial layer is not easily formed on the grid structure and the first source drain doping layer, and the bridging risk caused by the impurity epitaxial layer can be reduced.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that a sub-threshold leakage (SCE) phenomenon, which is a so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; the gate structure is also transformed from the original polysilicon gate structure to a metal gate structure, and the work function layer in the metal gate structure can adjust the threshold voltage of the semiconductor structure.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device area and a second device area, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, the substrate comprises a substrate and a channel structure separated from the substrate, the extending direction of the channel structure is the same as the extending direction of the boundary of the first device area and the second device area, the substrate further comprises a gate structure crossing the channel structure, and the gate structure covers part of the top wall and part of the side wall of the channel structure; forming a first source-drain doping layer in the channel structures on two sides of the grid structure of the first device area; forming a shielding layer which is positioned on the first source drain doping layer and exposes the second device area; forming a protective layer on the side wall of the shielding layer and the side wall of the grid structure; and forming a second source-drain doping layer in the channel structure of the second device region, wherein the second source-drain doping layer and the first source-drain doping layer are different in conductivity type.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: the device comprises a substrate and a control circuit, wherein the substrate comprises a first device area and a second device area, the first device area is used for forming a first type transistor, and the second device area is used for forming a second type transistor; the channel structure is separated from the substrate, and the extending direction of the channel structure is the same as the extending direction of the junction of the first device area and the second device area; a gate structure spanning the channel structure and covering a portion of the top wall and a portion of the sidewalls of the channel structure; the first source-drain doping layer is positioned in the channel structures on two sides of the grid structure of the first device area; the shielding layer is positioned in the first device area and covers the gate structure, the first source-drain doping layer and the channel structure of the first device area; and the protective layer is positioned on the side wall of the shielding layer and the side wall of the grid structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the embodiment of the invention, a protective layer is formed on the shielding layer and the side wall of the gate structure, in the second device region, the second source-drain doped layer is usually formed by a selective epitaxial growth process, the protective layer makes the side wall of the gate structure and the first source-drain doped layer in the shielding layer not easy to expose, therefore, the protective layer can ensure that the side wall of the gate structure and the first source-drain doping layer in the shielding layer are not easy to have the basis of epitaxial growth in the epitaxial growth process and are not easy to be arranged on the gate structure at the junction of the first device area and the second device area, and an impurity epitaxial layer is formed on the first source-drain doping layer, so that the bridging risk caused by the impurity epitaxial layer can be reduced, the probability of leakage current of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is favorably optimized.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
FIGS. 4-8 are schematic views of alternative methods for forming semiconductor structures corresponding to various steps;
FIGS. 9-17 are schematic structural diagrams corresponding to steps of a method of forming a semiconductor structure according to an embodiment of the present invention;
FIG. 18 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The semiconductor structure formed at present still has a problem of poor performance. The reason for the poor performance of the semiconductor structure is analyzed in combination with a method for forming the semiconductor structure.
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure.
As shown in fig. 1, providing a substrate, where the substrate includes a first device region I and a second device region II, the first device region I is used to form a first type transistor, the second device region II is used to form a second type transistor, the substrate includes a substrate 1 and a fin portion 2 discrete on the substrate 1, an extending direction of the fin portion 2 is the same as an extending direction of a boundary between the first device region I and the second device region II, the substrate further includes a gate structure (not shown) crossing the fin portion 2, and the gate structure covers a part of a top wall and a part of a sidewall of the fin portion 2; forming a first source-drain doping layer 3 in the fin portion 2 on two sides of the gate structure of the first device region I; forming a side wall material layer 5 covering the substrate of the first device area I and the second device area II; and forming a shielding layer 4 which is positioned on the first source-drain doping layer 3 and exposes the second device area II.
As shown in fig. 2, the sidewall material layer 5 on both sides of the gate structure of the second device region II and the fin 2 with a partial thickness are etched, a groove 6 is formed in the fin 2,
as shown in fig. 3, forming a second source-drain doping layer 7 in the groove 6; and after the second source-drain doping layer 7 is formed, removing the shielding layer 4.
The step of forming the shielding layer 4 generally comprises: forming a shielding material layer covering the first device area I and the second device area II; the shielding material layer is patterned, the remaining shielding material layer located in the first device region I serves as a shielding layer 4, in the actual patterning process, an overlay error exists, a part of the sidewall material layer 5 on the first source drain doping layer 3 is easily exposed, in the step of etching the groove 6 formed in the gate structure of the second device region II, the sidewall material layer 5 on the first source drain doping layer 3 exposed by the shielding layer 4 is easily removed, so that a part of the region of the first source drain doping layer 3 is exposed, in the step of forming the second source drain doping layer 7 in the groove 6, an impurity epitaxial layer 8 (shown in fig. 3) is easily formed on the first source drain doping layer 3 exposed by the shielding layer 4, and the impurity epitaxial layer 8 is easily bridged with other devices, so that the electrical performance of the semiconductor structure is poor.
Fig. 4 to 8 are schematic structural diagrams corresponding to steps in another method for forming a semiconductor structure.
As shown in fig. 4 and 5, fig. 5 is a cross-sectional view at aa of fig. 4, and a base is provided, where the base includes a first device region I and a second device region II, the first device region I and the second device region II are used for forming devices of different conductivity types, the base includes a substrate 50, a fin 30 located on the substrate 50, and a gate structure 10 crossing the fin 30 and covering a part of a top wall and a part of a sidewall of the fin 30, and the gate structure 10 crosses the fin 30 of the first device region I and the second device region II and covering a part of a top wall and a part of a sidewall of the fin 30; forming offset sidewall layers 80 on sidewalls of the gate structure 10; after the offset sidewall layer 80 is formed, forming a first sidewall material layer 20 which conformally covers the offset sidewall layer 80 and the gate structure 10; etching the fin portion 30 of the second device region II, and forming a first groove (not shown in the figure) in the fin portion 30; and forming a first source-drain doping layer (not shown in the figure) in the first groove.
It should be noted that the step of forming the first source-drain doping layer includes: and forming a first epitaxial layer in the first groove by adopting a selective epitaxial growth process, and carrying out in-situ self-doping on the first epitaxial layer with first type ions to form a first source-drain doping layer (not shown in the figure). During the in-situ self-doping process, a small amount of the first type ions 70 is easily formed on the sidewalls of the offset sidewall layer 80 and the sidewalls of the first sidewall material layer 20.
As shown in fig. 6, after the first source-drain doping layer is formed, a second sidewall material layer 40 is formed to conformally cover the gate structure 10, the offset sidewall 80, and the first sidewall material layer 20.
As shown in fig. 7, a shielding layer (not shown) is formed to cover the first device region I and expose the second device region II; in the second device region II, the fin portions 30 on both sides of the gate structure 10 are etched using the shielding layer as a mask, and a second groove (not shown in the figure) is formed in the fin portion 30.
As shown in fig. 8, a second source-drain doping layer (not shown in the figure) is formed in the second groove, and a forming method of the second source-drain doping layer is the same as a forming direction of the first source-drain doping layer, which is not described herein again.
The step of forming the masking layer generally comprises: forming a shielding material layer covering a first device region I and a second device region II, patterning the shielding material layer, using the remaining shielding material layer located in the first device region I as a shielding layer, in an actual patterning process, in order to avoid an influence of an overlay error, the shielding layer usually covers a part of the second device region II, in a process of forming a second groove, the remaining second sidewall material layer 40 is easy to expose a first type ion 70 (as shown in B in the figure) remaining on a sidewall of the first sidewall material layer 20, correspondingly, in a step of forming a second source/drain doping layer, the first type ion 70 is easy to provide a good interface state for selective epitaxial growth, so that an impurity epitaxial layer 90 is easy to form on the sidewall of the first sidewall material layer 20 where the shielding layer is exposed, and in a subsequent process of forming interlayer dielectric layers on the substrate 50 on both sides of the gate structure 10, the impurity epitaxial layer 90 is likely to hinder the formation of the interlayer dielectric layer, and holes (void) are likely to exist in the interlayer dielectric layer, so that the semiconductor structure is likely to have a leakage condition.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, in which a protection layer is formed on the shielding layer and the sidewall of the gate structure, in the second device region, the second source-drain doping layer is usually formed by a selective epitaxial growth process, and the protection layer makes the sidewall of the gate structure and the first source-drain doping layer in the shielding layer not easily exposed, so that the protection layer can make the sidewall of the gate structure and the first source-drain doping layer in the shielding layer not easily have a basis of epitaxial growth during an epitaxial growth process, and not easily form an impurity epitaxial layer on the gate structure at a junction between the first device region and the second device region and on the first source-drain doping layer, which can reduce a bridging risk caused by the impurity epitaxial layer and reduce a probability of a leakage current of the semiconductor structure, the method is favorable for optimizing the electrical performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 9 to 17 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Referring to fig. 9 and 10, fig. 10 is a top view of fig. 9, a base is provided, the base includes a first device region I and a second device region II, the first device region I is used for forming a first type transistor, the second device region II is used for forming a second type transistor, the base includes a substrate 100, a channel structure 101 separated on the substrate 100, an extending direction of the channel structure 101 is the same as an extending direction of a boundary between the first device region I and the second device region II, the base further includes a gate structure 102 crossing the channel structure 101, and the gate structure 102 covers a part of a top wall and a part of a side wall of the channel structure 101.
In this embodiment, the first device region I is a pmos (positive Channel Metal Oxide semiconductor) device region, and the second device region II is an nmos (negative Channel Metal Oxide semiconductor) device region. In other embodiments, the first device region may also be an NMOS device region and the second device region may also be a PMOS device region.
The substrate 100 provides a process platform for subsequently forming semiconductor structures. In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The present embodiment takes the formed semiconductor structure as a fin field effect transistor (FinFET) as an example. Correspondingly, the channel structure 101 is a fin portion. In other embodiments, the semiconductor structure formed is a fully-enclosed transistor (GAA), and accordingly, the channel structure is a stacked structure including a sacrificial layer and a channel layer on the sacrificial layer.
In this embodiment, the channel structure 101 is made of silicon. In other embodiments, the material of the channel structure may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the gate structure 102 is a dummy gate structure, and occupies a process space for forming a metal gate structure subsequently.
In the present embodiment, the gate structure 102 is a stacked structure. Specifically, the gate structure 102 includes a gate oxide layer (not shown) and a gate layer (not shown) on the gate oxide layer.
In this embodiment, the gate oxide layer is made of silicon oxide, and the gate layer is made of polysilicon.
It should be noted that the extending direction of the gate structure 102 is perpendicular to the extending direction of the boundary between the first device region I and the second device region II.
In the step of providing the substrate, a protective sidewall layer 104 is further formed on the sidewall of the gate structure 102.
The protective sidewall layer 104 is used to define a formation region of the first source-drain doping layer and the second source-drain doping layer, and is also used to protect the sidewall of the gate structure 102 during the formation of the semiconductor structure.
In this embodiment, the material of the protective sidewall layer 104 is a low-k dielectric material (the low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9). The protective sidewall layer 104 is used for reducing the capacitive coupling effect between the gate structure 102 and the first source-drain doping layer and the second source-drain doping layer, so that the electrical performance of the semiconductor structure is improved.
In this embodiment, the material of the protective sidewall layer 104 includes: carbon doped SiN or oxygen doped SiN. In other embodiments, the material of the protective sidewall layer includes: SiON, SiBCN or SiCN.
The substrate further comprises: and an isolation structure 103 located on the substrate 100 at the side of the channel structure 101, wherein the isolation structure 103 covers a part of the sidewall of the channel structure 101, and the top surface of the isolation structure 103 is lower than the top surface of the channel structure 101. The isolation structure 103 is used to electrically isolate the respective channel structures 101.
In this embodiment, the isolation structure 103 is made of a dielectric material. Specifically, the material of the isolation structure 103 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation structure 103 includes silicon oxide.
The isolation structure 103 is formed prior to forming the gate structure 102.
The step of providing a substrate further comprises: a first sidewall material layer (not shown) is formed overlying the first device region I and the second device region II.
The first sidewall material layer and the protective sidewall layer 104 together define a formation region of a first source-drain doped layer to be formed subsequently, and the first sidewall material layer can prevent the protective sidewall layer 104 from being damaged in the process of forming the first source-drain doped layer in the channel structure 101 on two sides of the gate structure 102 subsequently.
Specifically, the material of the first sidewall material layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon nitride and boron nitride silicon carbide. In this embodiment, the material of the first sidewall material layer includes silicon nitride. The silicon nitride has high hardness and density, so that the first side wall material layer is not easy to be etched by mistake in the subsequent process, and the silicon nitride is not easy to provide a growth interface in the subsequent process of forming the first epitaxial layer through a selective epitaxial growth process, so that the formed semiconductor structure is not easy to have the problems of bridging and the like.
In this embodiment, the first sidewall material layer is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process is selected, so that the thickness uniformity of the first side wall material layer is improved, and the thickness of the first side wall material layer can be accurately controlled; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the first side wall material layer is correspondingly improved. In other embodiments, the first sidewall material layer may be formed by a Chemical Vapor Deposition (CVD) process or a low-pressure furnace process.
Referring to fig. 11 and 12, fig. 12 is a top view of fig. 11, and first source-drain doping layers 107 are formed in the channel structure 101 on two sides of the gate structure 102 of the first device region I.
When the semiconductor structure works, the first source-drain doping layer 107 is used for providing stress for a channel in the first device region I and improving the migration rate of carriers in the channel.
In this embodiment, the first device region I is used to form a PMOS. During operation of the semiconductor structure, the first source-drain doped layer 107 applies compressive stress (compressive stress) to the channel under the gate structure, and the compressive stress can improve mobility of holes. Specifically, the material of the first source-drain doping layer 107 is silicon germanium or silicon doped with P-type ions. Specifically, the P-type ions include one or more of B, Ga and In.
In other embodiments, the first source-drain doped layer is used as a source and a drain of the NMOS. When the semiconductor structure works, the first source-drain doped layer applies tensile stress (tensile stress) to a channel below the gate structure, and the tensile stress can improve the migration rate of electrons. Specifically, the material of the first source-drain doping layer is silicon carbide, silicon phosphide or silicon doped with N-type ions. Specifically, the N-type ions include one or more of P, As and Sb.
Specifically, the step of forming the first source-drain doping layer 107 includes: forming first grooves (not shown in the figure) in the channel structures on two sides of the gate structure 102 in the first device region I; and forming a first epitaxial layer in the first groove by adopting a selective epitaxial growth process, and carrying out ion doping on the first epitaxial layer to form a first source-drain doping layer 107.
The first groove provides a space for forming a first source drain doping layer.
The step of forming the first groove includes: forming a first shielding layer (not shown in the figure) on the substrate, wherein the first shielding layer covers the substrate located in the second device region II and exposes the substrate located in the first device region; and etching the channel structure 101 on two sides of the gate structure 102 by using the first shielding layer as a mask to form the first groove.
Specifically, the first shielding layer exposes the channel structures 101 on two sides of the gate structure 102 in the first device region I, and the first grooves are formed in the channel structures 101 on two sides of the gate structure 102.
The step of forming the first groove includes: forming a first shielding layer (not shown in the figure) on the substrate, wherein the first shielding layer covers the substrate and the gate structure 102 in the second device region II, and exposes the channel structures 101 on two sides of the gate structure 102 in the first device region I; and etching the channel structure 101 by taking the first shielding layer and the first side wall material layer as masks to form the first groove.
Specifically, the first shielding layer exposes the channel structures 101 on two sides of the gate structure 102 in the first device region I, and the first grooves are formed in the channel structures 101 on two sides of the gate structure 102.
In this embodiment, the first blocking layer is made of a material that is easy to remove, and the substrate and the gate structure 102 are not easily damaged in the subsequent process of removing the first blocking layer.
In this embodiment, the channel structures 101 on the two sides of the gate structure 102 are etched by using a dry etching process, and first grooves are formed in the channel structures 101 on the two sides of the gate structure 102. The dry etching process has the characteristic of anisotropic etching, has better etching profile controllability, is favorable for enabling the appearance of the first groove to meet the process requirement, and is favorable for accurately controlling the depth of the first groove.
The method for forming the semiconductor structure further comprises the following steps: after the first groove is formed and before the first source-drain doping layer 107 is formed, the first shielding layer is removed.
In this embodiment, an ashing process is used to remove the first shielding layer.
It should be noted that, in the process of forming the first groove, in the first device region I, the first sidewall material layer on the sidewall of the gate structure 102 is easily removed by etching, and the remaining first sidewall material layer located in the second device region II is used as the first sidewall layer 108.
In this embodiment, a Selective Epitaxial Growth (SEG) process is used to form a first epitaxial layer (not shown in the figure) in the first groove, and the first epitaxial layer is ion-doped to form a first source-drain doping layer 107. The first epitaxial layer is formed through a selective epitaxial growth process, and the film is high in purity, few in growth defects and high in formation quality, so that the performance of the semiconductor structure is optimized.
In this embodiment, an in-situ self-doping process is adopted to perform ion doping on the first epitaxial layer, so as to form the first source-drain doping layer 107. By adopting the in-situ self-doping manner, the uniformity of the concentration of the doped ions in the first source-drain doped layer 107 is improved, so that the quality and the performance of the first source-drain doped layer 107 are improved. In other embodiments, after the first epitaxial layer is formed, ion doping may be performed on the first epitaxial layer in an ion implantation manner to form a first source-drain doping layer.
It should be noted that, during the process of ion doping the first epitaxial layer by using the in-situ self-doping process, P-type ions are easily doped on the sidewall of the gate structure 102.
Referring to fig. 13 and 14, a shielding layer is formed on the first source-drain doping layer 107 and exposes the second device region II.
In the subsequent process of forming the second groove in the second device region II, the shielding layer is used to protect the first source-drain doping layer 107 from being damaged.
In this embodiment, the shielding layer located on the first source-drain doping layer 107 and exposing the second device region II is used as a second shielding layer 108.
In this embodiment, the material of the second shielding layer 108 is a material that is easy to remove, and the substrate and the gate structure 102 are not easily damaged in the subsequent process of removing the second shielding layer 108.
Specifically, the second shielding layer 108 includes an organic material layer 1081, a hard mask layer 1082 disposed on the organic material layer 1081, a bottom anti-reflective coating 1083 disposed on the hard mask layer 1082, and a photoresist layer 1084 disposed on the bottom anti-reflective coating 1083.
In this embodiment, the material of the organic material layer 1081 includes an ODL (organic dielectric layer) material, a photoresist, a Spin On Carbon (SOC) layer, a DUO (Deep ultraviolet Absorbing Oxide) material, or an APF (Advanced Patterning Film) material.
In this embodiment, the hard mask layer 1082 includes silicon oxide or silicon nitride.
The method for forming the semiconductor structure further comprises the following steps: after the first source-drain doping layer 107 is formed and before the second shielding layer is formed, a side wall material layer covering the substrate in the first device region I and the second device region II is formed.
In this embodiment, the sidewall material layer formed after the first source-drain doping layer 107 is formed is used as the second sidewall material layer 106.
The second side wall material layer 106, the protective side wall layer 104 and the subsequently formed protective layer together define a formation region of a subsequently formed second source-drain doping layer, and in the subsequent process of forming the second source-drain doping layer in the channel structure 101 on both sides of the gate structure 102, the second side wall material layer 106 can prevent the protective side wall layer 104 from being damaged.
Specifically, the material of the second sidewall material layer 106 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron silicon, and boron nitride silicon carbide. In this embodiment, the material of the second sidewall material layer 106 includes silicon nitride. The silicon nitride has high hardness and density, so that the second side wall material layer 106 is not easily etched by mistake in the subsequent process, and the silicon nitride is not easy to provide a growth interface in the subsequent process of forming the second epitaxial layer through a selective epitaxial growth process, so that the formed semiconductor structure is not easy to have the problems of bridging and the like.
In this embodiment, the second sidewall material layer 106 is formed by an Atomic Layer Deposition (ALD) process. In other embodiments, the second sidewall material layer may be formed by a chemical vapor deposition process or a low pressure furnace process.
It should be noted that, correspondingly, the second shielding layer 108 is formed on the second side wall material layer 106.
Referring to fig. 15 and 16, a protective layer 109 is formed on sidewalls of the second blocking layer 108 and sidewalls of the gate structure 102 (as shown in fig. 16).
A protective layer 109 is formed on the second masking layer 108 and the sidewalls of the gate structure 102, and subsequently in the second device region II, the second source-drain doped layer is usually formed by a selective epitaxial growth process, the protective layer 109 makes the sidewall of the gate structure 102 and the first source-drain doped layer 107 in the second shielding layer 108 not easily exposed, therefore, the protective layer 109 can enable the sidewall of the gate structure 102 and the first source-drain doping layer 107 in the second shielding layer 108 not to have the basis of epitaxial growth in the epitaxial growth process, and is not easy to be on the gate structure 102 at the boundary between the first device region I and the second device region II, and an impurity epitaxial layer is formed on the first source-drain doping layer 107, so that the bridging risk caused by the impurity epitaxial layer can be reduced, the probability of leakage current of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is favorably optimized.
It should be noted that the protective layer 109 is not too thick nor too thin. If the protective layer 109 is too thick, the process time required for forming the protective layer 109 is too long, and the formation efficiency of the semiconductor structure is not easily improved; the channel structure 101 is a thin and tall structure, and if the protection layer 109 is too thick, the protection layer 109 is also prone to squeezing the channel structure 101, and the protection layer 109 is prone to bending or deformation, resulting in poor electrical properties of the semiconductor structure. If the protection layer 109 is too thin, in the process of subsequently forming a second source-drain doping layer in the second device region II, the protection layer 109 cannot well protect the gate structure 102 and the second shielding layer 108, which easily causes the side wall of the gate structure 102 and the first source-drain doping layer 107 in the second shielding layer 108 to be exposed, and impurity doping layers are easily formed on the side wall of the gate structure 102 and the side wall of the second shielding layer 108, which easily causes the problem of bridging of the impurity doping layers, and the semiconductor structure is easy to generate leakage current, which is not favorable for optimizing the electrical performance of the semiconductor structure. In this embodiment, the thickness of the protection layer 109 is
Figure BDA0002515089400000111
To
Figure BDA0002515089400000112
The forming step of the protective layer 109 includes: conformally covering a protective material layer 110 on the second barrier layer 108 and the substrate of the second device region II (as shown in FIG. 15); after the protective material layer 110 is formed, the protective material layer 110 on two sides of the gate structure 102 of the second device region II and the channel structure 101 with a partial thickness are etched, a groove is formed in the channel structure 101, and the remaining protective material layer 110 serves as the protective layer 109.
In this embodiment, the protective material layer 110 is formed by an atomic layer deposition process. The atomic layer deposition process is selected, so that the thickness uniformity of the protective material layer 110 is improved, and the thickness of the protective material layer 110 can be accurately controlled; in addition, the atomic layer deposition process has good gap filling performance and step coverage, and accordingly improves the conformal coverage capability of the protective material layer 110. In other embodiments, the protective material layer may be formed by a chemical vapor deposition process.
Specifically, in this embodiment, a groove in the channel structure 101 in the second device region II is used as the second groove 111, and the second groove 111 provides a process space for subsequently forming the second source-drain doping layer.
In this embodiment, in the process of etching the protective material layer 110 on two sides of the gate structure 102 of the second device region II and the channel structure 101 with a partial thickness, the second sidewall material layer 106 is also etched, and the second groove 111 is enclosed by the second sidewall material layer 106 and the channel structure 101.
In the process of etching the second sidewall material layer 106 of the second device region II, the etching difficulty of the protection material layer 110 is greater than that of the second sidewall material layer 106. In addition, in the subsequent step of forming the second epitaxial layer by the selective epitaxial growth process, the protective layer 109 is not easy to provide a good growth interface, and accordingly, an impurity epitaxial layer is not easy to form.
Thus, the material of the protective layer 109 includes one or more of silicon oxide, silicon oxynitride, silicon carbide nitride, boron nitride, and boron carbon silicon nitride. In this embodiment, the material of the protection layer 109 includes silicon oxide. The silicon oxide has higher process compatibility, and is a material which is commonly used in the process and has lower cost, so the silicon oxide is selected, and the process difficulty and the process cost are favorably reduced.
In this embodiment, the second shielding layer 108 is used as a mask, and the protective material layer 110 on two sides of the gate structure 102 of the second device region II and the channel structure 101 with a partial thickness are etched by using a dry etching process, so as to form a second groove 111 in the channel structure 101. The anisotropic etching characteristic is achieved, the etching profile controllability is good, the appearance of the second groove 111 meets the process requirements, the dry etching process is beneficial to accurately controlling the removal thickness of the channel structure 101, and the damage to other film layer structures is reduced. And by replacing the etching gas, the protective material layer 110, the second side wall material layer and the channel structure 101 can be etched in the same etching equipment, so that the process steps are simplified.
In this embodiment, in the process of forming the second groove 111 by using a dry etching process, the etching gas includes HF, HBr, and CF4。
It should be noted that, in the process of forming the second groove 111, the second sidewall material layer 106 exposed by the second shielding layer 108 is easily removed by etching.
In the step of forming the protection layer 109, the protection layer 109 is further formed on the second sidewall material layer 106 of the sidewall of the channel structure 101 in the second device region II.
The method for forming the semiconductor structure further comprises the following steps: after the second groove 111 is formed, the second blocking layer 108 is removed.
The second shielding layer 108 is made of an organic material, and in the embodiment of the invention, after the second groove 111 is formed, the second shielding layer 108 is removed, so that the second shielding layer 108 does not easily pollute the machine.
In this embodiment, the second blocking layer 108 is removed by an ashing process.
Referring to fig. 17, a second source-drain doping layer 112 is formed in the channel structure 101 of the second device region II, where the conductivity types of the second source-drain doping layer 112 and the first source-drain doping layer 107 are different.
When the semiconductor structure works, the second source-drain doping layer 112 is used for providing stress for a channel in the second device region II and improving the migration rate of carriers in the channel.
In this embodiment, the second device region II is used to form an NMOS. After the gate structure 102 is replaced with a metal gate structure, when the semiconductor structure works, the second source-drain doping layer 112 applies tensile stress to a channel below the metal gate structure, and the channel is stretched to improve the migration rate of electrons. Specifically, the material of the second source-drain doping layer 112 is silicon carbide, silicon phosphide or silicon doped with N-type ions. Specifically, the N-type ions include one or more of P, As and Sb.
In other embodiments, the second device region II may also be used to form a PMOS, and when the semiconductor structure operates, the first source-drain doped layer applies a compressive stress to a channel below the metal gate structure, and the compressive channel may improve mobility of holes. Specifically, the second source-drain doping layer is made of silicon germanium or silicon doped with P-type ions. Specifically, the P-type ions include one or more of B, Ga and In.
In the process of forming the second epitaxial layer by epitaxial growth, the protective layer 109 enables the side wall of the gate structure 102 and the first source-drain doping layer 107 in the second shielding layer 108 not to have the basis of epitaxial growth, so that an impurity epitaxial layer is not easily formed on the gate structure 102 at the junction of the first device region I and the second device region II and on the first source-drain doping layer 107, the bridging risk caused by the impurity epitaxial layer can be reduced, the probability of leakage current of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is favorably optimized.
Correspondingly, referring to fig. 18, an embodiment of the invention further provides a semiconductor structure.
The semiconductor structure includes: a substrate 200, the substrate 200 including a first device region I for forming a first type transistor and a second device region II for forming a second type transistor; the channel structure 201 is separated from the substrate 200, and the extending direction of the channel structure 201 is the same as the extending direction of the junction of the first device region I and the second device region II; a gate structure (not shown) crossing the channel structure 201 and covering a portion of the top wall and a portion of the sidewall of the channel structure 201; the first source-drain doping layer 207 is positioned in the channel structure 201 on two sides of the gate structure of the first device region I; the shielding layer 208 is positioned in the first device region I, and the shielding layer 208 covers the gate structure, the first source-drain doping layer 207 and the channel structure 201 of the first device region I; and a protective layer 209 located on the sidewall of the shielding layer 208 and the sidewall of the gate structure.
In the semiconductor structure provided by the embodiment of the present invention, the protection layer 209 is located on the sidewall of the shielding layer 208 and the sidewall of the gate structure, and then in the second device region II, the second source-drain doping layer is formed in the channel structure 201 on both sides of the gate structure, the second source-drain doping layer is usually formed by using a selective epitaxial growth process, and the protection layer 209 makes the sidewall of the gate structure and the first source-drain doping layer 207 in the shielding layer 208 not to be exposed easily, so that in the epitaxial growth process, the protection layer 209 can make the sidewall of the gate structure and the first source-drain doping layer 207 in the shielding layer 208 not have the basis of epitaxial growth, and is not easy to form an impurity epitaxial layer on the gate structure at the junction of the first device region I and the second device region II and on the first source-drain doping layer 207, which can reduce the bridging risk caused by the impurity epitaxial layer, the probability of the leakage current of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is favorably optimized.
In this embodiment, the first device region I is a PMOS device region, and the second device region II is an NMOS device region. In other embodiments, the first device region I may also be an NMOS device region and the second device region II may also be a PMOS device region.
The substrate 200 provides a process platform for subsequently forming semiconductor structures. In this embodiment, the substrate 200 is made of silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In the present embodiment, the formed semiconductor structure is a fin field effect transistor (FinFET) as an example. Correspondingly, the channel structure 201 is a fin portion. In other embodiments, the semiconductor structure formed is a fully-enclosed transistor (GAA), and accordingly, the channel structure is a stacked structure including a sacrificial layer and a channel layer on the sacrificial layer.
In this embodiment, the channel structure 201 is made of silicon. In other embodiments, the material of the channel structure may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the gate structure is a dummy gate structure, and occupies a process space for forming a metal gate structure subsequently.
In this embodiment, the gate structure is a stacked structure. Specifically, the gate structure includes a gate oxide layer (not shown in the figure) and a gate layer (not shown in the figure) on the gate oxide layer.
In this embodiment, the gate oxide layer is made of silicon oxide, and the gate layer is made of polysilicon.
It should be noted that the extending direction of the gate structure is perpendicular to the extending direction of the boundary between the first device region I and the second device region II.
The semiconductor structure further includes: and a protective sidewall layer (not shown) on the sidewall of the gate structure.
The protective sidewall layer is used for defining a formation region of the first source drain doping layer 207 and a subsequently formed second source drain doping layer.
In this embodiment, the material of the protective sidewall layer is a low-k dielectric material. The protective sidewall layer is used for reducing the capacitive coupling effect between the subsequent metal gate structure and the first source-drain doping layer 207 and the capacitive coupling effect between the metal gate structure and the second source-drain doping layer, so that the electrical performance of the semiconductor structure is improved.
In this embodiment, the material of the protective sidewall layer includes: carbon doped SiN or oxygen doped SiN. In other embodiments, the material of the protective sidewall layer includes: SiON, SiBCN or SiCN.
The substrate further comprises: and an isolation structure 203 located on the substrate 200 at the side of the channel structure 201, wherein the isolation structure 203 covers a part of the sidewall of the channel structure 201, and the top surface of the isolation structure 203 is lower than the top surface of the channel structure 201. The isolation structures 203 are used to electrically isolate the respective channel structures 201 from each other.
In this embodiment, the isolation structure 203 is made of a dielectric material. Specifically, the material of the isolation structure 203 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation structure 203 includes silicon oxide.
When the semiconductor structure works, the first source-drain doping layer 207 is used for providing stress for a channel in the first device region I and improving the migration rate of carriers in the channel.
In this embodiment, the first device region I is used to form a PMOS. When the semiconductor structure works, the first source-drain doping layer 207 applies compressive stress to a channel below the metal gate structure, and the compressive channel can improve the mobility of holes. Specifically, the material of the first source-drain doping layer 207 is silicon germanium or silicon doped with P-type ions. Specifically, the P-type ions include one or more of B, Ga and In.
In other embodiments, the first source-drain doped layer is used as a source and a drain of the NMOS. When the semiconductor structure works, the first source-drain doped layer applies tensile stress to a channel below the metal gate structure, and the channel is stretched to improve the migration rate of electrons. Specifically, the material of the first source-drain doping layer is silicon carbide, silicon phosphide or silicon doped with N-type ions. Specifically, the N-type ions include one or more of P, As and Sb.
In the process of forming the second recess 211 in the second device region II, the shielding layer 208 is used to protect the first source-drain doping layer 207 from being damaged.
In this embodiment, the material of the blocking layer 208 is easy to remove, and the substrate and the gate structure are not easily damaged in the subsequent process of removing the blocking layer 208.
Specifically, the shielding layer 208 includes an organic material layer 2081, a hard mask layer 2082 on the organic material layer 2081, a bottom anti-reflection coating 2083 on the hard mask layer 2082, and a photoresist layer 2084 on the bottom anti-reflection coating 2083.
In this embodiment, the material of the organic material layer 2081 includes an ODL (organic dielectric layer) material, a photoresist, a Spin On Carbon (SOC) layer, a DUO (deep ultraviolet Absorbing Oxide) material, or an APF (Advanced Patterning Film) material.
In this embodiment, the hard mask layer 2082 is made of silicon oxide or silicon nitride.
Specifically, the material of the protective layer 209 includes one or more of silicon oxide, silicon oxynitride, silicon carbide nitride, boron nitride boron, and boron nitride silicon carbide. In this embodiment, the material of the protection layer 209 includes silicon oxide. The silicon oxide has higher process compatibility, and is a material which is commonly used in the process and has lower cost, so the silicon oxide is selected, and the process difficulty and the process cost are favorably reduced.
It should be noted that the protective layer 209 is not too thick nor too thin. If the protective layer 209 is too thick, the process time required for forming the protective layer 209 is too long, and the forming efficiency of the semiconductor structure is not easily improved; the channel structure 201 is a thin and high structure, if the protection layer 209 is too thick, the protection layer 209 is also easy to extrude the channel structure 201, and the protection layer 209 is easy to bend or deform, so that the electrical performance of the semiconductor structure is poor. If the protection layer 209 is too thin, in the process of forming a second source-drain doping layer in the second device region II, the protection layer 209 cannot well protect the gate structure and the shielding layer 208, which easily causes the side wall of the gate structure and the first source-drain doping layer 207 in the shielding layer 208 to be exposed, impurity doping layers are easily formed on the side wall of the gate structure and the side wall of the second shielding layer 208, the impurity epitaxial layer easily causes a bridging risk, and the semiconductor structure is easy to generate leakage current, which is not beneficial to optimizing the electrical performance of the semiconductor structure. In this embodiment, the thickness of the protection layer 209 is
Figure BDA0002515089400000161
To
Figure BDA0002515089400000162
It should be noted that, in the first region I, the side wall material layer 206 is further located between the isolation structure 203 and the shielding layer 208, between the channel structure 201 and the shielding layer 208, between the first source-drain doping layer 207 and the gate structure, and between the gate structure and the shielding layer 208.
It should be noted that the protection layer 209 is further located on the sidewall spacer material layer 206 on the sidewall of the channel structure 201 in the second device region II.
The semiconductor structure further includes: and the groove is positioned in the channel structure 201 at two sides of the gate structure in the second device area II.
In this embodiment, the grooves in the channel structures 201 on both sides of the gate structure in the second region II are used as the second grooves 211. The second recess 211 provides a process space for the subsequent formation of a second source-drain doped layer.
The semiconductor structure further includes: and the side wall material layer 206 is positioned between the protective layer 209 and the channel structure 201, between the protective layer 209 and the gate structure, and also positioned between the first source-drain doping layer 207 and the shielding layer 208.
The sidewall material layer 206 is used to protect the protective sidewall layer from damage.
The sidewall material layer 206 and the protection layer 209 have etching selectivity, specifically, the etched difficulty of the sidewall material layer 206 is smaller than that of the protection layer 209, so that in the process of etching the channel structures 201 on two sides of the gate structure in the second device region II to form the second groove 211, the protection layer 209 protects the side wall of the shielding layer 208 and the side wall of the gate structure, the first source-drain doping layer 207 is not exposed easily, the doping ions formed on the side wall of the gate structure are not exposed easily, and in the subsequent process of forming the second epitaxial layer through a selective epitaxial growth process, impurity epitaxial layers are not formed on the first source-drain doping layer 207 and the side wall of the gate structure easily, so that the probability of bridging is reduced.
Specifically, the material of the sidewall material layer 206 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron, and boron nitride silicon carbide. In this embodiment, the material of the sidewall material layer 206 includes silicon nitride. The silicon nitride has high hardness and density, so that the sidewall material layer 206 is not easily etched by mistake in the subsequent process, and the silicon nitride is not easy to provide a growth interface in the subsequent process of forming the first epitaxial layer through a selective epitaxial growth process, so that the formed semiconductor structure is not easy to have the problems of bridging and the like.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first device area and a second device area, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, the substrate comprises a substrate and a channel structure separated from the substrate, the extending direction of the channel structure is the same as the extending direction of the boundary of the first device area and the second device area, the substrate further comprises a gate structure crossing the channel structure, and the gate structure covers part of the top wall and part of the side wall of the channel structure;
forming a first source-drain doping layer in the channel structures on two sides of the grid structure of the first device area;
forming a shielding layer which is positioned on the first source drain doping layer and exposes the second device area;
forming a protective layer on the side wall of the shielding layer and the side wall of the grid structure;
and forming a second source-drain doping layer in the channel structure of the second device region, wherein the second source-drain doping layer and the first source-drain doping layer are different in conductivity type.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming the protective layer comprises:
conformally covering a layer of protective material over the barrier layer and the substrate of the second device region;
and after the protective material layer is formed, etching the protective material layer on two sides of the grid structure of the second device area and the channel structure with partial thickness, forming a groove in the channel structure, and taking the residual protective material layer as the protective layer.
3. The method of claim 2, wherein the layer of protective material is formed using an atomic layer deposition process or a chemical vapor deposition process.
4. The method of forming a semiconductor structure of claim 1, wherein the protective layer has a thickness of
Figure FDA0002515089390000011
To
Figure FDA0002515089390000012
5. The method of forming a semiconductor structure of claim 1, wherein a material of the protective layer comprises one or more of silicon oxide, silicon oxynitride, silicon carbide nitride, boron nitride boron silicon nitride, and boron carbon silicon nitride.
6. The method of forming a semiconductor structure of claim 2, further comprising: after the first source-drain doping layer is formed and before the shielding layer is formed, forming a side wall material layer of the substrate covering the first device area and the second device area;
in the step of forming a protective material layer, the protective material layer is formed on the shielding layer and the side wall material layer of the second device region;
and in the process of forming the groove, etching the side wall material layer of the second device region, wherein the groove is surrounded by the side wall material layer and the channel structure.
7. The method for forming the semiconductor structure according to claim 6, wherein in the process of etching the sidewall material layer of the second device region, the etching difficulty of the protective material layer is greater than that of the sidewall material layer.
8. The method for forming a semiconductor structure according to claim 2, wherein a recess is formed in the channel structure by a dry etching process using the barrier layer as a mask.
9. The method of claim 8, wherein a dry etch process is used, and wherein an etch gas comprises HF, HBr, and CF during the forming of the recess4。
10. The method for forming the semiconductor structure according to claim 1, wherein the step of forming the second source-drain doping layer comprises: and forming an epitaxial layer by adopting a selective epitaxial growth process, and carrying out in-situ doping on the epitaxial layer to form the second source-drain doping layer.
11. The method of claim 1, wherein in the step of providing the substrate, the channel structure is a fin;
or the channel structure is a channel lamination layer, and the channel lamination layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer.
12. The method for forming the semiconductor structure according to claim 1, wherein In the step of forming the first source-drain doping layer, one or more of B, Ga and In are doped In the first source-drain doping layer;
in the step of forming the second source-drain doping layer, one or more of P, As and Sb are doped in the second source-drain doping layer;
alternatively, the first and second electrodes may be,
in the step of forming the first source-drain doping layer, one or more of P, As and Sb are doped in the first source-drain doping layer;
in the step of forming the second source-drain doping layer, one or more of B, Ga and In are doped In the second source-drain doping layer.
13. A semiconductor structure, comprising:
the device comprises a substrate and a control circuit, wherein the substrate comprises a first device area and a second device area, the first device area is used for forming a first type transistor, and the second device area is used for forming a second type transistor;
the channel structure is separated from the substrate, and the extending direction of the channel structure is the same as the extending direction of the junction of the first device area and the second device area;
a gate structure spanning the channel structure and covering a portion of the top wall and a portion of the sidewalls of the channel structure;
the first source-drain doping layer is positioned in the channel structures on two sides of the grid structure of the first device area;
the shielding layer is positioned in the first device area and covers the gate structure, the first source-drain doping layer and the channel structure of the first device area;
and the protective layer is positioned on the side wall of the shielding layer and the side wall of the grid structure.
14. The semiconductor structure of claim 13, wherein a material of the protective layer comprises: one or more of silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon nitride, and boron nitride silicon carbide.
15. The semiconductor structure of claim 13, wherein the protective layer has a thickness of
Figure FDA0002515089390000031
To
Figure FDA0002515089390000032
16. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: and the side wall material layer is positioned between the protective layer and the channel structure, between the protective layer and the grid structure, and between the first source drain doping layer and the shielding layer.
17. The semiconductor structure of claim 16, wherein the spacer material layer and the protective layer have an etch selectivity.
18. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: and the groove is positioned in the channel structures at two sides of the grid electrode structure in the second device area.
19. The semiconductor structure of claim 13, wherein the channel structure is a fin; alternatively, the first and second electrodes may be,
the channel structure is a channel stack including a sacrificial layer and a channel layer on the sacrificial layer.
CN202010473447.6A 2020-05-29 Semiconductor structure and forming method thereof Active CN113745162B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010473447.6A CN113745162B (en) 2020-05-29 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010473447.6A CN113745162B (en) 2020-05-29 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN113745162A true CN113745162A (en) 2021-12-03
CN113745162B CN113745162B (en) 2024-05-17

Family

ID=

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103589A (en) * 2013-04-10 2014-10-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing transistor
US20150171085A1 (en) * 2013-12-18 2015-06-18 Semiconductor Manufacturing International (Shanghai) Corporation Fin field effect transistor and method for forming the same
CN105489555A (en) * 2014-09-19 2016-04-13 中国科学院微电子研究所 Manufacturing method of semiconductor device
CN107346730A (en) * 2016-05-05 2017-11-14 中芯国际集成电路制造(上海)有限公司 Improve the method for performance of semiconductor device
CN107346762A (en) * 2016-05-05 2017-11-14 中芯国际集成电路制造(上海)有限公司 The forming method of fin field effect pipe

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103589A (en) * 2013-04-10 2014-10-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing transistor
US20150171085A1 (en) * 2013-12-18 2015-06-18 Semiconductor Manufacturing International (Shanghai) Corporation Fin field effect transistor and method for forming the same
CN105489555A (en) * 2014-09-19 2016-04-13 中国科学院微电子研究所 Manufacturing method of semiconductor device
CN107346730A (en) * 2016-05-05 2017-11-14 中芯国际集成电路制造(上海)有限公司 Improve the method for performance of semiconductor device
CN107346762A (en) * 2016-05-05 2017-11-14 中芯国际集成电路制造(上海)有限公司 The forming method of fin field effect pipe

Similar Documents

Publication Publication Date Title
CN109427582B (en) Semiconductor structure and forming method thereof
CN112309861B (en) Semiconductor structure, forming method thereof and transistor
CN110364483B (en) Semiconductor structure and forming method thereof
CN110797262A (en) Semiconductor device and method of forming the same
CN110581173B (en) Semiconductor structure and forming method thereof
CN109003899B (en) Semiconductor structure, forming method thereof and forming method of fin field effect transistor
CN111554578A (en) Semiconductor structure and forming method thereof
CN108022881B (en) Transistor and forming method thereof
CN113809011B (en) Semiconductor structure and forming method thereof
CN111490092B (en) Semiconductor structure and forming method thereof
CN113745162B (en) Semiconductor structure and forming method thereof
CN109003976B (en) Semiconductor structure and forming method thereof
CN112151381A (en) Semiconductor structure and forming method thereof
CN113745162A (en) Semiconductor structure and forming method thereof
CN111128731A (en) Semiconductor device and method of forming the same
CN113838806B (en) Semiconductor structure and forming method thereof
CN112652578B (en) Method for forming semiconductor structure and transistor
CN110875390B (en) Semiconductor structure and forming method thereof
CN112951725B (en) Semiconductor structure and forming method thereof
CN112103249B (en) Semiconductor structure and forming method thereof
CN112151606B (en) Semiconductor structure and forming method thereof
CN111863710B (en) Semiconductor structure and forming method thereof
CN110690286B (en) Semiconductor structure and forming method thereof
CN114078769A (en) Semiconductor structure and forming method thereof
CN117476461A (en) Method for forming semiconductor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant