CN108573862A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108573862A CN108573862A CN201710131028.2A CN201710131028A CN108573862A CN 108573862 A CN108573862 A CN 108573862A CN 201710131028 A CN201710131028 A CN 201710131028A CN 108573862 A CN108573862 A CN 108573862A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 38
- 238000000280 densification Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
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- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
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- 239000000377 silicon dioxide Substances 0.000 claims description 4
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
Abstract
A kind of semiconductor structure and forming method thereof, method includes：Substrate, substrate have device architecture, and device architecture includes initial sidewall structure；Initial first medium layer is formed on substrate, device architecture and initial sidewall structure；Initial first medium layer is planarized, first medium layer is formed；The initial sidewall structure in removal part forms sidewall structure, and sidewall structure top surface is less than or is flush to first medium layer top surface minimum point；After forming sidewall structure, densification first medium layer forms initial second dielectric layer, and initial second dielectric layer bottom surface is less than sidewall structure top surface, and initial second dielectric layer density is more than first medium layer density；After forming initial second dielectric layer, removal devices structure forms hatch frame, forming material layer in hatch frame and in initial second dielectric layer；Smoothing material layer and initial second dielectric layer form gate structure and second dielectric layer up to exposing sidewall structure top surface.The second dielectric layer isolation performance is good.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
With the reduction of technology node, traditional gate dielectric layer is constantly thinning, and transistor leakage amount increases therewith, causes half
The problems such as conductor device power wastage.To solve the above problems, prior art offer is a kind of to substitute polysilicon gate by metal gates
The solution of pole.Wherein, post tensioned unbonded prestressed concrete (gate last) technique is to form a main technique of metal gates.
However, during rear grid technique, the metal material of metal gates makes the dielectric layer in semiconductor structure
Isolation performance is deteriorated, to influence the performance of semiconductor structure.
Invention content
The technical problem to be solved by the present invention is to provide a kind of semiconductor structures and forming method thereof, can improve semiconductor junction
Structure performance.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of semiconductor structure, including：It provides
Substrate has device architecture in the substrate, and the device architecture includes initial sidewall structure；In the substrate, device architecture
And the top surface of initial sidewall structure forms initial first medium layer；The initial first medium layer is planarized, until sudden and violent
Expose the top surface of initial sidewall structure, forms first medium layer；The initial sidewall structure in removal part forms sidewall structure, institute
The top surface for stating sidewall structure is less than or is flush to the minimum point of the first medium layer top surface；Form the side wall
After structure, densification processing is carried out to the part first medium layer and forms initial second dielectric layer, described initial second is situated between
The bottom surface of matter layer is less than the top surface of the sidewall structure, and the density of the initial second dielectric layer is more than described the
The density of one dielectric layer；It is formed after the initial second dielectric layer, removal devices structure forms hatch frame；In the opening
Forming material layer in the interior and initial second dielectric layer of structure；The material layer and initial second dielectric layer are planarized until sudden and violent
Expose the top surface of sidewall structure, forms gate structure and second dielectric layer.
Optionally, the substrate includes：Firstth area and the secondth area.
Optionally, the device architecture includes positioned at first dummy gate structure in firstth area and positioned at secondth area
The second dummy gate structure；First dummy gate structure includes：First pseudo- gate dielectric layer and it is situated between positioned at the described first pseudo- grid
The first dummy gate layer on matter layer；Second dummy gate structure includes：Second pseudo- gate dielectric layer and pseudo- positioned at described second
The second dummy gate layer on gate dielectric layer.
Optionally, first dummy gate structure is less than the second dummy gate structure along raceway groove along the size of orientation
The size of length direction.
Optionally, the top surface of first dummy gate layer has the first mask layer；The top of second dummy gate layer
Portion surface has the second mask layer；First mask layer thickness is thin compared with the second mask layer thickness.
Optionally, the initial sidewall structure includes initial first side wall and initial second side wall, initial first side
Wall is located at the side wall of the described first pseudo- gate dielectric layer and the first dummy gate layer, and initial second side wall is located at the described second pseudo- grid
The side wall of dielectric layer and the second dummy gate layer.
Optionally, during planarizing the initial first medium layer, further include：The first mask layer and second is removed to cover
Film layer.
Optionally, the material of the initial first medium layer includes：Silica.
Optionally, the formation process of the initial first medium layer includes：Fluid chemistry gas-phase deposition.
Optionally, the technique of the planarization initial first medium layer includes：Chemical mechanical milling tech.
Optionally, the technique of the initial sidewall structure in removal part includes：Isotropic dry etch process or wet etching
Technique.
Optionally, the technological parameter of the isotropic dry etch process includes：Etching gas includes：CH3F、CH2F2
And O2, wherein CH3The flow of F is：10 standard milliliters/minute~500 standard milliliters/minute, CH2F2Flow be：10 standards
Ml/min~200 standard milliliters/minute, O2Flow be：10 standard milliliters/minute~300 standard milliliters/minute, pressure
For：The millitorr of 2 millitorrs~50, power：100 watts~200 watts.
Optionally, the initial sidewall structure is along the removal amount on the direction on the base top surface：3 receive
Rice~10 nanometers.
Optionally, densification processing carried out to the first medium layer form the technique of initial second dielectric layer include：It is high
Isothermal plasma processing；The technological parameter of the high-temperature plasma treatment process includes：Gas includes：Helium, the stream of helium
Amount is：100 standard milliliters/minute~1000 standard milliliters/minute, temperature：300 degrees Celsius~500 degrees Celsius, 100 watts of power
~1000 watts, pressure：The support of 0.2 support~5.
Optionally, the minimum thickness of the second dielectric layer is：5 nanometers~20 nanometers.
Optionally, the technique for planarizing the material layer and initial second dielectric layer includes：Chemical machinery polishes technique.
Correspondingly, the present invention also provides a kind of a kind of semiconductor structures formed using the above method, including：Substrate, institute
Stating has gate structure in substrate, the gate structure includes sidewall structure, the top surface of the sidewall structure and the grid
The top surface of pole structure flushes；The top surface of first medium layer in the substrate, the first medium layer is less than
The top surface of the sidewall structure；Second dielectric layer on the first medium layer, the top of the second dielectric layer
Surface is flushed with the top surface of the sidewall structure.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
In the forming method for the semiconductor structure that technical solution of the present invention provides, by removing the initial sidewall structure in part,
The top surface for being formed by sidewall structure is set to be less than or be flush to the minimum point of the first medium layer top surface.Subsequently
Densification processing is carried out to the part first medium layer and forms initial second dielectric layer, then is formed by initial second dielectric layer
Top surface be higher than or be flush to the top surface of the side wall.Even if the surface of the initial second dielectric layer has recessed
It falls into, follow-up after planarization, it is still flat to be formed by second medium layer surface.The bottom of the initial second dielectric layer
Portion surface is less than the top surface of the sidewall structure so that material layer described in subsequent planarization is until expose sidewall structure
When top surface, the top surface of the first medium layer is still covered by second dielectric layer completely.Also, described initial second
The density of dielectric layer is big compared with the density of the first medium layer, therefore, is more advantageous to the second dielectric layer formed after making planarization
Top surface it is smooth so that the better performances between the second dielectric layer isolation of semiconductor different components, to improve half
The performance of conductor structure.
In the semiconductor structure that technical solution of the present invention provides, it is located at the close of the second dielectric layer on the first medium layer
Degree is big compared with the density of the first medium layer, and the top surface of the second dielectric layer is smooth, the second dielectric layer isolation half
Better performances between conductor different components, to improve the performance of semiconductor structure.
Description of the drawings
Fig. 1 to Fig. 2 is a kind of structural schematic diagram of each step of the forming method of semiconductor structure；
Fig. 3 to Fig. 8 is the structural schematic diagram of each step of the forming method of the semiconductor structure of one embodiment of the invention.
Specific implementation mode
As described in background, the isolation performance of the dielectric layer in the semiconductor structure is bad.
Fig. 1 to Fig. 2 is a kind of structural schematic diagram of each step of the forming method of semiconductor structure.
Referring to FIG. 1, providing substrate, the substrate includes the first area A and the second area B, is had in the firstth area A substrates
First dummy gate structure 101, first dummy gate structure 101 include the first pseudo- grid side wall 102 and the first dummy gate layer (in figure
Do not mark), 101 top surface of the first dummy gate structure has the first mask layer (not marked in figure), the secondth area B bases
It includes 104 and second pseudo- grid of the second pseudo- grid side wall to have the second dummy gate structure 103, second dummy gate structure 103 on bottom
Pole layer (not marked in figure), 103 top surface of the second dummy gate structure has the second mask layer (not marked in figure), described
There is initial first medium layer in substrate, the first dummy gate structure 101 and the second dummy gate structure 103；It planarizes described first
Beginning first medium layer forms first and is situated between until exposing the top surface of 102 and second pseudo- grid side wall 104 of the first pseudo- grid side wall
Matter layer 105, the top surface of the first medium layer 105 is less than 102 and second pseudo- grid side wall 104 of the described first pseudo- grid side wall
Top surface.
Referring to FIG. 2, removal first dummy gate structure 101 forms the first opening, formed in first opening
First grid structure 107；It removes second dummy gate structure 103 and forms the second opening, form the in second opening
Two gate structures 108.
The material of the initial first medium layer includes：Silica；The technique for forming the initial first medium layer includes：
Fluid chemistry gas-phase deposition.
The material of first mask layer and the second mask layer includes：Silicon nitride.
However, poor using semiconductor structure performance prepared by the above method, reason is：
In the above method, the firstth area A is used to form short channel area, and the secondth area B is used to form long channel region, institute
The device spacing for stating short channel area is small compared with the device spacing of long channel region.In order to form good first dummy gate structure of pattern
101 and second dummy gate structure 103, it is located at the thickness of first mask layer in first dummy gate structure 101 compared with position
It is thin in the thickness of the second mask layer in second dummy gate structure 103.
Later use chemical mechanical milling tech planarizes the initial first medium layer, until it is pseudo- to expose described first
The top surface of grid side wall 102 and the second pseudo- grid side wall 104, forms the first medium layer 105.Planarizing described initial the
During one dielectric layer, first mask layer and the second mask layer are also removed.Due to first mask layer and second
The density of mask layer is big compared with the density of the initial first medium layer, therefore, planarization remove the initial first medium layer,
During first mask layer and the second mask layer, machinery of the flatening process process to the initial first medium layer
Grinding rate is more than the mechanical lapping rate to first mask layer and the second mask layer, so that using flatening process
The top surface of the first medium layer 105 of formation has recess.
Specifically, in the planarization removal part initial first medium layer, the first mask layer and the second mask layer
In the process, since the thickness of first mask layer is thin compared with the thickness of the second mask layer, when first mask layer is complete
When full removal, second mask layer still has residual.When first mask layer is completely removed, it is located at the first area A and the
The top surface of the first medium floor 105 of two area B generates recess.After removing first mask layer, in order to remove second
Mask layer, continues the initial first medium layer described to part and the second mask layer planarizes, and the first of the second area B is caused to be situated between
The recess of matter layer surface is deepened.Therefore, when the second mask layer is completely removed, it is located at the first medium floor of the firstth area A
105 top surfaces have the first recess, have the second recess positioned at 105 top surface of first medium of the second area B, and described
The depth capacity of first recess is less than the depth capacity of the second recess.
First grid structure 107 subsequently is formed in first opening, second grid is formed in second opening
Structure 108.The forming step of the first grid structure 107 and second grid structure 108 includes：In first opening, the
Two opening in and first medium layer 105 on forming material layer；Planarization is carried out to the material layer until exposing the first puppet
The top surface of grid side wall 102 and the second pseudo- grid side wall 104.When being planarized to the material layer, it is located at the first recess
With the easy deposition materials layer of the second recess so that the performance of 105 isolation of semiconductor different components of the first medium layer is poor, into
And influence the performance of semiconductor structure.
In order to solve the above technical problems, technical solution of the present invention provides a kind of forming method of semiconductor structure, including：It carries
For substrate, there is device architecture, the device architecture includes initial sidewall structure in the substrate；In the substrate, device junction
The top surface of structure and initial sidewall structure forms initial first medium layer；The initial first medium layer is planarized, until
The top surface of initial sidewall structure is exposed, first medium layer is formed；The initial sidewall structure in removal part forms sidewall structure,
The top surface of the sidewall structure is less than or is flush to the minimum point of the first medium layer top surface；Form the side
After wall construction, densification processing is carried out to the part first medium layer and forms initial second dielectric layer, described initial second
The bottom surface of dielectric layer is less than the top surface of the sidewall structure, and the density of the initial second dielectric layer is more than described
The density of first medium layer；It is formed after the initial second dielectric layer, removal devices structure forms hatch frame；It is opened described
Forming material layer in the interior and initial second dielectric layer of mouth structure；It planarizes the material layer and initial second dielectric layer is straight
To the top surface for exposing sidewall structure, gate structure and second dielectric layer are formed.
In the method, by removing the initial sidewall structure in part, the top surface for being formed by sidewall structure is made to be less than
Or it is flush to the minimum point of the first medium layer top surface.Subsequently the part first medium layer is carried out at densification
Reason forms initial second dielectric layer, then the top surface for being formed by initial second dielectric layer is higher than or is flush to the side wall
Top surface.Even if the surface of the initial second dielectric layer has recess, follow-up after planarization, it is formed by the
Second medium layer surface is still flat.The bottom surface of the initial second dielectric layer is less than the top surface of the sidewall structure,
So that material layer described in subsequent planarization until expose sidewall structure top surface when, the top table of the first medium layer
Face is covered by second dielectric layer completely.Also, the density of the initial second dielectric layer is big compared with the density of the first medium layer,
Therefore, the top surface for being more advantageous to the second dielectric layer formed after making planarization is smooth so that the second dielectric layer isolation
Better performances between semiconductor different components, to improve the performance of semiconductor structure.
It is understandable to enable above-mentioned purpose, feature and the advantageous effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
Fig. 3 to Fig. 8 is the structural schematic diagram of each step of the forming method of the semiconductor structure of one embodiment of the invention.
Referring to FIG. 3, providing substrate 200, the substrate 200 has device architecture (not marked in figure), the device junction
Structure includes initial sidewall structure (not marked in figure)；It is formed just on the substrate 200, device architecture and initial sidewall structure
Beginning first medium layer 201.
In the present embodiment, the substrate 200 includes：Substrate 202 and the fin 203 on substrate 202.Other
In embodiment, the substrate is planar substrate.
The forming step of the substrate 200 includes：Initial substrate is provided；The graphical initial substrate, forms substrate 202
With the fin 203 on substrate 202.
In the present embodiment, the material of the initial substrate is silicon.In other embodiments, the initial substrate can also be
The semiconductor substrates such as germanium substrate, silicon-Germanium substrate, silicon-on-insulator or germanium on insulator.
The substrate 200 further includes isolation structure (not marked in figure), and the isolation structure is for realizing semiconductor difference
Electrical isolation between device.
In the present embodiment, the substrate 200 includes the first area I and the second area II, and firstth area I is used to form short ditch
Road device, secondth area II are used to form long channel device.
In the present embodiment, the device architecture includes：Positioned at first dummy gate structure 204 in firstth area I and position
The second dummy gate structure 205 in secondth area II, and first dummy gate structure 204 is along the size of orientation
Less than the second dummy gate structure 205 along the size of orientation.
In the present embodiment, further include：The is formed in the fin 203 of 204 both sides of the first dummy gate structure
One source and drain doping area 208；The second source and drain doping area 209 is formed in the fin 203 of 205 both sides of the second dummy gate structure.
First dummy gate structure 204 is referred to along the size of orientation：First dummy gate structure 204
Size on 208 line direction of both sides the first source and drain doping area.
Second dummy gate structure 205 is referred to along the size of orientation：Second dummy gate structure 205
Size on 209 line direction of both sides the second source and drain doping area.
In the present embodiment, the initial sidewall structure includes：Initial first side wall 206 and initial second side wall 207.
First dummy gate structure 204 includes：First pseudo- gate dielectric layer, the first puppet on the first pseudo- gate dielectric layer
Grid layer and initial first side wall 206 positioned at the described first pseudo- gate dielectric layer side wall and the first dummy gate layer side wall.
Second dummy gate structure 205 includes：Second pseudo- gate dielectric layer, the second puppet on the second pseudo- gate dielectric layer
Grid layer and initial second side wall 207 positioned at the described second pseudo- gate dielectric layer side wall and the second dummy gate layer side wall.
The consistency of thickness of initial first side wall 206 and initial second side wall 207.
In the present embodiment, there is the top surface of first dummy gate structure 204 first mask layer (not marked in figure
Go out), first mask layer forms the mask of first dummy gate layer as etching.Second dummy gate structure 205
There is top surface the second mask layer (not marked in figure), second mask layer to form second dummy gate layer as etching
Mask, and first mask layer thickness is thin compared with the second mask layer thickness.
First mask layer thickness reason thin compared with the second mask layer thickness include：Firstth area I is used to form short
Channel region, secondth area II are used to form long channel region, between the device of the longer channel region of device spacing in the short channel area
Away from small.In order to form good first dummy gate structure, 204 and second dummy gate structure 205 of pattern, it is located at the described first pseudo- grid
Thickness of the thickness of the first mask layer in pole structure 204 compared with the second mask layer in second dummy gate structure 205
It is thin.
The material of first mask layer and second mask layer includes：Silicon nitride.
It is formed before the initial first medium layer 201, further includes：It is pseudo- to first dummy gate structure 204 and second
The fin 203 of 205 both sides of gate structure carries out that ion implanting is lightly doped；It is described to be lightly doped after ion implanting, described
The first source and drain doping area 208 is formed in the fin 203 of first dummy gate structure, 204 both sides；In the second dummy gate structure 205
The second source and drain doping area 209 is formed in the fin 203 of both sides；Form first source and drain doping area 208 and the second source and drain
After doped region 209, in the substrate 200, the first source and drain doping area 208, the second source and drain doping area 209, first mask
Stop-layer 210 is formed on layer and the second mask layer.
The forming step in first source and drain doping area 208 includes：Using etching technics in first dummy gate structure
Opening is formed in the fin 203 of 204 both sides；Epitaxial layer is formed using selective epitaxial depositing operation in the opening；Institute
Doped p-type ion or N-type ion in epitaxial layer are stated, first source and drain doping area 208 is formed.
The forming step in second source and drain doping area 209 includes：Using etching technics in second dummy gate structure
Opening is formed in the fin 203 of 205 both sides；Epitaxial layer is formed using selective epitaxial depositing operation in the opening；Institute
Doped p-type ion or N-type ion in epitaxial layer are stated, second source and drain doping area 209 is formed.
The material of the stop-layer 210 includes：Silicon nitride.
The material of the initial first medium layer 201 includes：Silica.The formation work of the initial first medium layer 201
Skill includes：Fluid chemistry gas-phase deposition.The initial first medium layer 201 is for realizing between semiconductor different components
Electrical isolation.
Referring to FIG. 4, planarizing the initial first medium layer 201 until exposing the top of the initial sidewall structure
Surface forms first medium layer 211.
During planarizing the initial first medium layer 201, further include：Remove the first mask layer and the second mask
Layer.
The flatening process includes：Chemical mechanical milling tech.Due to first mask layer and the second mask layer
Density is big compared with the density of the initial first medium layer 201, therefore, the part initial first medium layer is removed in planarization
201, during the first mask layer and the second mask layer, the flatening process is to the initial first medium layer 201
Mechanical lapping rate is more than the mechanical lapping rate to first mask layer and the second mask layer so that uses flatening process
The top surface of the first medium layer 211 of formation has recess.
Firstth area, I first medium floor, 211 top surface has the first recess, II first medium floor of the secondth area, 211 top table
Face has the second recess.It is described first recess depth capacity be：H1, it is described second recess depth capacity be：H2, and H1 is small
In H2.
The depth capacity H1 of first recess is referred to：Top surface positioned at I first medium floor 211 of the firstth area is to
The full-size of the top surface of one pseudo- grid structure 204.
The depth capacity H2 of second recess is referred to：Top surface positioned at II first medium floor 211 of the secondth area arrives
The full-size of the top surface of second pseudo- grid structure 205.
H1 is less than H2, and H1 includes less than the reason of H2：When first mask layer is completely removed, it is located at described first
Area I and II first medium floor of the secondth area, 211 top surface are recessed.After removing first mask layer, in order to complete
The second mask layer is removed, 201 and second mask layer of initial first medium layer is continued to planarize, leads to the secondth area
The recess of II 211 top surface of first medium layer is deepened.Therefore, when the second mask layer is completely removed so that first is recessed
Sunken depth capacity H1 is less than the depth capacity H2 of the second recess.
The depth of depth capacity H2 of second recess is：3 nanometers~10 nanometers.
The depth capacity H2 of second recess determines that the follow-up initial sidewall structure is pushed up along perpendicular to the fin 203
Removal amount in portion's surface direction.
Referring to FIG. 5, the initial sidewall structure in removal part forms sidewall structure, the sidewall structure top surface be less than or
Person is flush to the minimum point of 211 top surface of first medium layer.
Partly initially the technique of sidewall structure includes for removal：Isotropic dry etch process or wet-etching technology.
The technological parameter of the isotropic dry etch process includes：Etching gas includes：CH3F、CH2F2And O2,
In, CH3The flow of F is：10 standard milliliters/minute~500 standard milliliters/minute, CH2F2Flow be：10 standard milliliters/point
Clock~200 standard milliliters/minute, O2Flow be：10 standard milliliters/minute~300 standard milliliters/minute, pressure are：2 millis
Hold in the palm~50 millitorrs, power：100 watts~200 watts.
The minimum point of 211 top surface of first medium layer is located at the position at the second recess depth capacity H2.
The initial sidewall structure is by described second along the removal amount on 203 top surface direction of the fin
The depth capacity H2 of recess is determined.
During the initial sidewall structure in removal part, the initial sidewall structure is along perpendicular to 203 top of the fin
Removal amount in surface direction is：3 nanometers~10 nanometers.The initial sidewall structure is selected to be pushed up along perpendicular to the fin 203
The meaning of removal amount in portion's surface direction is：The initial sidewall structure is along perpendicular to 203 top surface side of the fin
Upward removal amount is less than 3 nanometers, and second dielectric layer, the second dielectric layer are subsequently formed on the first medium layer 211
Top surface when forming gate structure the still material layer of residual fraction, to influence the influence isolation of second dielectric layer
Can, and then influence the performance of semiconductor structure；If the initial sidewall structure is along perpendicular to 203 top surface direction of the fin
On removal amount be more than 10 nanometers, the height for the gate structure being subsequently formed is too low, is unfavorable for the performance of semiconductor structure.
The sidewall structure includes：First side wall 212 and the second side wall 213.
The forming step of first side wall 212 includes：Initial first side wall 206 in part is removed, the first side wall is formed
212,212 top surface of the first side wall is less than or is flush to the minimum point of 211 top surface of first medium layer.
The forming step of second side wall 213 includes：Initial second side wall 207 in part is removed, the second side wall is formed
213,213 top surface of the second side wall is less than or is flush to the minimum point of 211 top surface of first medium layer.
The sidewall structure top surface is less than or is flush to the minimum point of 211 top surface of first medium layer,
Purpose is：In order to ensure subsequently on the first medium layer 211 formed second dielectric layer when, the top of the second dielectric layer
Portion surface residual without material layer when forming gate structure to improve the isolation performance of second dielectric layer, and then improves half
The performance of conductor structure.
Referring to FIG. 6, being formed after the sidewall structure, densification processing is carried out to the part first medium layer 211
Initial second dielectric layer 214 is formed, the bottom surface of the initial second dielectric layer 214 is less than the top table of the sidewall structure
Face, and the density of the initial second medium 214 is more than the density of the first medium layer 211.
Densification processing carried out to the first medium layer 211 form the technique of initial second dielectric layer 214 include：High temperature
Plasma-treating technology；The technological parameter of the high-temperature plasma treatment process includes：Gas includes：Helium, helium
Flow is：100 standard milliliters/minute~1000 standard milliliters/minute, temperature：300 degrees Celsius~500 degrees Celsius, power 100
Watt~1000 watts, pressure：The support of 0.2 support~5.
The principle of density that the density of the initial second medium 214 is more than the first medium layer 211 includes：Described
Under high-temperature plasma treatment process, part 211 high temperature of first medium layer recombinates to form larger initial second Jie of density
Matter layer 214.
The minimum thickness of the initial second dielectric layer 214 is：5 nanometers~20 nanometers, select the initial second medium
The meaning of 214 minimum thickness of layer is：If the minimum thickness of the initial second dielectric layer 214 is less than 5 nanometers, subsequently formed
When gate structure, when carrying out planarization process to the material layer in the initial second dielectric layer 214, the initial second medium
214 thickness of layer are excessively thin so that the initial second dielectric layer 214 is inadequate to the protection of first medium layer 211.That is, described
Initial second dielectric layer is flattened after removal, also flattens the removal part first medium layer 211.Due to described first
Dielectric layer 211 is formed by fluid chemistry gas-phase deposition, and therefore, 211 quality of first medium layer is softer.Flat
During smoothization removes the part first medium layer 211, the first medium layer 211 is easily being subsequently formed gate structure two
Side is recessed, and has the isolation performance of the first medium layer 211 of recess poor, is unfavorable for improving the performance of semiconductor structure；
If the minimum thickness of the initial second dielectric layer 214 is more than 20 nanometers, increase first medium layer described in densification process part
211 technology difficulty.
The bottom surface of the initial second dielectric layer 214 is less than the top surface of the sidewall structure, and described initial
The density of second dielectric layer 214 is more than the density of the first medium layer 211 so that the second of subsequent planarization material layer formation
The top surface planarization of dielectric layer 214 is good, so that the electric isolation performance of the second dielectric layer 214 is good, to carry
The performance of high semiconductor structure.
Referring to FIG. 7, removal devices structure forms hatch frame.
The hatch frame includes：First opening 215 and the second opening 216, first opening, 215 and second opening
216 forming step includes：First dummy gate structure 204 is removed, the first opening 215 is formed；Remove the described second pseudo- grid
Pole structure 205 forms the second opening 216.
The technique for removing the first dummy gate structure 204 and the second dummy gate structure 205 includes：Anisotropic dry etching work
Skill or dry etch process are combined with wet-etching technology.
The anisotropic dry etch process includes with the technological parameter that wet-etching technology is combined：Etching gas packet
It includes：Hydrogen bromide, chlorine and oxygen, wherein the flow of hydrogen bromide is：10 standard milliliters/minute~500 standard milliliters/minute, chlorine
The flow of gas is：The flow of 10 standard milliliters/minute~500 standard milliliters/minute, oxygen is：2 standard milliliters/minute~100
Standard milliliters/minute, power：100 watts~1000 watts, etching agent includes：The concentration proportion of diluted hydrofluoric acid, hydrofluoric acid and water is：
50：1~2000：1, the mass fraction of tetramethylammonium hydroxide is：0.5%~5%.
Referring to FIG. 8, being formed after the hatch frame, the deposition materials layer in the hatch frame, described in planarization
The initial second dielectric layer of material layer and part 214 forms gate structure and the until expose the top surface of sidewall structure
Second medium layer 219.
The gate structure includes：First grid structure 217 and second grid structure 218, the first grid structure 217
Forming step with second grid structure 218 includes：In 215, second opening 216 of the first opening and initial second is situated between
Forming material layer on matter layer 214；The material layer is planarized until exposing the top surface of sidewall structure, in the first opening
First grid structure 217 is formed in 215, and second grid structure 218 is formed in second opening 216.
The material of the material layer includes：The material of metal layer, the metal layer includes：Tungsten.
The technique of the planarization material layer includes：Chemical mechanical milling tech.
The top surface planarization of the second dielectric layer 219 is good so that the isolation performance of the second dielectric layer compared with
It is good, to improve the performance of semiconductor structure.
To sum up, in the present embodiment, by removing the initial sidewall structure in part, make the top table for being formed by sidewall structure
Face is less than or is flush to the minimum point of the first medium layer top surface.Subsequently the part first medium layer is carried out close
Realification processing forms initial second dielectric layer, then the top surface for being formed by initial second dielectric layer is higher than or is flush to described
The top surface of side wall.Even if the surface of the initial second dielectric layer has recess, follow-up after planarization, institute's shape
At second medium layer surface it is still flat.The bottom surface of the initial second dielectric layer is less than the top of the sidewall structure
Surface so that material layer described in subsequent planarization until expose sidewall structure top surface when, the first medium layer
Top surface is still covered by second dielectric layer completely.Also, the density first medium of the initial second dielectric layer
The density of layer is big, and therefore, the top surface for being more advantageous to the second dielectric layer formed after making planarization is smooth so that described second
Better performances between dielectric layer isolation of semiconductor different components, to improve the performance of semiconductor structure.
The embodiment of the present invention also provide it is a kind of semiconductor structure is formed by using the above method, referring to FIG. 8, including：
There is in the substrate 200 substrate 200 gate structure, the gate structure to have sidewall structure, the side wall knot
The top surface of structure is flushed with the top surface of the gate structure；
First medium layer 211 (see Fig. 5) in the substrate 200, the top surface of the first medium layer 211 are low
In the top surface of the gate structure；
Second dielectric layer 219 on the first medium layer 211, the top surface of the second dielectric layer 219 with
The top surface of the gate structure flushes.
To sum up, in the present embodiment, the density more described first for being located at the second dielectric layer on the first medium layer is situated between
The density of matter layer is big, and the top surface of the second dielectric layer is smooth, therefore, the second dielectric layer isolation of semiconductor difference device
Better performances between part, to improve the performance of semiconductor structure.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, there is device architecture in the substrate, the device architecture includes initial sidewall structure；
Initial first medium layer is formed in the top surface of the substrate, device architecture and initial sidewall structure；
The initial first medium layer is planarized, until exposing the top surface of initial sidewall structure, forms first medium layer；
The initial sidewall structure in removal part forms sidewall structure, and the top surface of the sidewall structure is less than or is flush to described
The minimum point of first medium layer top surface；
It is formed after the sidewall structure, carrying out densification processing to the part first medium layer forms initial second medium
Layer, the bottom surface of the initial second dielectric layer are less than the top surface of the sidewall structure, and the initial second medium
The density of layer is more than the density of the first medium layer；
It is formed after the initial second dielectric layer, removal devices structure forms hatch frame；
Forming material layer in the hatch frame and in initial second dielectric layer；
The material layer and initial second dielectric layer are planarized until exposing the top surface of sidewall structure, forms grid knot
Structure and second dielectric layer.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate includes：Firstth area and
Secondth area.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the device architecture includes being located at institute
State first dummy gate structure in the firstth area and the second dummy gate structure positioned at secondth area；First dummy gate structure
Including：First pseudo- gate dielectric layer and the first dummy gate layer on the described first pseudo- gate dielectric layer；Second dummy grid
Structure includes：Second pseudo- gate dielectric layer and the second dummy gate layer on the described second pseudo- gate dielectric layer.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that first dummy gate structure is along ditch
The size of road length direction is less than size of second dummy gate structure along orientation.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that the top of first dummy gate layer
Surface has the first mask layer；The top surface of second dummy gate layer has the second mask layer；The first mask thickness
Degree is thin compared with the second mask layer thickness.
6. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the initial sidewall structure includes just
Begin the first side wall and initial second side wall, and initial first side wall is located at the described first pseudo- gate dielectric layer and the first dummy gate layer
Side wall, initial second side wall is located at the side wall of the described second pseudo- gate dielectric layer and the second dummy gate layer.
7. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the planarization initial first medium
During layer, further include：Remove the first mask layer and the second mask layer.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the initial first medium layer
Material includes：Silica.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that the shape of the initial first medium layer
Include at technique：Fluid chemistry gas-phase deposition.
10. the forming method of semiconductor structure as described in claim 1, which is characterized in that planarization described initial first is situated between
The technique of matter layer includes：Chemical mechanical milling tech.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that the removal initial sidewall structure in part
Technique include：Isotropic dry etch process or wet-etching technology.
12. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that the isotropic dry etching
The technological parameter of technique includes：Etching gas includes：CH3F、CH2F2And O2, wherein CH3The flow of F is：10 standard milliliters/point
Clock~500 standard milliliters/minute, CH2F2Flow be：10 standard milliliters/minute~200 standard milliliters/minute, O2Flow
For：10 standard milliliters/minute~300 standard milliliters/minute, pressure are：The millitorr of 2 millitorrs~50, power：100 watts~200 watts.
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that the initial sidewall structure is along vertical
It is in the removal amount on the direction on the base top surface directly：3 nanometers~10 nanometers.
14. the forming method of semiconductor structure as described in claim 1, which is characterized in that carried out to the first medium layer
The technique that densification processing forms initial second dielectric layer includes：High-temperature plasma treatment process；The high-temperature plasma
The technological parameter for the treatment of process includes：Gas includes：The flow of helium, helium is：The standard of 100 standard milliliters/minute~1000
Ml/min, temperature：300 degrees Celsius~500 degrees Celsius, 100 watts~1000 watts of power, pressure：The support of 0.2 support~5.
15. the forming method of semiconductor structure as described in claim 1, which is characterized in that the minimum of the second dielectric layer
Thickness is：5 nanometers~20 nanometers.
16. the forming method of semiconductor structure as described in claim 1, which is characterized in that planarize the material layer and
Initially the technique of second dielectric layer includes：Chemical machinery polishes technique.
17. a kind of being formed by semiconductor structure using such as any one of claim 1 to 16 method, which is characterized in that including：
Substrate has gate structure in the substrate, and the gate structure includes sidewall structure, the top table of the sidewall structure
Face is flushed with the top surface of the gate structure；
First medium layer in the substrate, the top surface of the first medium layer are less than the top of the sidewall structure
Surface；
Second dielectric layer on the first medium layer, the top surface of the second dielectric layer and the sidewall structure
Top surface flushes.
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