CN107591398A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN107591398A CN107591398A CN201610527850.6A CN201610527850A CN107591398A CN 107591398 A CN107591398 A CN 107591398A CN 201610527850 A CN201610527850 A CN 201610527850A CN 107591398 A CN107591398 A CN 107591398A
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Abstract
A kind of semiconductor structure and forming method thereof, methods described includes：Substrate is provided；Grid structure is formed in substrate；Side wall is formed in the side wall of grid structure, the material of side wall is low k dielectric materials；Nitrating layer is formed on side wall, the atom percentage content of nitrogen is more than the atom percentage content of nitrogen in side wall in nitrating layer；After forming nitrating layer, source and drain doping area is formed in the substrate of grid structure both sides；Form covering grid structure and the interlayer dielectric layer of substrate；Contact hole plug is formed in interlayer dielectric layer, contact hole plug is in contact with source and drain doping area.The present invention forms nitrating layer on side wall; when forming contact hole plug; nitrating layer plays a protective role to side wall; the etch rate to form the etching technics of contact hole plug to side wall can be reduced; so as to the phenomenon for avoiding the side wall from being lost or grid structure exposes; to avoid the contact hole plug and grid structure that short circuit occurs, and then improve the electric property of semiconductor devices.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
With the continuous development of semiconductor process technique, the development trend that semiconductor technology node follows Moore's Law is continuous
Reduce.In order to adapt to the reduction of process node, it has to constantly shorten the channel length of MOSFET FETs.Channel length
Shorten the tube core density with increase chip, increase the benefits such as the switching speed of MOSFET FETs.
However, with the shortening of device channel length, the distance between device source electrode and drain electrode also shortens therewith, so
Grid is deteriorated to the control ability of raceway groove so that sub-threshold leakage (subthreshold leakage) phenomenon, i.e., it is so-called short
Channelling effect (SCE：Short-channel effects) it is easier to occur.
Therefore, in order to preferably adapt to the scaled requirement of device size, semiconductor technology gradually starts from plane
Transistor transient from mosfet transistor to the three-dimensional with more high effect, such as fin field effect pipe (FinFET).
In FinFET, grid can be at least controlled from both sides to ultra-thin body (fin), be had more much better than than planar MOSFET devices
Grid to the control ability of raceway groove, can be good at suppressing short-channel effect；And FinFET has more preferable relative to other devices
Existing production of integrated circuits technology compatibility.
But the performance of the semiconductor devices of prior art formation has much room for improvement.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, optimize the property of semiconductor devices
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided；Institute
State and grid structure is formed in substrate；Side wall is formed in the side wall of the grid structure, the material of the side wall is low k dielectric material
Material；Nitrating layer is formed on the side wall, the atom percentage content of nitrogen is more than the original of nitrogen in the side wall in the nitrating layer
Sub- degree；After forming the nitrating layer, source and drain doping area is formed in the substrate of the grid structure both sides；Formation is covered
Cover the grid structure and the interlayer dielectric layer of substrate；Contact hole plug, the contact hole are formed in the interlayer dielectric layer
Connector is in contact with the source and drain doping area.
Optionally, the relative dielectric constant of the side wall is 3.9 to 7.5.
Optionally, the material of the side wall is oxygen-enriched carbon silicon oxynitride.
Optionally, in the oxygen-enriched carbon silicon oxynitride, the atom percentage content of oxygen is 25% to 40%.
Optionally, the step of forming side wall and the nitrating layer includes：Form the conformal covering substrate and grid structure
Side wall film, the material of the side wall film is low k dielectric materials；Nitrating technique is carried out to the side wall film；Remove the substrate
Side wall film at the top of upper and grid structure, forms side wall, and formed and mixed on the side wall in the side wall of the grid structure
Nitrogen layer.
Optionally, the technique for forming the side wall film is atom layer deposition process.
Optionally, the presoma of the atom layer deposition process is oxygen-containing gas.
Optionally, the material of the side wall film is oxygen-enriched carbon silicon oxynitride, the technological parameter of the atom layer deposition process
Including：The presoma being passed through into ald room is the presoma containing Si, C, O and N, and the total gas flow rate of presoma is
10sccm to 1000sccm, technological temperature are 25 degrees Celsius to 600 degrees Celsius, and pressure is 1 millitorr to 500 millitorrs.
Optionally, the nitrating technique is plasma nitridation process.
Optionally, the technological parameter of the nitrating technique includes：Power is 1 watt to 500 watts, and pressure is 1 millitorr to 1000
Millitorr, process time are 5 seconds to 100 seconds, and reacting gas is nitrogen, and auxiliary gas is helium, and the gas flow of nitrogen is 10 marks
Quasi- milliliter is per minute per minute to 1000 standard milliliters, and the gas flow of helium is per minute to 1000 standards milli for 1 standard milliliters
Liter Per Minute.
Optionally, the thickness of the side wall is 10 angstroms to 100 angstroms.
Optionally, the semiconductor structure is fin field effect pipe；In the step of providing substrate, the substrate includes substrate
And protrude from the fin of the substrate；On the substrate formed grid structure the step of in, be developed across the fin and
Cover fin atop part and the grid structure of sidewall surfaces；Source and drain doping area is formed in the substrate of the grid structure both sides
The step of in, the source and drain doping area is formed in the fin of the grid structure both sides.
Optionally, the step of source and drain doping area is formed in the substrate of the grid structure both sides includes：Etching is positioned at institute
The fin of the segment thickness of grid structure both sides is stated, groove is formed in the fin；Form the stress of the full groove of filling
Layer, and the source and drain doping area is formed using auto-dope processing in situ during the stressor layers are formed；Or etching position
In the fin of the segment thickness of the grid structure both sides, groove is formed in the fin；Form the full groove of filling
Stressor layers；The stressor layers are doped with processing and forms the source and drain doping area.
Accordingly, the present invention also provides a kind of semiconductor structure, including：Substrate；Grid structure, in the substrate；
Side wall on the gate structure sidewall, the material of the side wall is low k dielectric materials；Nitrating on the side wall
Layer, the atom percentage content of nitrogen is more than the atom percentage content of nitrogen in the side wall in the nitrating layer；Source and drain doping area,
In the substrate of the grid structure both sides；Interlayer dielectric layer, cover the grid structure and the substrate；Positioned at the layer
Between contact hole plug in dielectric layer, the contact hole plug is in contact with the source and drain doping area.
Optionally, the relative dielectric constant of the side wall is 3.9 to 7.5.
Optionally, the material of the side wall is oxygen-enriched carbon silicon oxynitride.
Optionally, in the oxygen-enriched carbon silicon oxynitride, the atom percentage content of oxygen is 25% to 40%.
Optionally, the thickness of the side wall is 10 angstroms to 100 angstroms.
Optionally, the semiconductor structure also includes：Intrabasement stressor layers positioned at the grid structure both sides；It is described
Source and drain doping area is located in the stressor layers.
Optionally, the semiconductor structure is fin field effect pipe；The substrate includes substrate and protrudes from the lining
The fin at bottom；The grid structure is across the fin and covering fin atop part and sidewall surfaces；The source and drain doping area
In the fin of the grid structure both sides.
Compared with prior art, technical scheme has advantages below：
The present invention forms nitrating layer on side wall, and when forming contact hole plug, the nitrating layer plays to the side wall
Protective effect, the etch rate to form the etching technics of the contact hole plug to the side wall can be reduced, that is to say, that make
The etching technics is more than the etch rate to the side wall to the etch rate of interlayer dielectric layer；So as to avoid forming contact
In the technical process of hole connector, the side wall is made the material of the side wall by the phenomenon that even grid structure exposes is lost
Matter is stable, and can avoid the contact hole plug that short circuit occurs with grid structure, and then improves the electrical property of semiconductor devices
Energy.
In alternative, the semiconductor structure is fin field effect pipe, formed source and drain doping area the step of be included in grid
Stressor layers are formed in the fin of pole structure both sides；By forming nitrating layer on side wall, the nitrating layer can avoid being formed
In the technical process in the source and drain doping area, the stressor layers are formed on the side wall surface, so that the material of the side wall
Property is stable, and the material of the side wall has relatively low relative dielectric constant all the time；Therefore grid structure, positioned at the grid knot
The capacitance for the equivalent capacity that contact hole plug and the side wall above structure are formed is small, and then can improve semiconductor devices
Operating rate.
In alternative, the relative dielectric constant of the side wall is 3.9 to 7.5；Therefore grid structure can be made, positioned at institute
It is smaller to state the capacitance for the equivalent capacity that the contact hole plug above grid structure and the side wall are formed, is partly led so as to improve
The operating rate of body device.
Semiconductor structure of the present invention includes the nitrating layer on side wall；The nitrating layer can be inserted in contact hole
In the forming process of plug, the side wall is played a protective role, avoids the side wall by loss even grid structure exposure
Phenomenon, so that the material character of the side wall is stable, and avoids the contact hole plug that short circuit occurs with grid structure, and then
The operating rate and electric property of semiconductor devices can be improved.
Brief description of the drawings
Fig. 1 to Figure 12 be semiconductor structure of the present invention the embodiment of forming method one in each step counter structure schematic diagram.
Embodiment
From background technology, the electric property for the semiconductor devices that prior art is formed has much room for improvement.With reference to a kind of half
Conductor structure is analyzed its reason and is：
The semiconductor structure includes：Substrate；Grid structure in the substrate；Positioned at the gate structure sidewall
On side wall；Positioned at the intrabasement stressor layers in grid structure both sides；Source and drain doping area in the stressor layers；It is located at
The dielectric layer in substrate between the grid structure；The contact being in contact through the dielectric layer and with the source and drain doping area
Hole connector.
Wherein, the grid structure of semiconductor structure, the contact hole plug above the grid structure and positioned at institute
State and an equivalent capacity is formed between the side wall on gate structure sidewall, the operating rate of semiconductor devices and the equivalent capacity
The inversely proportional relation of capacitance.Therefore, the capacitance of the equivalent capacity is reduced, semiconductor devices can be effectively improved
Operating rate.The equivalent capacity is considered as capacity plate antenna structure, dielectric layer of the side wall between two flat boards, according to flat board electricity
The capacitance formula of appearance understands that the capacitance of the equivalent capacity and the relative dielectric constant of the material of the side wall are in direct ratio
Relation；Therefore, it is used as side by using low k dielectric materials (relative dielectric constant is less than the material of silicon nitride relative dielectric constant)
The material of wall, the capacitance of the equivalent capacity can be reduced.
But in the substrate of the grid structure both sides during epitaxial growth stressor layers, the easy extension life of stressor layers
It is longer than the side wall surface, is changed so as to easily cause the material property of low k side walls, relative Jie of the material of low k side walls
Electric constant becomes big, therefore the capacitance of above-mentioned equivalent capacity becomes big, then influences the operating rate of semiconductor devices.
In addition, the step of forming contact hole plug includes：The dielectric layer of the grid structure both sides is etched, in the medium
The contact hole for exposing the source and drain doping area is formed in floor；Contact hole plug is formed in the contact hole.The etching technics
The etch rate of the dielectric layer and low k side walls is closer to, therefore the etching technics easily caused quarter to the side wall
Erosion, or even the grid structure is exposed, so as to cause the contact hole plug that short circuit occurs with grid structure, and then cause half
The electric property of conductor device declines.
In order to solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：Base is provided
Bottom；Grid structure is formed on the substrate；Side wall is formed in the side wall of the grid structure, the material of the side wall is low
K dielectric materials；Nitrating layer is formed on the side wall, the atom percentage content of nitrogen is more than in the side wall in the nitrating layer
The atom percentage content of nitrogen；After forming the nitrating layer, source and drain doping area is formed in the substrate of the grid structure both sides；
Form the interlayer dielectric layer for covering the grid structure and substrate；Contact hole plug is formed in the interlayer dielectric layer, it is described
Contact hole plug is in contact with the source and drain doping area.
The present invention forms nitrating layer on side wall, and when forming contact hole plug, the nitrating layer plays to the side wall
Protective effect, the etch rate to form the etching technics of the contact hole plug to the side wall can be reduced, that is to say, that make
The etching technics is more than the etch rate to the side wall to the etch rate of interlayer dielectric layer；So as to avoid forming contact
In the technical process of hole connector, the side wall is made the material of the side wall by the phenomenon that even grid structure exposes is lost
Matter is stable, and can avoid the contact hole plug that short circuit occurs with grid structure, and then improves the electrical property of semiconductor devices
Energy.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 12 be semiconductor structure of the present invention the embodiment of forming method one in each step counter structure schematic diagram.
With reference to being cross-sectional views of the Fig. 1 along AA1 directions with reference to figure 1 and Fig. 2, Fig. 2, there is provided substrate (does not indicate).
The substrate provides technique platform to be subsequently formed semiconductor structure.
In the present embodiment, the semiconductor structure of formation is fin field effect pipe；Accordingly, the substrate includes：Substrate
100 and the discrete fin 110 that protrudes from the substrate 100.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be
Germanium, SiGe, carborundum, GaAs or gallium indium, the substrate can also be on silicon substrate or insulator on insulator
Germanium substrate.
The material of the fin 110 is identical with the material of the substrate 100.In the present embodiment, the material of the fin 110
For silicon.In other embodiment, the material of the fin can also be germanium, SiGe, carborundum, GaAs or gallium indium.
In another embodiment, the semiconductor structure of formation is planar transistor；Accordingly, the substrate is plane base
Bottom, the planar substrates are silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, on silicon-on-insulator substrate or insulator
Germanium substrate, glass substrate or III-V substrate (such as gallium nitride substrate or gallium arsenide substrate etc.), subsequently described flat
Grid structure is formed in the substrate of face.
Specifically, the substrate 100 is formed, the processing step of fin 110 includes：Initial substrate is provided；Described initial
Patterned hard mask layer 200 is formed in substrate；With the hard mask layer 200 for initial substrate described in mask etching, after etching
Initial substrate as substrate 100, the projection positioned at the surface of substrate 100 is as fin 110.
In the present embodiment, after forming the substrate 100 and fin 110, retain the hard mask layer positioned at the top of fin 110
200.The material of the hard mask layer 200 is silicon nitride, subsequently when carrying out planarization process technique, the hard mask layer 200
Top surface is used for the stop position for defining flatening process, plays a part of protecting the top of fin 110.
With reference to reference to figure 3, it is necessary to illustrate, the forming method also includes：Form the substrate 100 and fin 110
Afterwards, cushion oxide layer 101 is formed in the sidewall surfaces of the fin 110, for repairing the fin 110.
In the present embodiment, the cushion oxide layer 101 is formed by oxidation processes.
In oxidation processes, because the ratio surface of the faceted portions of the fin 110 protrusion is bigger, it is easier to by oxygen
Change, after subsequently removing the cushion oxide layer 101, not only layer is removed the defects of 110 surface of fin, and protrudes corner angle
Part is also removed, and makes that the surface of the fin 110 is smooth, and lattice quality is improved, and avoids the drift angle of fin 110 tip
Electric discharge problem, be advantageous to improve the performance of fin field effect pipe.
In the present embodiment, the cushion oxide layer 101 is also located at the surface of substrate 100, the cushion oxide layer 101
Material is silica.
With reference to reference to figure 4, it is also necessary to explanation, formed after the cushion oxide layer 101, the forming method is also wrapped
Include：Isolation structure 102 is formed on substrate 100 between the adjacent fin 110, the isolation structure 102 covers the fin
The partial sidewall surface in portion 110, and the top of the isolation structure 102 is less than the top of fin 110.
The isolation structure 102 plays a part of being electrically isolated adjacent fin 110.In the present embodiment, the isolation structure 102
Material be silica.In other embodiments, the material of the isolation structure can also be silicon nitride or silicon oxynitride.
Specifically, the step of forming isolation structure 102 includes：In the cushion oxide layer 101 formed forerunner every
From film, the top top (as shown in Figure 3) higher than the hard mask layer 200 of forerunner's barrier film；To forerunner's barrier film
The first annealing process is carried out, forerunner's barrier film is converted into barrier film；Grinding is removed higher than the top of hard mask layer 200
Barrier film；The barrier film of segment thickness is removed to form isolation structure 102；Remove the hard mask layer 200.
In order to improve the filling perforation for the technique to form the barrier film (gap-filling) ability, in the present embodiment, using stream
Dynamic property chemical vapor deposition method (FCVD, Flowable CVD) forms forerunner's barrier film.In another embodiment, may be used also
With using high vertical wide than chemical vapor deposition method (HARP CVD) formation forerunner's barrier film.
It should be noted that in the step of removing the barrier film of segment thickness, also remove higher than the isolation structure 102
Cushion oxide layer 101.
With reference to figure 5, Fig. 5 is cross-sectional views of the Fig. 4 along fin bearing of trend (as shown in BB1 directions in Fig. 1),
Grid structure (not indicating) is formed in the substrate.
In the present embodiment, the grid structure covers the atop part surface of fin 110 and side across the fin 110
Wall surface.
In the present embodiment, the grid structure is pseudo- grid structure, including pseudo- gate oxide 111 and pseudo- gate electrode layer 112；Institute
State grid structure and taken up space position to be subsequently formed metal gate structure.
The material of the pseudo- gate oxide 111 is silica, and the material of the pseudo- gate electrode layer 112 is polysilicon, aoxidized
Silicon, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.In the present embodiment, the pseudo- gate electrode
The material of layer 112 is polysilicon.
Specifically, the step of forming the grid structure includes：Pseudo- gate oxide 111 is formed on the surface of fin 110；
Pseudo- gate electrode film is formed on the pseudo- surface of gate oxide 111；Planarization process is carried out to the pseudo- gate electrode film；In the puppet
Gate electrode film surface forms graph layer 210；It is mask with the graph layer 210, the graphical pseudo- gate electrode film, in the puppet
The surface of gate oxide 111 forms pseudo- gate electrode layer 112；Remove the graph layer 210.
In the present embodiment, the graph layer 210 is hard mask layer, and the material of the graph layer 210 is silicon nitride.
It should be noted that in another embodiment, the grid structure can also be metal gate structure, the grid
The material of structure includes Al, Cu, Ag, Au, Pt, Ni, Ti or W.
With reference to reference to figure 6 to Fig. 8, side wall 121 is formed in the side wall of the grid structure (not indicating) (such as Fig. 8 institutes
Show), the material of the side wall 121 is low k dielectric materials；Nitrating layer 141, the nitrating layer 141 are formed on the side wall 121
The atom percentage content of middle nitrogen is more than the atom percentage content of nitrogen in the side wall 121.
The side wall 121 is used for as the injection mask for being subsequently formed source and drain doping area, also acts as the protection grid knot
The effect of structure side wall；Wherein, low k dielectric materials refer to that relative dielectric constant is less than the material of silicon nitride relative dielectric constant.
In the present embodiment, the relative dielectric constant of the side wall 121 is 3.9 to 7.5.
The nitrating layer 141 is used to play a protective role to the side wall 121.
The side wall 121, grid structure and the contact hole plug composition one being subsequently formed above the grid structure
Individual equivalent capacity；The equivalent capacity is considered as capacity plate antenna structure, dielectric layer of the side wall 121 between two flat boards,
It can be seen from the capacitance formula of capacity plate antenna, the capacitance of the equivalent capacity and the relative dielectric of the material of side wall 121
Constant direct proportionality；Therefore, by using the low k dielectric materials that relative dielectric constant is 3.9 to 7.5 as the side wall
121 material, the capacitance of the equivalent capacity can be significantly reduced.
In the present embodiment, the material of the side wall 121 is oxygen-enriched carbon silicon oxynitride, and the thickness of the side wall 121 is 10 angstroms
To 100 angstroms.Wherein, the oxygen-enriched carbon silicon oxynitride refers to the higher carbon silicon oxynitride of oxygen atom percentage content.
It should be noted that the atom percentage content of oxygen is higher, the relative dielectric constant of the side wall 121 is lower；For
The guarantee side wall 121 has a relatively low relative dielectric constant, in the oxygen-enriched carbon silicon oxy-nitride material, the atomic percent of oxygen
It is more unsuitable than content too low；The atom percentage content of oxygen is also unsuitable too high, and otherwise easily the material character of the side wall 121 is produced
Raw harmful effect.Therefore, in the present embodiment, in the oxygen-enriched carbon silicon oxy-nitride material, the atom percentage content of oxygen is 25%
To 40%.
Specifically, the step of forming the side wall 121 and nitrating layer 141 includes：Form the conformal covering substrate and grid
The side wall film 120 (as shown in Figure 6) of pole structure, the material of the side wall film 120 is low k dielectric materials；To the side wall film 120
Carry out nitrating technique 130 (as shown in Figure 7)；The side wall film 120 in the substrate and at the top of grid structure is removed, in the grid
Side wall 121 is formed in the side wall of structure.
In the present embodiment, the technique for forming the side wall film 120 is atom layer deposition process.Specifically, the atomic layer
The presoma of depositing operation is oxygen-containing gas；So as to advantageously reduce the relative dielectric constant of the side wall 121.
In the present embodiment, the material of the side wall 121 is oxygen-enriched carbon silicon oxynitride；Accordingly, the ald work
The technological parameter of skill includes：The presoma being passed through into ald room is the presoma containing Si, C, O and N.
It should be noted that the technological temperature of the atom layer deposition process is unsuitable too low, it is also unsuitable too high.Work as process warm
When spending low, easily cause the deposition velocity of each depositing operation excessively slow, so as to cause the thinner thickness of the side wall film 120,
Or need to increase the process time to reach target thickness value, so as to reduce the formation efficiency of the side wall film 120；When the work
When skill temperature is too high, easily cause the thermal decomposition of the presoma, so as to introduce the phenomenon of similar chemical vapor deposition, Jin Erying
The purity and step coverage of the side wall film 120 are rung, finally reduces the formation quality of the side wall film 120.Therefore, this implementation
In example, technological temperature is 25 degrees Celsius to 600 degrees Celsius.
In the present embodiment, the oxygen-containing gas is N2O or O2, for being used as the presoma containing O.Specifically, institute is formed
The chemical equation for stating side wall film 120 is：SiCnHm+NH3+N2O(or O2)→SiCO1+xN+N2。
By the presoma containing O, under hyperbaric environment, the low k sides with higher oxygen atom percentage content are formed
Wall film 120, and the relative dielectric constant of the side wall film 120 is smaller.Specifically, chamber pressure is 1 millitorr to 500 millitorrs.
Technological temperature and chamber pressure based on the setting, the total gas flow rate of presoma is set in zone of reasonableness value
It is interior, so as to ensure the high-purity of the side wall film 120 and good step spreadability, and meet the thickness of the side wall film 120
Process requirements.Therefore, in this implementation, the total gas flow rate of presoma is 10sccm to 1000sccm.
In the present embodiment, by nitrating technique 130, by N ion implantings to the surface of side wall film 120, so that described
The surface of side wall film 120 forms nitrating film 140 (as shown in Figure 7)；After being subsequently formed nitrating layer 141, the nitrating layer 141 be used for pair
The side wall 121 plays a protective role.
Specifically, the nitrating technique 130 is plasma nitridation process.The technique ginseng of the plasma nitridation process
Number includes：Power is 1 watt to 500 watts, and pressure is 1 millitorr to 1000 millitorrs, and the process time is 5 seconds to 100 seconds, and reacting gas is
Nitrogen, auxiliary gas are helium.
It should be noted that the gas flow of nitrogen is unsuitable very few, it is unsuitable excessive.If the gas flow of nitrogen is very few,
The atom percentage content of nitrogen is too low in the nitrating film 140, i.e., the atom percentage content mistake of nitrogen in described nitrating layer 141
Low, the protective effect of 141 pairs of the nitrating layer side wall 121 is not obvious enough described in subsequent technique；If the gas stream of nitrogen
Amount is excessive, and the atom percentage content of nitrogen is too high in the nitrating film 140, i.e., the atomic percent of nitrogen in described nitrating layer 141
Too high levels, easily the material property of the side wall 121 is had undesirable effect on the contrary.Therefore, in the present embodiment, the gas of nitrogen
Body flow is that 10 standard milliliters are per minute per minute to 1000 standard milliliters.
It should also be noted that, the gas flow of helium can have an impact to the atom percentage content of nitrogen；Therefore, helium
Gas flow also need control in the reasonable scope.In the present embodiment, the gas flow of helium is per minute extremely for 1 standard milliliters
1000 standard milliliters are per minute.
In the present embodiment, using without mask etching technique, remove in the substrate (not indicating) and grid structure (is not marked
Show) at the top of side wall film 120 (as shown in Figure 7), in the side wall of the grid structure formed side wall 121.
It should be noted that no mask etching technique is used also to remove institute to be formed in the technical process of the side wall 121
State grid structure both sides and the part puppet gate oxide 111 not covered by the side wall 121.
It should also be noted that, in the present embodiment, the nitrating layer 141 and element phase contained by the material of the side wall 121
Together, and the atom percentage content of nitrogen is more than the atom percentage content of nitrogen in the side wall 121 in the nitrating layer 141.
In another embodiment, the nitrating layer differs with element contained by the material of the side wall, element contained by the material of the side wall
Comprising nitrogen, and the atom percentage content of nitrogen is more than the atom percentage content of nitrogen in the side wall in the nitrating layer.At it
In his embodiment, the atom percentage content of nitrogen can also be zero in the side wall.
With reference to figure 9, after forming the nitrating layer 141, formation source in the substrate of both sides (is not indicated) in the grid structure
Leak doped region (not shown).
In the present embodiment, the substrate includes：Substrate 100 and the discrete fin protruded from the substrate 100
110；Accordingly, in the step of source and drain doping area is formed in the substrate of the grid structure both sides, in the grid structure two
The source and drain doping area is formed in the fin 110 of side.
Specifically, the step of source and drain doping area is formed in the substrate of the grid structure both sides includes：Etching is positioned at institute
The fin 110 of the segment thickness of grid structure both sides is stated, groove is formed in the fin 110；Form the full groove of filling
Stressor layers 150, and the source and drain doping is formed using auto-dope processing in situ during the stressor layers 150 are formed
Area.
In another embodiment, the step of source and drain doping area is formed in the substrate of the grid structure both sides can also wrap
Include：Etching forms groove positioned at the fin of the segment thickness of the grid structure both sides in the fin；Form the full institute of filling
State the stressor layers of groove；The stressor layers are doped with processing and forms the source and drain doping area.
In the present embodiment, the stressor layers 150 are formed using chemical vapor deposition epitaxial growth method.
In the present embodiment, so that the semiconductor structure of formation is N-type semiconductor structure as an example, the material of the stressor layers 150
Can be SiC or SiP.In the present embodiment, the materials of the stressor layers 150 is SiC, the chemical vapor deposition epitaxial growth method
Technological parameter include：Technological temperature is 500 DEG C to 950 DEG C, and the process time is 100s to 10000s, and reative cell air pressure is
50Torr to 1000Torr, pretreatment gas H2, reacting gas HCl, SiH2Cl2、SiH4、PH3(SiH3)2CH2In one kind
The mixed gas of gas or a variety of compositions.
Accordingly, the Doped ions in the source and drain doping area are N-type ion, for example, P, As or Sb.
In another embodiment, when the semiconductor structure of formation is P-type semiconductor structure, the material of the stressor layers may be used also
Think SiGe or SiGeB.Accordingly, the Doped ions in the source and drain doping area are p-type ion, for example, B, Ga or In.
It should be noted that due to causing the side formed with nitrating layer 141, the nitrating layer 141 on the side wall 121
Wall 121 and the material lattice constant mismatch of stressor layers 150；Therefore, stressor layers are formed using chemical vapor deposition epitaxial growth method
During 150, epitaxial growth film will not be carried out on the surface of side wall 121, so that the material character of the side wall 121
Stable, the material of the side wall 121 has relatively low relative dielectric constant all the time；Therefore the side wall 121, grid structure, with
And be subsequently formed the equivalent capacity that contact hole plug above the grid structure is formed capacitance it is small, and then can improve
The operating rate of semiconductor devices.
With reference to figure 10, the interlayer dielectric layer 103 for covering the grid structure (not indicating) and substrate is formed.
The interlayer dielectric layer 103 provides Process ba- sis to be subsequently formed contact hole plug.
Specifically, the step of forming interlayer dielectric layer 103 includes：Formed in substrate between the grid structure
Inter-level dielectric film, the inter-level dielectric film top is higher than at the top of the grid structure；The inter-level dielectric film is planarized
Technique, remove higher than the inter-level dielectric film at the top of the grid structure, form interlayer dielectric layer 103.
The material of the interlayer dielectric layer 103 is silica.The technique for forming the interlayer dielectric layer 103 can be chemistry
The methods of gas-phase deposition, plasma enhanced chemical vapor deposition technique or low-pressure chemical vapor deposition process.
It should be noted that in the present embodiment, the grid structure is pseudo- grid structure；Therefore, the inter-level dielectric is formed
After layer 103, the forming method also includes：The grid structure is removed, opening is formed in the interlayer dielectric layer 103；
Metal gate structure is formed in the opening, is flushed at the top of the metal gate structure with the top of interlayer dielectric layer 103.
In the present embodiment, the metal gate structure includes the gate dielectric layer 122 positioned at the open bottom and side wall, with
And on the gate dielectric layer 122 and the full opening of filling metal level 123.
The material of the gate dielectric layer 122 is high-k gate dielectric material, wherein, high-k gate dielectric material refers to relative Jie
Electric constant is more than the gate dielectric material of silica relative dielectric constant, and high-k gate dielectric material can be HfO2、HfSiO、
HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3.In the present embodiment, the material of the gate dielectric layer 122 is HfO2。
In the present embodiment, the material of the metal level 123 is W.In other embodiments, the material of the metal level may be used also
Think Al, Cu, Ag, Au, Pt, Ni or Ti.
With reference to reference to figure 11 and Figure 12, contact hole plug 160 is formed in the interlayer dielectric layer 103 (such as Figure 12 institutes
Show), the contact hole plug 160 is in contact with source and drain doping area (not shown).
The contact hole plug 160 is in contact with the source and drain doping area, for realizing the electrical connection in semiconductor devices,
It is additionally operable to realize the electrical connection between device and device.
Specifically, the step of forming contact hole plug 160 includes：The interlayer dielectric layer 103 is etched, formation is exposed
The contact hole 153 (as shown in figure 11) in the source and drain doping area；Form the conductive material layer of the full contact hole 153 of filling, institute
State conductive material layer and be also located at the top of interlayer dielectric layer 103；Planarization process is carried out to the conductive material layer, removed high
Conductive material layer in the top of interlayer dielectric layer 103, the contact hole plug 160 formed in the contact hole 153, institute
Contact hole plug 160 is stated to be in contact with the source and drain doping area.
In the present embodiment, the interlayer dielectric layer 103 is etched using dry etch process.Specifically, the dry etching
Technique is plasma etch process, and the etching gas used is CF4, buffer gas He, pressure be 20mTorr extremely
200mTorr, wherein CF4Gas flow be 50sccm to 1000sccm, He gas flow is 50sccm to 1000sccm.
In other embodiments, CF can also be used4、CHF3、C2F6Deng the one or more combination in fluorine base gas as etching gas
Body.
In the present embodiment, the material of the contact hole plug 160 is W.Chemical vapor deposition method, sputtering work can be used
Skill or electroplating technology form the contact hole plug 160.In other embodiments, the material of the contact hole plug can also be
The metal materials such as Al, Cu, Ag or Au.
It should be noted that formed with nitrating layer 141 on the side wall 121, when etching forms the contact hole 153,
141 pairs of the nitrating layer side wall 121 plays a protective role, and can reduce quarter of the etching technics to the side wall 121
Lose speed, that is to say, that the etching technics is more than the quarter to the side wall 121 to the etch rate of interlayer dielectric layer 103
Lose speed；So as to avoid phenomenon of the side wall 121 by the even described metal gate structure exposure of loss, to avoid to described
The performance of side wall 121 has undesirable effect and with the metal gate structure short circuit occurs for the contact hole plug 160, enters
And improve the electric property of semiconductor devices.
With continued reference to Figure 12, the present invention also provides a kind of semiconductor structure, including：
Substrate；
Grid structure (does not indicate), in the substrate；
Side wall 121 on the gate structure sidewall, the material of the side wall 121 is low k dielectric materials；
Nitrating layer 141 on the side wall 121, the atom percentage content of nitrogen is more than institute in the nitrating layer 141
State the atom percentage content of nitrogen in side wall 121；
Source and drain doping area (not shown), in the substrate of the grid structure both sides；
Interlayer dielectric layer 103, cover the grid structure and the substrate；
Contact hole plug 160 in the interlayer dielectric layer 103, the contact hole plug 160 are mixed with the source and drain
Miscellaneous area is in contact.
In the present embodiment, the semiconductor structure is fin field effect pipe；Accordingly, the substrate includes：Substrate 100,
And the discrete fin 110 protruded from the substrate 100.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be
Germanium, SiGe, carborundum, GaAs or gallium indium, the substrate can also be on silicon substrate or insulator on insulator
Germanium substrate.
The material of the fin 110 is identical with the material of the substrate 100.In the present embodiment, the material of the fin 110
For silicon.In other embodiment, the material of the fin can also be germanium, SiGe, carborundum, GaAs or gallium indium.
In another embodiment, the semiconductor structure is planar transistor；Accordingly, the substrate is planar substrates,
The planar substrates are silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, silicon-on-insulator substrate or germanium on insulator lining
Bottom, glass substrate or III-V substrate (such as gallium nitride substrate or gallium arsenide substrate etc.), the grid structure is located at
In the planar substrates.
It should be noted that the semiconductor structure also includes：On substrate 100 between the adjacent fin 110
Isolation structure 102, the isolation structure 102 covers the partial sidewall surface of the fin 110, and the isolation structure 102
Top less than the top of the fin 110.
The isolation structure 102 plays a part of being electrically isolated adjacent fin 110.In the present embodiment, the isolation structure 102
Material be silica.In other embodiments, the material of the isolation structure can also be silicon nitride or silicon oxynitride.
In the present embodiment, the grid structure covers the atop part surface of fin 110 and side across the fin 110
Wall surface.
In the present embodiment, the grid structure is metal gate structure, including across the fin 110, and cover fin
110 atop part surfaces and the gate dielectric layer 122 of sidewall surfaces, and the metal level 123 on the gate dielectric layer 122.
The material of the gate dielectric layer 122 is high-k gate dielectric material, wherein, high-k gate dielectric material refers to relative Jie
Electric constant is more than the gate dielectric material of silica relative dielectric constant, and high-k gate dielectric material can be HfO2、HfSiO、
HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3.In the present embodiment, the material of the gate dielectric layer 122 is HfO2。
In the present embodiment, the material of the metal level 123 is W.In other embodiments, the material of the metal level may be used also
Think Al, Cu, Ag, Au, Pt, Ni or Ti.
The material of the side wall 121 is low k dielectric materials, wherein, low k dielectric materials refer to that relative dielectric constant is less than
The material of silicon nitride relative dielectric constant.In the present embodiment, the relative dielectric constant of the side wall 121 is 3.9 to 7.5.
The side wall 121, grid structure and the contact hole plug 160 above the grid structure form one
Equivalent capacity；The equivalent capacity is considered as capacity plate antenna structure, dielectric layer of the side wall 121 between two flat boards, root
Understand that the capacitance of the equivalent capacity and the relative dielectric of the material of side wall 121 are normal according to the capacitance formula of capacity plate antenna
Number direct proportionality；Because the material of the side wall 121 is the low k dielectric materials that relative dielectric constant is 3.9 to 7.5, because
This can significantly reduce the capacitance of the equivalent capacity.
In the present embodiment, the material of the side wall 121 is oxygen-enriched carbon silicon oxynitride, and the thickness of the side wall 121 is 10 angstroms
To 100 angstroms.Wherein, the oxygen-enriched carbon silicon oxynitride refers to the higher carbon silicon oxynitride of oxygen atom percentage content.
It should be noted that the atom percentage content of oxygen is higher, the relative dielectric constant of the side wall 121 is lower；For
The guarantee side wall 121 has a relatively low relative dielectric constant, in the oxygen-enriched carbon silicon oxy-nitride material, the atomic percent of oxygen
It is more unsuitable than content too low；The atom percentage content of oxygen is also unsuitable too high, and otherwise easily the material character of the side wall 121 is produced
Raw harmful effect.Therefore, in the present embodiment, in the oxygen-enriched carbon silicon oxy-nitride material, the atom percentage content of oxygen is 25%
To 40%.
In the present embodiment, the nitrating layer 141 is identical with element contained by the material of the side wall 121, and the nitrating layer
The atom percentage content of nitrogen is more than the atom percentage content of nitrogen in the side wall 121 in 141.In another embodiment, institute
State nitrating layer to differ with element contained by the material of the side wall, element contained by the material of the side wall includes nitrogen, and described mixes
The atom percentage content of nitrogen is more than the atom percentage content of nitrogen in the side wall in nitrogen layer.In other embodiments, it is described
The atom percentage content of nitrogen can also be zero in side wall.
It should be noted that the semiconductor structure also includes：Positioned at the intrabasement stressor layers in grid structure both sides
150, the source and drain doping area is located in the stressor layers 150.
In the present embodiment, so that the semiconductor structure of formation is N-type semiconductor structure as an example, the material of the stressor layers 150
For SiC or SiP；The Doped ions in the source and drain doping area are N-type ion, for example, P, As or Sb.
In another embodiment, when the semiconductor structure of formation is p-type structure, the material of the stressor layers can also be
SiGe or SiGeB；The Doped ions in the source and drain doping area are p-type ion, for example, B, Ga or In.
In the present embodiment, the substrate includes：Substrate 100 and the discrete fin protruded from the substrate 100
110；Accordingly, the stressor layers 150 are located in the fin 110 of the grid structure both sides, and the source and drain doping area is located at institute
State in the fin 110 of grid structure both sides.
Nitrating layer 141 on the side wall 121 causes the side wall 121 and the material lattice constant of stressor layers 150
Mismatch；Therefore, will not be in the superficial growth film of side wall 121, so that institute in the forming process of the stressor layers 150
The material character stabilization of side wall 121 is stated, the material of the side wall 121 has relatively low relative dielectric constant all the time；Therefore it is described
The electric capacity for the equivalent capacity that side wall 121, grid structure and the contact hole plug 160 above the grid structure are formed
Value is smaller, and then can improve the operating rate of semiconductor devices.
In the present embodiment, the material of the interlayer dielectric layer 103 is silica.
The contact hole plug 160 is located in the interlayer dielectric layer 103, and is in contact with the source and drain doping area, uses
In realizing the electrical connection in semiconductor devices, it is additionally operable to realize the electrical connection between device and device.
In the present embodiment, the material of the contact hole plug 160 is W.In other embodiments, the contact hole plug
Material can also be the metal materials such as Al, Cu, Ag or Au.
In the present embodiment, the nitrating layer 141 on the side wall 121, in the forming process of the contact hole plug 160
In, the side wall 121 is played a protective role, avoids the side wall 121 from being showed by the loss even grid structure exposure
As, so that the material character of the side wall 121 is stable, and avoids the contact hole plug 160 that short circuit occurs with grid structure,
And then the operating rate and electric property of semiconductor devices can be improved.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Substrate is provided；Grid structure is formed on the substrate；Side wall is formed in the side wall of the grid structure, the material of the side wall is low k dielectric materials；Nitrating layer is formed on the side wall, the atom percentage content of nitrogen is more than the original of nitrogen in the side wall in the nitrating layer Sub- degree；After forming the nitrating layer, source and drain doping area is formed in the substrate of the grid structure both sides；Form the interlayer dielectric layer for covering the grid structure and substrate；Contact hole plug is formed in the interlayer dielectric layer, the contact hole plug is in contact with the source and drain doping area.
- 2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the relative dielectric constant of the side wall For 3.9 to 7.5.
- 3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of the side wall is oxygen-enriched carbon Silicon oxynitride.
- 4. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that in the oxygen-enriched carbon silicon oxynitride, The atom percentage content of oxygen is 25% to 40%.
- 5. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that form side wall and the nitrating layer Step includes：The side wall film of the conformal covering substrate and grid structure is formed, the material of the side wall film is low k dielectric material Material；Nitrating technique is carried out to the side wall film；Remove in the substrate and grid structure at the top of side wall film, form side wall in the side wall of the grid structure, and Nitrating layer is formed on the side wall.
- 6. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that the technique for forming the side wall film is Atom layer deposition process.
- 7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that before the atom layer deposition process Drive body is oxygen-containing gas.
- 8. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that the material of the side wall film is oxygen-enriched Carbon silicon oxynitride, the technological parameter of the atom layer deposition process include：The presoma being passed through into ald room be containing Si, C, O and N presoma, the total gas flow rate of presoma are 10sccm to 1000sccm, technological temperature be 25 degrees Celsius extremely 600 degrees Celsius, pressure is 1 millitorr to 500 millitorrs.
- 9. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that the nitrating technique is plasma Nitriding process.
- 10. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that the technique ginseng of the nitrating technique Number includes：Power is 1 watt to 500 watts, and pressure is 1 millitorr to 1000 millitorrs, and the process time is 5 seconds to 100 seconds, and reacting gas is Nitrogen, auxiliary gas are helium, and the gas flow of nitrogen is per minute per minute to 1000 standard milliliters for 10 standard milliliters, helium Gas flow for 1 standard milliliters it is per minute per minute to 1000 standard milliliters.
- 11. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the thickness of the side wall is 10 angstroms To 100 angstroms.
- 12. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the semiconductor structure is fin FET；In the step of providing substrate, the substrate includes substrate and protrudes from the fin of the substrate；In the step of forming grid structure on the substrate, the fin and covering fin atop part and side wall are developed across The grid structure on surface；In the step of source and drain doping area is formed in the substrate of the grid structure both sides, the fin in the grid structure both sides It is interior to form the source and drain doping area.
- 13. the forming method of semiconductor structure as claimed in claim 12, it is characterised in that in the grid structure both sides The step of source and drain doping area is formed in substrate includes：Etching is located at the fin of the segment thickness of the grid structure both sides, in institute State and groove is formed in fin；The stressor layers of the full groove of filling are formed, and using auto-dope in situ processing shape during the stressor layers are formed Into the source and drain doping area；OrEtching forms groove positioned at the fin of the segment thickness of the grid structure both sides in the fin；Form the stressor layers of the full groove of filling；The stressor layers are doped with processing and forms the source and drain doping area.
- 14. a kind of semiconductor structure, including：Substrate；Grid structure, in the substrate；Side wall on the gate structure sidewall, the material of the side wall is low k dielectric materials；Nitrating layer on the side wall, the atom percentage content of nitrogen is more than the original of nitrogen in the side wall in the nitrating layer Sub- degree；Source and drain doping area, in the substrate of the grid structure both sides；Interlayer dielectric layer, cover the grid structure and the substrate；Contact hole plug in the interlayer dielectric layer, the contact hole plug are in contact with the source and drain doping area.
- 15. semiconductor structure as claimed in claim 14, it is characterised in that the relative dielectric constant of the side wall be 3.9 to 7.5。
- 16. semiconductor structure as claimed in claim 14, it is characterised in that the material of the side wall is oxygen-enriched carbon nitrogen oxidation Silicon.
- 17. semiconductor structure as claimed in claim 16, it is characterised in that in the oxygen-enriched carbon silicon oxynitride, the atom of oxygen Degree is 25% to 40%.
- 18. semiconductor structure as claimed in claim 14, it is characterised in that the thickness of the side wall is 10 angstroms to 100 angstroms.
- 19. semiconductor structure as claimed in claim 14, it is characterised in that the semiconductor structure also includes：Intrabasement stressor layers positioned at the grid structure both sides；The source and drain doping area is located in the stressor layers.
- 20. semiconductor structure as claimed in claim 14, it is characterised in that the semiconductor structure is fin field effect pipe；The substrate includes substrate and protrudes from the fin of the substrate；The grid structure is across the fin and covering fin atop part and sidewall surfaces；The source and drain doping area is located in the fin of the grid structure both sides.
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