CN105161405A - Method for improving electrical properties of device - Google Patents
Method for improving electrical properties of device Download PDFInfo
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- CN105161405A CN105161405A CN201510459351.3A CN201510459351A CN105161405A CN 105161405 A CN105161405 A CN 105161405A CN 201510459351 A CN201510459351 A CN 201510459351A CN 105161405 A CN105161405 A CN 105161405A
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- side wall
- electric property
- device electric
- method improving
- improving device
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000000137 annealing Methods 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims description 25
- 239000012212 insulator Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 abstract description 24
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 5
- 230000000149 penetrating effect Effects 0.000 abstract 1
- -1 phosphonium ion Chemical class 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/0231—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to electromagnetic radiation, e.g. UV light
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a method for improving electrical properties of a device. The method includes: providing a semiconductor substrate, forming a well region in the semiconductor substrate, and then performing annealing treatment on the well region; performing ion injection on the surface of the surface of the semiconductor substrate, so as to form an ion-doped layer; growing a gate insulation layer on the ion-doped layer; and sequentially forming a gate located on the gate insulation layer and in well region, a side wall located on a gate side wall, and a source electrode and a drain electrode which are located at two sides of the bottom of the side wall, and then carrying out a process for leading out the gate, the source electrode and the drain electrode. The ion-doped layer is formed through ion injection, growth of the gate insulation layer can be facilitated and uniformity of the gate insulation layer can be improved, and ions in the gate can be stopped from penetrating through the gate insulation layer and entering a channel, thereby avoiding a dismatch of threshold voltage of the device, and improving the electrical properties of the device.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to a kind of method improving device electric property.
Background technology
Along with the development of integrated circuit technique, the quantity of semiconductor device integrated in one chip is on the increase, and when carrying out integrated circuit (IC) design, usually will use the semiconductor device of some same electrical mathematic(al) parameters.Such as, when relating to the memory cell of static random access memory (SRAM), need the MOS transistor of some same electrical mathematic(al) parameters.But; in the product of reality; nominally the electrical parameter of MOS transistor identical in SRAM memory cell usually can drift about; cause the electrical parameter mismatch (mismatch) of MOS transistor that originally should be identical; namely matching properties declines, thus can cause the problems such as SRAM storage speed slows down, power consumption increases, clock is chaotic.
Cause the reason of this transistor electricity parameter mismatch a lot, wherein mainly comprise: the height of the pattern density near device is inconsistent and the grinding and polishing speed that causes different, the implantation dosage that process deviation in ion implantation process causes is different, the Stress non-homogeneity etc. that some stressor layers that process deviation causes cause.
In present mainstream technology, the formation of grid oxic horizon is all injected at trap and is formed after annealing, thinning along with grid oxic horizon, the ion in polysilicon gate can enter into raceway groove under the effect of heat budget, and this also can increase the mismatch of the electrical parameter of device.
Summary of the invention
In order to overcome above problem, the present invention aims to provide a kind of method improving device electric property, and employing is carried out ion implantation on a semiconductor substrate and formed one deck ion implanted layer, and then grows grid oxic horizon, thus reduces the threshold voltage of device.
To achieve these goals, the invention provides a kind of method improving device electric property, it comprises:
Step 01: semi-conductive substrate is provided, and form well region in the semiconductor substrate, then annealing in process is carried out to described well region;
Step 02: carry out ion implantation at described semiconductor substrate surface, to form ion doped layer;
Step 03: grow gate insulator on described ion doped layer;
Step 04: formed successively and to be positioned on described gate insulator and grid on described well region, to be positioned at the side wall of described gate lateral wall and to be positioned at source, the drain electrode of described side wall two bottom sides, then carries out the extraction technique of described grid and described source, drain electrode.
Preferably, in described step 02, described ion implantation adopts N~+ implantation,
Preferably, in described step 02, the energy of described ion implantation is 2KeV ~ 5KeV.
Preferably, in described step 02, the dosage of described ion implantation is 1E12 ~ 5E13/cm
2.
Preferably, in described step 02, the temperature of described ion implantation is normal temperature or low temperature; Described low temperature is less than 10 DEG C.
Preferably, described low temperature is-30 ~ 0 DEG C.
Preferably, in described step 03, the material of described gate insulator is silicon oxynitride or silica.
Preferably, in described step 04, the formation of described grid comprises: deposition of gate material on the semiconductor substrate, then, forms described grid through photoetching and etching technics.
Preferably, described step 04 comprises:
Step 041: form the first side wall on described gate lateral wall surface;
Step 042: form lightly-doped source, drain structure in the described well region of described first side wall two bottom sides;
Step 043: form the second side wall in described first side wall sidewall surfaces;
Step 044: form source, drain electrode in the described lightly-doped source, drain structure of described second side wall two bottom sides;
Step 045: annealing in process is carried out to described source, drain electrode;
Step 046: prepare pre-metal dielectric, through hole, metal plug and metal level at the semiconductor substrate surface completing described step 045.
Preferably, in described step 045, spike-anneal technique is adopted to carry out annealing in process to described source, drain electrode.
The method improving device electric property of the present invention, after formation well region also annealing, first ion implantation is carried out to form ion doped layer at semiconductor substrate surface, then, ion implanted layer grows gate insulator, form ion doped layer by ion implantation can promote the growth of gate insulator and improve the uniformity of gate insulator, raceway groove is entered into after can also hindering the ion penetration gate insulator in grid, thus avoid the mismatch of the threshold voltage of device, improve the electric property of device.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the method for the improvement device electric property of a preferred embodiment of the present invention
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Below in conjunction with accompanying drawing 1 and specific embodiment, the method improving device electric property of the present invention is described in further detail.It should be noted that, accompanying drawing all adopt simplify very much form, use non-ratio accurately, and only in order to object that is convenient, that clearly reach aid illustration the present embodiment.
Refer to Fig. 1, the method for the improvement device electric property in the present embodiment, comprises the following steps:
Step 01: semi-conductive substrate is provided, and form well region in the semiconductor substrate, then annealing in process is carried out to well region;
Concrete, Semiconductor substrate can be, but not limited to as silicon substrate, and the formation of well region can adopt ion implantation technology.In the present embodiment, can inject through phosphonium ion in a silicon substrate and form N-type well region and form P type trap zone through boron ion implantation.
Then, conventional annealing process is carried out to N-type well region and P type trap zone, repairs with the defect activated injected Doped ions and cause ion implantation.
Step 02: carry out ion implantation at semiconductor substrate surface, to form ion doped layer;
Concrete, in the present embodiment, N~+ implantation is carried out to well region, thus form Nitrogen ion doped layer on well region surface.In this step, the energy of ion implantation and dosage control extremely important.Because the ion doped layer that energy or dosage size are formed, not only can affect the speed of growth and the uniformity of subsequent gate insulating layer, also greatly affect the reliability of device, such as negative temperature bias unstable effect, hot carrier's effect etc.Therefore, suitable energy and dosage, not only can not affect the speed of growth of gate insulator, the such as boron ion of the Doped ions in grid can also be hindered rightly under thermal excitation, to penetrate gate insulator and enter in raceway groove, thus the mismatch of the threshold voltage of device can be reduced, and then improve the performance of device.Preferably, the energy of ion implantation is 2KeV ~ 5KeV, and the dosage of ion implantation is 1E12 ~ 5E13/cm
2; The temperature of ion implantation can be normal temperature, also can be low temperature; Low temperature can be less than 10 DEG C, and preferably, low temperature is-30 ~ 0 DEG C.
Step 03: grow gate insulator on ion doped layer;
Concrete, in the present embodiment, Nitrogen ion doped layer can be, but not limited to adopt chemical vapour deposition technique long gate in next life insulating barrier, the material of gate insulator can be silicon oxynitride or silica.
Step 04: formed successively and to be positioned on gate insulator and grid on well region, to be positioned at the side wall of gate lateral wall and to be positioned at source, the drain electrode of side wall two bottom sides, then carries out the extraction technique of grid and source, drain electrode.
Concrete, in the present embodiment, gate insulator forms grid respectively in N-type well region, P type trap zone, and the material of grid can be polysilicon; The formation of grid can comprise: deposition of gate material on a semiconductor substrate, then, forms gate patterns, can also comprise and carry out ion doping technique to grid through photoetching and etching technics.
Then, can be, but not limited to carry out following process:
Step 041: form the first side wall on gate lateral wall surface; Can be, but not limited to adopt Low Pressure Chemical Vapor Deposition to form the first side wall, the material of the first side wall is silicon nitride.
Step 042: form lightly-doped source, drain structure in the well region of the first side wall two bottom sides;
Here, in N-type well region and P type trap zone, lightly-doped source, drain structure is all formed; The impurity adopted can be boron fluoride.
Step 043: form the second side wall in the first side wall sidewall surfaces;
Here, the formation of the second side wall can comprise: the deposition of the second spacer material and the etching of the second spacer material.The material of the second side wall can be silicon nitride.
Step 044: form source, drain electrode in institute's lightly-doped source, drain structure of the second side wall two bottom sides;
Here, carry out source, leak ion implantation technology thus all form source, drain electrode in N-type well region and P shape well region, wherein, carry out P type Doped ions in the lightly-doped source in N-type well region, drain structure and inject, such as boron Doped ions; The injection of N-type Doped ions is carried out in lightly-doped source in P type trap zone, drain structure.
Step 045: annealing in process is carried out to source, drain electrode; Here, spike-anneal technique can be adopted to carry out annealing in process to source, drain electrode;
Step 046: prepare pre-metal dielectric, through hole, metal plug and metal level at the semiconductor substrate surface of completing steps 045; Here, common process can be adopted to complete this step 046, thus complete grid, the extraction of source, drain electrode.
In sum, the method improving device electric property of the present invention, after formation well region also annealing, first ion implantation is carried out to form ion doped layer at semiconductor substrate surface, then, ion implanted layer grows gate insulator, form ion doped layer by ion implantation can promote the growth of gate insulator and improve the uniformity of gate insulator, raceway groove is entered into after can also hindering the ion penetration gate insulator in grid, thus avoid the mismatch of the threshold voltage of device, improve the electric property of device.
Although the present invention discloses as above with preferred embodiment; right described embodiment is citing for convenience of explanation only; and be not used to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (10)
1. improve a method for device electric property, it is characterized in that, comprising:
Step 01: semi-conductive substrate is provided, and form well region in the semiconductor substrate, then annealing in process is carried out to described well region;
Step 02: carry out ion implantation at described semiconductor substrate surface, to form ion doped layer;
Step 03: grow gate insulator on described ion doped layer;
Step 04: formed successively and to be positioned on described gate insulator and grid on described well region, to be positioned at the side wall of described gate lateral wall and to be positioned at source, the drain electrode of described side wall two bottom sides, then carries out the extraction technique of described grid and described source, drain electrode.
2. the method improving device electric property according to claim 1, is characterized in that, in described step 02, described ion implantation adopts N~+ implantation.
3. the method improving device electric property according to claim 2, is characterized in that, in described step 02, the energy of described ion implantation is 2KeV ~ 5KeV.
4. the method improving device electric property according to claim 2, is characterized in that, in described step 02, the dosage of described ion implantation is 1E12 ~ 5E13/cm
2.
5. the method improving device electric property according to claim 2, is characterized in that, in described step 02, the temperature of described ion implantation is normal temperature or low temperature; Described low temperature is less than 10 DEG C.
6. the method improving device electric property according to claim 5, is characterized in that, described low temperature is-30 ~ 0 DEG C.
7. the method improving device electric property according to claim 1, is characterized in that, in described step 03, the material of described gate insulator is silicon oxynitride or silica.
8. the method improving device electric property according to claim 1, is characterized in that, in described step 04, the formation of described grid comprises: deposition of gate material on the semiconductor substrate, then, forms described grid through photoetching and etching technics.
9. the method improving device electric property according to claim 1, is characterized in that, described step 04 comprises:
Step 041: form the first side wall on described gate lateral wall surface;
Step 042: form lightly-doped source, drain structure in the described well region of described first side wall two bottom sides;
Step 043: form the second side wall in described first side wall sidewall surfaces;
Step 044: form source, drain electrode in the described lightly-doped source, drain structure of described second side wall two bottom sides;
Step 045: annealing in process is carried out to described source, drain electrode;
Step 046: prepare pre-metal dielectric, through hole, metal plug and metal level at the semiconductor substrate surface completing described step 045.
10. the method improving device electric property according to claim 9, is characterized in that, in described step 045, adopts spike-anneal technique to carry out annealing in process to described source, drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510459351.3A CN105161405A (en) | 2015-07-30 | 2015-07-30 | Method for improving electrical properties of device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510459351.3A CN105161405A (en) | 2015-07-30 | 2015-07-30 | Method for improving electrical properties of device |
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| CN105161405A true CN105161405A (en) | 2015-12-16 |
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| CN201510459351.3A Pending CN105161405A (en) | 2015-07-30 | 2015-07-30 | Method for improving electrical properties of device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080160710A1 (en) * | 2006-12-29 | 2008-07-03 | Dongbu Hitek Co., Ltd. | Method of fabricating mosfet device |
| CN102468178A (en) * | 2010-11-19 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing transistor |
| CN102800593A (en) * | 2011-05-25 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
-
2015
- 2015-07-30 CN CN201510459351.3A patent/CN105161405A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080160710A1 (en) * | 2006-12-29 | 2008-07-03 | Dongbu Hitek Co., Ltd. | Method of fabricating mosfet device |
| CN102468178A (en) * | 2010-11-19 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing transistor |
| CN102800593A (en) * | 2011-05-25 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
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