TWI581314B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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本揭露是有關於製造半導體裝置,特別是有關於製造半導體裝置期間的注入程序。 The present disclosure relates to the fabrication of semiconductor devices, and more particularly to implant processes during the fabrication of semiconductor devices.
半導體裝置藉由一製造程序形成在一晶圓上。在某些情況下,形成在一晶圓上的半導體裝置是相同的,亦即它們具有相同的尺寸和相同的特性。然而,現代半導體裝置的製造程序可包含數十或甚至數百個程序步驟,並且程序變化可能導致裝置的尺寸偏差。此裝置尺寸偏差可能會導致裝置特性的偏差,例如半導體裝置的臨界電壓Vth、或崩潰電壓Vpt。這種偏差可能在當晶圓的尺寸增加或各個半導體裝置的尺寸減小時變更大。 The semiconductor device is formed on a wafer by a manufacturing process. In some cases, the semiconductor devices formed on a wafer are identical, that is, they have the same dimensions and the same characteristics. However, the manufacturing process of modern semiconductor devices may include tens or even hundreds of program steps, and program variations may result in dimensional deviations of the device. This device size deviation may cause variations in device characteristics, such as the threshold voltage Vth of the semiconductor device, or the breakdown voltage Vpt. Such variations may vary greatly as the size of the wafer increases or the size of each semiconductor device decreases.
本揭露提供一種半導體裝置的製造方法,包含準備包含多個突起部形成在一基板上的一晶圓。這些突起部向上突起在基板的一表面並且具有從基板的表面上測量的一高度。此方法更包含決定代表相鄰的突起部之間的間隔的分布的一間隔分布,以及基於高度和間隔分布計算一注入角度。此注入角度為基板的一法線方向和一注入方向之間的一角度。此方法也包含以計算的注入角度注入離子。 The present disclosure provides a method of fabricating a semiconductor device including preparing a wafer including a plurality of protrusions formed on a substrate. These protrusions protrude upward on a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representative of the distribution of the spacing between adjacent protrusions, and calculating an injection angle based on the height and spacing distribution. The implantation angle is an angle between a normal direction of the substrate and an injection direction. This method also involves injecting ions at a calculated injection angle.
本揭露也提供一種半導體裝置,包含一基板以及複數個突起部形成在基板上。這些突起部向上突起在基板的一表面。相鄰的這些突起部的多個間隔是互不相同的。這裝置還包含複數個摻雜區,形成在基板中並形成在這些突起部之間。這些摻雜區對應這些間隔並且包含多個不同的摻雜濃度。 The present disclosure also provides a semiconductor device including a substrate and a plurality of protrusions formed on the substrate. These protrusions protrude upward on a surface of the substrate. The plurality of intervals of the adjacent protrusions are different from each other. The device also includes a plurality of doped regions formed in the substrate and formed between the protrusions. These doped regions correspond to these intervals and contain a plurality of different doping concentrations.
本揭露的特徵和優點可以從下列的描述中說明,並且部分地是從描述中顯而易見的、或者可通過本揭露的實施而得知。這些特徵和優點可以由所附的申請專利範圍所特別指出的元件和其組合實現。 The features and advantages of the present disclosure are set forth in the description which follows, These features and advantages can be realized by the elements and combinations thereof particularly pointed out in the appended claims.
應當理解的是,前述一般的描述和以下的詳細描述都只是示例性和說明性的,並不如要求保護申請專利範圍用以限制本發明的。 It is to be understood that the foregoing general descriptions
所附的圖式包含在說明書中,並與說明書構成本說明書的一部分,圖式示出了本發明的幾個實施例,並且可參照說明書用於解釋本發明的原理。 The accompanying drawings, which are incorporated in the specification of FIG
100、500‧‧‧晶圓 100, 500‧‧‧ wafer
102、502、1307、1308、1309、1310‧‧‧突起部 102, 502, 1307, 1308, 1309, 1310‧‧ ‧ protrusions
104、504、1301‧‧‧基板 104, 504, 1301‧‧‧ substrate
106、106a、106b、1300‧‧‧半導體裝置 106, 106a, 106b, 1300‧‧‧ semiconductor devices
W‧‧‧閘極寬度 W‧‧‧ gate width
L、L1、L2‧‧‧閘極長度 L, L1, L2‧‧‧ gate length
Vth‧‧‧臨界電壓 Vth‧‧‧ threshold voltage
Vpt‧‧‧崩潰電壓 Vpt‧‧‧crash voltage
H‧‧‧閘極高度 H‧‧‧ gate height
P‧‧‧間距 P‧‧‧ spacing
X1、X2、1302、1304、1306‧‧‧間隔 X1, X2, 1302, 1304, 1306‧‧‧ interval
θ‧‧‧注入角度 θ ‧‧‧Injection angle
Y‧‧‧突起部中的垂直位置 Y‧‧‧Vertical position in the protrusion
602‧‧‧離子 602‧‧‧ ions
1312、1314、1316‧‧‧區域 1312, 1314, 1316‧‧‧ areas
第1圖繪示包含多個突起部形成在一基板上的一晶圓的一部份的透視圖。 Figure 1 is a perspective view of a portion of a wafer including a plurality of protrusions formed on a substrate.
第2A圖和第2B圖繪示在第1圖中的晶圓的不同部份的剖面圖。 2A and 2B are cross-sectional views showing different portions of the wafer in Fig. 1.
第3A圖和第3B圖繪示半導體裝置的一臨界電壓或一崩潰電壓和一閘極長度或一閘極寬度之間關係的示意圖。 3A and 3B are schematic diagrams showing a relationship between a threshold voltage or a breakdown voltage and a gate length or a gate width of the semiconductor device.
第4圖繪示半導體裝置的臨界電壓和崩潰電壓在一晶圓上的分布的示意圖。 FIG. 4 is a schematic diagram showing the distribution of the threshold voltage and the breakdown voltage of the semiconductor device on a wafer.
第5A圖、第5B圖、第6A圖和第6B圖繪示依據一實施例的半導體裝置製造方法的剖面圖。 5A, 5B, 6A, and 6B are cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment.
第7A圖和第7B圖繪示經例如第5A圖、第5B圖、第6A圖和第6B圖的製造方法的晶圓的一部份的俯視圖。 FIGS. 7A and 7B illustrate top views of a portion of a wafer by, for example, the manufacturing methods of FIGS. 5A, 5B, 6A, and 6B.
第8A圖和第8B圖繪示依據本揭露一實施例製造方法半導體裝置的臨界電壓或崩潰電壓和閘極長度或閘極寬度之間的效果的示意圖。 8A and 8B are schematic diagrams showing effects between a threshold voltage or a breakdown voltage and a gate length or a gate width of a semiconductor device in accordance with an embodiment of the present disclosure.
第9圖繪示依據本揭露一實施例製造方法半導體裝置的臨界電壓或崩潰電壓在一晶圓上的分布的效果的示意圖。 FIG. 9 is a schematic diagram showing the effect of the distribution of the threshold voltage or breakdown voltage of a semiconductor device on a wafer according to an embodiment of the present disclosure.
第10A圖和第10B圖繪示在依據一實施例執行自對準注入後的晶圓的不同部份的模擬雜質分布的示意圖。 10A and 10B are schematic diagrams showing simulated impurity distributions of different portions of a wafer after self-aligned implantation is performed in accordance with an embodiment.
第11A圖和第11B圖繪示半導體裝置的具有不同的閘極長度的模擬的臨界電壓和崩潰電壓的折線圖。 11A and 11B are line graphs of simulated threshold voltages and breakdown voltages of semiconductor devices having different gate lengths.
第12A圖和第12B圖繪示依據本揭露一實施例以一斜向離子注入突起部的垂直摻雜分布以及以一垂直離子注入突起部之間的比較的示意圖。 12A and 12B are schematic views showing a vertical doping profile of an oblique ion implantation protrusion and a comparison between the vertical ion implantation protrusions according to an embodiment of the present disclosure.
第13圖繪示依據本揭露一實施例的半導體裝置的不同間隔的相鄰的突起部之間具有不同的摻雜濃度的示意圖。 FIG. 13 is a schematic view showing different doping concentrations between adjacent protrusions of different intervals of a semiconductor device according to an embodiment of the present disclosure.
本揭露的一實施例包含製造半導體裝置的一方法。 One embodiment of the present disclosure includes a method of fabricating a semiconductor device.
在本文中,參照圖式描述本揭露的實施例。盡可能地,圖式中相同的參考符號用來表示相同或相似的元件。 Embodiments of the present disclosure are described herein with reference to the drawings. Wherever possible, the same reference numerals in the drawings
第1圖繪示包含多個突起部102形成在一基板104上的一晶圓100的一部份的透視圖。突起部102形成在基板104上的一間距P(pitch)。 這此例中,突起部102為半導體裝置106的閘極結構。半導體裝置106可例如為金氧半場效電晶體(MOSFET)、電荷擷取(charge-trap)記憶體單元,如氧化物氮化物氧化物(ONO)記憶體單元或浮閘記憶體單元。每一半導體裝置106都與多個尺寸參數相關,例如閘極長度L、閘極寬度W和閘極高度H,亦即突起部102。由於程序的變化,晶圓100上的半導體裝置106中的尺寸參數可為不同的。舉例來說,第2A圖和第2B圖繪示晶圓100的不同區域的分別具有不同閘極長度L1及L2的半導體裝置106a及半導體裝置106b的剖面圖。因此,半導體裝置106a和半導體裝置106b的電氣特性例如臨界電壓Vth或崩潰電壓Vpt可能不相同。 FIG. 1 is a perspective view of a portion of a wafer 100 including a plurality of protrusions 102 formed on a substrate 104. The protrusions 102 are formed at a pitch P on the substrate 104. In this example, the protrusion 102 is a gate structure of the semiconductor device 106. The semiconductor device 106 can be, for example, a gold oxide half field effect transistor (MOSFET), a charge-trap memory cell, such as an oxide nitride oxide (ONO) memory cell or a floating gate memory cell. Each semiconductor device 106 is associated with a plurality of dimensional parameters, such as gate length L, gate width W, and gate height H, i.e., protrusions 102. The size parameters in the semiconductor device 106 on the wafer 100 can be different due to program variations. For example, FIGS. 2A and 2B illustrate cross-sectional views of semiconductor device 106a and semiconductor device 106b having different gate lengths L1 and L2, respectively, in different regions of wafer 100. Therefore, the electrical characteristics of the semiconductor device 106a and the semiconductor device 106b such as the threshold voltage Vth or the breakdown voltage Vpt may not be the same.
第3A圖和第3B圖繪示一半導體裝置的臨界電壓Vth或崩潰電壓Vpt和閘極長度或閘極寬度之間的關係的示意圖。第3A圖和第3B圖分別示出了基板104中的不同摻雜濃度的情況。在相同的摻雜條件下,一較小的裝置相較於一較大的裝置通常有較低的臨界電壓Vth或崩潰電壓Vpt,故對於較小的裝置的結構設計裕度是比較小的。因此,當裝置尺寸縮放時,一較小的裝置的電氣特性對於複雜的熱擴散和程序控制是敏感的。據此,一較小的裝置具有可能受一非均勻的摻雜分布影響而有限的操作電流區域。舉例來說,在一具有高的局部摻雜濃度的區域的一較小的裝置相較於在一具有低的局部摻雜濃度的區域的一較小的裝置會有一較大的臨界電壓Vth。另一方面,一較大的裝置可能具有較寬廣的操作電流區域以平衡受非均勻的摻雜分布引起的電氣變化。在第3A圖和第3B圖中,水平軸代表閘極長度L或閘極寬度W,而垂直軸代表臨界電壓Vth或崩潰電壓Vpt。因此,在第3A圖和第3B圖中,每一曲線代表四個從屬關係:臨界電壓Vth 和閘極長度L的關係、臨界電壓Vth和閘極寬度W的關係、崩潰電壓Vpt和閘極長度L的關係以及崩潰電壓Vpt和閘極寬度W的關係。 3A and 3B are schematic views showing the relationship between the threshold voltage Vth or the breakdown voltage Vpt of a semiconductor device and the gate length or the gate width. FIGS. 3A and 3B show the different doping concentrations in the substrate 104, respectively. Under the same doping conditions, a smaller device typically has a lower threshold voltage Vth or a breakdown voltage Vpt than a larger device, so the structural design margin for smaller devices is relatively small. Thus, when the device is scaled, the electrical characteristics of a smaller device are sensitive to complex thermal diffusion and program control. Accordingly, a smaller device has a limited operating current region that may be affected by a non-uniform doping profile. For example, a smaller device in a region with a high local doping concentration will have a larger threshold voltage Vth than a smaller device in a region with a low local doping concentration. On the other hand, a larger device may have a wider operating current region to balance the electrical changes caused by the non-uniform doping profile. In FIGS. 3A and 3B, the horizontal axis represents the gate length L or the gate width W, and the vertical axis represents the threshold voltage Vth or the breakdown voltage Vpt. Therefore, in Figures 3A and 3B, each curve represents four affiliations: threshold voltage Vth The relationship with the gate length L, the relationship between the threshold voltage Vth and the gate width W, the relationship between the breakdown voltage Vpt and the gate length L, and the relationship between the breakdown voltage Vpt and the gate width W.
具體地,第3A圖示出了基板104中的摻雜濃度相對低而發生短通道效應的情況。另一方面,第3B圖示出了基板104中的摻雜濃度相對高而發生反轉短通道效應的情況。如第3A圖和第3B圖所示,在這兩種情況的任一種中,臨界電壓Vth和崩潰電壓Vpt都隨著有著不同的閘極長度L或閘極寬度W的裝置而有很大的改變。因此,如果形成在同一晶圓上不同區域的半導體裝置具有不同的尺寸,例如如第2A圖和第2B圖所示的不同的閘極長度,則一或多個裝置特性例如在晶圓上的半導體裝置的臨界電壓Vth或崩潰電壓Vpt可能會不同,導致一裝置特性分布亦即晶圓上的裝置特性是不均勻的。第4圖繪示臨界電壓Vth或崩潰電壓Vpt的分布的示意圖。在第4圖中,水平軸代表臨界電壓Vth或崩潰電壓Vpt,而垂直軸代表具有一特定臨界電壓Vth或崩潰電壓Vpt的裝置的數量。由於程序變化,此分布可能非常寬廣。 Specifically, FIG. 3A shows a case where the doping concentration in the substrate 104 is relatively low and a short channel effect occurs. On the other hand, FIG. 3B shows a case where the doping concentration in the substrate 104 is relatively high and the reverse short channel effect occurs. As shown in FIGS. 3A and 3B, in either of the two cases, the threshold voltage Vth and the breakdown voltage Vpt are both large with devices having different gate lengths L or gate widths W. change. Thus, if semiconductor devices formed in different regions on the same wafer have different sizes, such as different gate lengths as shown in FIGS. 2A and 2B, then one or more device characteristics are, for example, on a wafer. The threshold voltage Vth or the breakdown voltage Vpt of the semiconductor device may be different, resulting in a device characteristic distribution, that is, device characteristics on the wafer are not uniform. FIG. 4 is a schematic diagram showing the distribution of the threshold voltage Vth or the breakdown voltage Vpt. In Fig. 4, the horizontal axis represents the threshold voltage Vth or the breakdown voltage Vpt, and the vertical axis represents the number of devices having a specific threshold voltage Vth or breakdown voltage Vpt. This distribution can be very broad due to program changes.
第5A圖、第5B圖、第6A圖和第6B圖繪示依據本揭露一實施例的半導體裝置製造方法的剖面圖。如第5A圖和第5B圖所示,晶圓500包含突起部502形成在基板504上。基板504可為一半導體基板,例如為一矽基板或一矽上絕緣體(SOI)基板。甚至,基板504可為n型或p型摻雜。在一些實施例中,半導體裝置為電晶體且基板504上被突起部502覆蓋的區域對應電晶體的通道區。 5A, 5B, 6A, and 6B are cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present disclosure. As shown in FIGS. 5A and 5B, the wafer 500 includes protrusions 502 formed on the substrate 504. The substrate 504 can be a semiconductor substrate, such as a germanium substrate or a top insulator (SOI) substrate. Even the substrate 504 can be n-type or p-type doped. In some embodiments, the semiconductor device is a transistor and the region of the substrate 504 that is covered by the protrusions 502 corresponds to the channel region of the transistor.
形成在晶圓500上的突起部502可為在半導體裝置的一製造程序期間形成的結構,此結構可在製造程序之後的階段被移除或破壞,或 者保留在最後的裝置中。在一些實施例中,突起部502被包含在由一單一材料形成的一圖案化層中,舉例來說,一電介質如氧化物、一氮化物或一氮氧化物,一半導體如一單晶矽或一多晶矽,一金屬,或一光阻。在一些實施例中,突起部502被包含在由至少兩種材料形成的一圖案化層,其中一材料堆疊在另一材料之上。這至少兩種材料可例如從上述材料中選擇。在一些實施例中,突起部502為電晶體的閘極結構。這些電晶體可以例如為金氧半場效電晶體(MOSFET)、電荷擷取記憶體單元如ONO記憶體單元或浮閘記憶體單元。 The protrusion 502 formed on the wafer 500 may be a structure formed during a manufacturing process of the semiconductor device, which may be removed or destroyed at a stage after the manufacturing process, or The person remains in the last device. In some embodiments, the protrusions 502 are included in a patterned layer formed of a single material, such as a dielectric such as an oxide, a nitride or an oxynitride, a semiconductor such as a single crystal germanium or A polysilicon, a metal, or a photoresist. In some embodiments, the protrusions 502 are included in a patterned layer formed of at least two materials, one of which is stacked over the other. The at least two materials can be selected, for example, from the above materials. In some embodiments, protrusion 502 is a gate structure of a transistor. These transistors may be, for example, gold oxide half field effect transistors (MOSFETs), charge extraction memory cells such as ONO memory cells or floating gate memory cells.
突起部502形成在基板504上的同一間距P且具有相同的高度H。第5A圖示出了晶圓500的一第一區域,其中第一區域中突起部502的長度為L1且相鄰的突起部502之間的間隔為X1。第5B圖示出了晶圓500的一第二區域,其中第二區域中突起部502的長度為L2且相鄰的突起部502之間的間隔為X2。在此例中,由於長度上的差別,L1大於L2且X1小於X2。 The protrusions 502 are formed at the same pitch P on the substrate 504 and have the same height H. FIG. 5A shows a first region of the wafer 500 in which the length of the protrusion 502 in the first region is L1 and the interval between adjacent protrusions 502 is X1. Figure 5B shows a second region of wafer 500 in which the length of protrusion 502 in the second region is L2 and the spacing between adjacent protrusions 502 is X2. In this case, due to the difference in length, L1 is greater than L2 and X1 is less than X2.
如第6A圖和第6B圖所示,在如第5A圖和第5B圖所示的晶圓500上以一注入角度θ注入離子602以執行一離子注入。此注入角度θ為基板504的一法線方向(第6A圖和第6B圖的虛線)和離子602被注入的一注入方向(第6A圖和第6B圖的實線)之間的一角度。離子602可為砷離子、硼離子、銦離子、銻離子、氮離子、鍺離子、碳離子、或磷離子的至少一個。 As shown in FIGS. 6A and 6B, ions 602 are implanted at an implantation angle θ on the wafer 500 as shown in FIGS. 5A and 5B to perform an ion implantation. This injection angle θ is an angle between a normal direction of the substrate 504 (dashed lines of FIGS. 6A and 6B) and an injection direction (solid lines of FIGS. 6A and 6B) in which the ions 602 are injected. The ions 602 may be at least one of an arsenic ion, a boron ion, an indium ion, a cerium ion, a nitrogen ion, a cerium ion, a carbon ion, or a phosphorus ion.
符合本揭露的實施例中,注入角度θ被選擇以使第5A圖和第6A圖所示的第一區域中的離子602被突起部502完全擋住,因此不能到 達基板504上相鄰的突起部502之間的區域。另一方面,第5B圖和第6B圖所示的第二區域中離子602並未被突起部502完全擋住,因此一些離子602可到達基板504上相鄰的突起部502之間的區域。依據本揭露的實施例的這種傾斜注入也被稱為自對準注入。 In an embodiment consistent with the present disclosure, the injection angle θ is selected such that the ions 602 in the first region shown in FIGS. 5A and 6A are completely blocked by the protrusions 502, and thus cannot be A region between adjacent protrusions 502 on the substrate 504. On the other hand, the ions 602 in the second region shown in FIGS. 5B and 6B are not completely blocked by the protrusions 502, so some ions 602 can reach the region between the adjacent protrusions 502 on the substrate 504. Such oblique implants in accordance with embodiments of the present disclosure are also referred to as self-aligned implants.
符合本揭露的實施例中,基於突起部502的高度H和代表晶圓500上相鄰的突起部502之間的間隔的分布的一間隔分布計算注入角度θ。此間隔分布可包含一系列的間隔值,例如90nm、94nm、94nm、100nm、…,其中每個間隔值對應兩個相鄰的突起部之間的間隔。此間隔分布也可包含一統計說明,對每一間隔範圍有多少對的相鄰的突起部具有一間隔落在此間隔範圍內。舉例來說,有10對相鄰的突起部的間隔落在間隔範圍90nm到90nm之間,有20對相鄰的突起部的間隔落在間隔範圍91nm到92nm之間,等等。 In accordance with an embodiment of the present disclosure, the injection angle θ is calculated based on an interval distribution of the height H of the protrusion 502 and the distribution of the spacing between adjacent protrusions 502 on the wafer 500. This spacing distribution may comprise a series of spacing values, such as 90 nm, 94 nm, 94 nm, 100 nm, ..., where each spacing value corresponds to the spacing between two adjacent protrusions. The spacing distribution may also include a statistical description of how many pairs of adjacent protrusions in each interval range have an interval within the interval. For example, the interval between 10 pairs of adjacent protrusions falls between 90 nm and 90 nm, and the interval between 20 pairs of adjacent protrusions falls between 91 nm and 92 nm, and so on.
符合本揭露的實施例中,為了決定注入角度θ,基於晶圓500的第一區域中的突起部502的高度H和相鄰的突起部502之間的間隔X1計算一第一角度θ1,使用一公式:θ1=arctan(X1/H)。相似的,基於晶圓500的第二區域中的突起部502的高度H和相鄰的突起部502之間的間隔X2計算一第二角度θ2,使用一公式:θ2=arctan(X2/H)。因此,選擇注入角度θ以使θ1θ<θ2。 In accordance with an embodiment of the present disclosure, in order to determine the injection angle θ, a first angle θ1 is calculated based on the height H of the protrusion 502 in the first region of the wafer 500 and the interval X1 between the adjacent protrusions 502, using A formula: θ1 = arctan (X1/H). Similarly, a second angle θ2 is calculated based on the height H of the protrusion 502 in the second region of the wafer 500 and the interval X2 between the adjacent protrusions 502, using a formula: θ2=arctan(X2/H) . Therefore, choose the injection angle θ to make θ1 θ < θ2.
在一些實施例中,晶圓500的第一區域中相鄰的突起部502之間的間隔X1為間隔分布中最小的間隔。在一些實施例中,晶圓500的第二區域中相鄰的突起部502之間的間隔X2為間隔分布中最大的間隔。在一些實施例中,X1和X2分別為間隔分布中最小最大的間隔。 In some embodiments, the spacing X1 between adjacent protrusions 502 in the first region of wafer 500 is the smallest of the spacing distributions. In some embodiments, the spacing X2 between adjacent protrusions 502 in the second region of wafer 500 is the largest interval in the spacing distribution. In some embodiments, X1 and X2 are the smallest and largest intervals in the interval distribution, respectively.
間隔分布可透過各種方法來決定。在一些實施例中,在基板504上形成突起部502之後,從晶圓500上切割一樣本條。測量此樣本條上的相鄰的突起部之間的間隔而因此決定此樣本條上的間隔分布(也被稱為「樣本間隔分布」)。此樣本間隔分布被用來當作整個晶圓500上的間隔分布。對於本領域具有通常知識者來所能理解的,愈多突起部502被包含在此樣本條中,此樣本間隔分布愈接近晶圓500上實際的間隔分布。 The interval distribution can be determined by various methods. In some embodiments, after the protrusions 502 are formed on the substrate 504, the same strip is cut from the wafer 500. The spacing between adjacent protrusions on the strip is measured and thus the spacing distribution on the strip (also referred to as "sample spacing distribution") is determined. This sample spacing distribution is used as an interval distribution across the wafer 500. As will be appreciated by those of ordinary skill in the art, the more protrusions 502 are included in the sample strip, the closer the sample spacing distribution is to the actual spacing distribution on the wafer 500.
在一些實施例中,可以用歷史資料來決定晶圓500上的間隔分布。相似於晶圓500的一個(或多個)晶圓且此晶圓與晶圓500於相似條件下形成多個突起部,測量此晶圓上的間隔而儲存結果。因此而決定間隔分布(也被稱為「統計間隔分布」)。被用來當作晶圓500上的間隔分布。 In some embodiments, historical data can be used to determine the spacing distribution on wafer 500. Similar to one (or more) wafers of wafer 500 and the wafers and wafers 500 form a plurality of protrusions under similar conditions, the spacing on the wafer is measured to store the results. Therefore, the interval distribution (also referred to as "statistical interval distribution") is determined. It is used as an interval distribution on the wafer 500.
如上面描述的,依據本揭露的實施例中的離子注入為一傾斜離子注入。也就是說,此離子注入並非沿著基板504的法線方向執行。離子注入的方向(也被稱為離子注入方向)因此有兩個分量,亦即水平方向的分量和垂直方向的分量。離子注入方向的水平方向的分量示意在第7A圖和第7B圖的俯視圖。第7A圖和第7B圖所示的區域可為晶圓500的同一部分或不同部分。在第7A圖中,沿著突起部502的長度L的方向(如第7A圖中的黑箭頭所示)執行離子注入,亦即由基板504的法線方向和平行於突起部502的長度方向的注入方向定義的一平面。這對應於如第5A圖、第5B圖、第6A圖和第6B圖所示的剖面圖的情形。在這種情況下,間隔分布代表相鄰的突起部502之間沿著突起部502的長度方向的間隔的分布。在一些實施例中,突起部502的長度方向對應晶圓500上的一位元線方向,因此此間隔分布代表相鄰的突起部502之間沿著晶圓500的位元線 方向上的間隔的分布。 As described above, ion implantation in accordance with embodiments of the present disclosure is a tilted ion implantation. That is, this ion implantation is not performed along the normal direction of the substrate 504. The direction of ion implantation (also referred to as ion implantation direction) therefore has two components, namely a component in the horizontal direction and a component in the vertical direction. The component in the horizontal direction of the ion implantation direction is shown in a plan view of FIGS. 7A and 7B. The regions shown in FIGS. 7A and 7B may be the same portion or different portions of the wafer 500. In FIG. 7A, ion implantation is performed along the direction of the length L of the protrusion 502 (as indicated by the black arrow in FIG. 7A), that is, the normal direction of the substrate 504 and the length direction parallel to the protrusion 502. The plane of the injection is defined by a plane. This corresponds to the case of the cross-sectional views as shown in FIGS. 5A, 5B, 6A, and 6B. In this case, the interval distribution represents a distribution of the interval between adjacent protrusions 502 along the longitudinal direction of the protrusion 502. In some embodiments, the length direction of the protrusions 502 corresponds to a one-dimensional line direction on the wafer 500, and thus the spacing distribution represents bit lines along the wafer 500 between adjacent protrusions 502. The distribution of the spacing in the direction.
另一方面,在第7B圖中,沿著突起部502的長度L的方向(如第7A圖中的黑箭頭所示)執行離子注入,亦即由基板504的法線方向和平行於突起部502的長度方向的注入方向定義的一平面。這對應於如第5A圖、第5B圖、第6A圖和第6B圖所示的剖面圖的情形。在這種情況下,間隔分布代表相鄰的突起部502之間沿著突起部502的長度方向的間隔的分布。在一些實施例中,突起部502的長度方向對應晶圓500上的一位元線方向,因此此間隔分布代表相鄰的突起部502之間沿著晶圓500的位元線方向上的間隔的分布。 On the other hand, in FIG. 7B, ion implantation is performed along the direction of the length L of the protrusion 502 (as indicated by the black arrow in FIG. 7A), that is, by the normal direction of the substrate 504 and parallel to the protrusion A plane defined by the injection direction of the length direction of 502. This corresponds to the case of the cross-sectional views as shown in FIGS. 5A, 5B, 6A, and 6B. In this case, the interval distribution represents a distribution of the interval between adjacent protrusions 502 along the longitudinal direction of the protrusion 502. In some embodiments, the length direction of the protrusions 502 corresponds to a one-dimensional line direction on the wafer 500, and thus the spacing distribution represents an interval between the adjacent protrusions 502 along the bit line direction of the wafer 500. Distribution.
第8A圖和第8B圖繪示依據本揭露一實施例製造方法半導體裝置的臨界電壓或崩潰電壓和閘極長度或閘極寬度之間的效果的示意圖。在第8A圖和第8B圖中,對應於半導體裝置的臨界電壓Vth或崩潰電壓Vpt和閘極長度L或閘極寬度W的關係的實線的曲線相似於第3A圖和第3B圖的曲線。另一方面,對應於半導體裝置的臨界電壓Vth或崩潰電壓Vpt和閘極長度L或閘極寬度W的關係的虛線的曲線為使用依據本揭露的實施例中的方法製造的。相似於第3A圖和第3B圖,第8A圖和第8B圖的每一曲線代表四種從屬關係。 8A and 8B are schematic diagrams showing effects between a threshold voltage or a breakdown voltage and a gate length or a gate width of a semiconductor device in accordance with an embodiment of the present disclosure. In FIGS. 8A and 8B, the solid line curve corresponding to the relationship between the threshold voltage Vth or the breakdown voltage Vpt of the semiconductor device and the gate length L or the gate width W is similar to the curves of FIGS. 3A and 3B. . On the other hand, a broken line curve corresponding to the relationship between the threshold voltage Vth or the breakdown voltage Vpt of the semiconductor device and the gate length L or the gate width W is manufactured using the method according to the embodiment of the present disclosure. Similar to Figures 3A and 3B, each of the curves of Figures 8A and 8B represents four affiliations.
如第8A圖和第8B圖所示,依照本揭露的實施例的製造程序的裝置的從屬曲線更平坦。因此,使用本揭露的實施例的製造方法,即使程序變化導致尺寸的偏差,特性例如晶圓上的最終的半導體裝置的電氣特性相對地比較均勻。也就是說,晶圓上的臨界電壓Vth或崩潰電壓Vpt分布變得比較狹窄,如第9圖的虛線曲線所示。在第9圖中,實線曲線代 表晶圓未使用依據本揭露的實施例的製造程序,相似於第4圖所示的曲線。 As shown in FIGS. 8A and 8B, the slave curves of the apparatus for manufacturing the program according to the embodiments of the present disclosure are flatter. Therefore, with the manufacturing method of the embodiment of the present disclosure, even if the program variation causes dimensional deviation, characteristics such as the electrical characteristics of the final semiconductor device on the wafer are relatively uniform. That is to say, the distribution of the threshold voltage Vth or the breakdown voltage Vpt on the wafer becomes relatively narrow, as shown by the broken line curve of FIG. In Figure 9, the solid curve generation The wafer of the table wafer is not used in accordance with the manufacturing procedure of the embodiment of the present disclosure, similar to the curve shown in FIG.
第10A圖和第10B圖繪示在依據一實施例執行自對準注入後的晶圓的模擬雜質分布的示意圖。特別地說,第10A圖示出了晶圓的一區域對應於如第5A圖和第6A圖所示的晶圓500的第一區域,而第10B圖示出了晶圓的一區域對應於如第5B圖和第6B圖所示的晶圓500的第二區域。在第10A圖和第10B圖中,突起部形成在同一間距上。第10A圖中的突起部的長度是110nm,而第10B圖中的突起部的長度是94nm。以注入角度為35°注入一劑3E13原子/cm2的硼離子而執行兩個傾斜注入(如第10A圖和第10B圖所示的箭頭線),一個從左側注入而另一個從右側注入。在第10A圖所示的區域中,離子被突起部擋住。另一方面,在第10B圖所示的區域中,因為突起部不能完全擋住離子,所以離子被注入到基板上突起部和雜質分佈之間的被修改的區域。應當注意的是,即使是在第10A圖中,仍有少部分離子穿過基板上突起部之間的區域注入到基板上突起部和雜質分佈之間的被修改的區域,但相對10b圖所示的量要來的少。 10A and 10B are schematic diagrams showing simulated impurity distribution of a wafer after self-aligned implantation is performed in accordance with an embodiment. In particular, FIG. 10A shows that a region of the wafer corresponds to the first region of the wafer 500 as shown in FIGS. 5A and 6A, and FIG. 10B shows that a region of the wafer corresponds to The second region of wafer 500 as shown in Figures 5B and 6B. In Figs. 10A and 10B, the projections are formed at the same pitch. The length of the protrusion in Fig. 10A is 110 nm, and the length of the protrusion in Fig. 10B is 94 nm. Two oblique implants (such as the arrow lines shown in Figs. 10A and 10B) were performed by injecting a dose of 3E13 atoms/cm 2 of boron ions at an implantation angle of 35°, one injected from the left side and the other injected from the right side. In the region shown in Fig. 10A, ions are blocked by the protrusions. On the other hand, in the region shown in Fig. 10B, since the projections do not completely block the ions, ions are implanted into the modified region between the projections on the substrate and the impurity distribution. It should be noted that even in the 10A, there is still a small amount of ions injected through the region between the protrusions on the substrate into the modified region between the protrusions on the substrate and the impurity distribution, but with respect to FIG. The amount shown is less.
第11A圖和第11B圖繪示半導體裝置的具有不同的閘極長度的模擬的臨界電壓Vth和崩潰電壓Vpt的折線圖。在第11A圖和第11B圖中,有著鑽石點的曲線代表半導體裝置未使用本揭露的實施例的自對準注入,有著方形點的曲線代表半導體裝置使用以注入角度為35°注入一劑3E13原子/cm2的的自對準注入,而有著三角形點的曲線代表半導體裝置使用以注入角度為35°注入一劑5E13原子/cm2的的自對準注入。如第11A圖和第11B圖所示,使用依據本揭露的實施例的自對準注入,裝置中的臨界電壓Vth和崩潰電壓Vpt在不同的維度都較均勻,例如不同閘極長度,亦 即抑制了臨界電壓Vth和崩潰電壓Vpt的下降(roll-off)。 11A and 11B are line graphs of the simulated threshold voltage Vth and the breakdown voltage Vpt of the semiconductor device having different gate lengths. In FIGS. 11A and 11B, the curve with the diamond dots represents the self-aligned implantation of the semiconductor device without the embodiment of the present disclosure, and the curve with the square dots represents the semiconductor device used to inject a dose of 3E13 at an implantation angle of 35°. A self-aligned implant of atoms/cm 2 , and a curve with a triangular point represents a self-aligned implant of a semiconductor device using a dose of 5E13 atoms/cm 2 at an implantation angle of 35°. As shown in FIGS. 11A and 11B, with the self-aligned implantation according to the embodiment of the present disclosure, the threshold voltage Vth and the breakdown voltage Vpt in the device are relatively uniform in different dimensions, such as different gate lengths, that is, The threshold voltage Vth and the roll-off of the breakdown voltage Vpt are suppressed.
第12A圖和第12B圖繪示依據本揭露一實施例例如形成在晶圓上的閘極結構以本揭露的實施例的一斜向離子注入突起部的垂直摻雜分布(第12A圖)以及以一垂直離子注入突起部的垂直摻雜分布(第12B圖)之間的比較的示意圖。箭頭線代表離子注入的方向。在第12A圖和第12B圖中,每一摻雜分布圖中的水平軸的字母Y代表突起部中的垂直位置。沿著如第12A圖和第12B圖所示的垂直虛線測量摻雜濃度。如第12A圖所示,對於執行依據本揭露的實施例的一斜向離子注入的一晶圓,注入的離子主要被包含在突起部靠近接收注入的一側面的區域(對角斜線陰影的區域)。在這種情況下,突起部的垂直摻雜分布是相對平坦的。另一方面,如第12B圖所示,對於不執行一斜向離子注入而執行一垂直離子注入的一晶圓,注入的離子主要被埋在突起部的區域(對角斜線陰影的區域)並且平行橫跨突起部的一側面到另一側面。這被埋的區域的深度及寬度例如取決於注入的能量和注入離子的類型以及突起部的材料。在這種情況下,突起部的垂直摻雜分布是變化劇烈的。因此,藉由測量裝置的突起部的垂直摻雜分布可決定是否在裝置的製造期間執行依據本揭露的實施例的斜向離子注入。 12A and 12B illustrate a vertical doping profile (FIG. 12A) of an oblique ion implantation protrusion according to an embodiment of the present disclosure, such as a gate structure formed on a wafer, according to an embodiment of the present disclosure; A schematic diagram of a comparison between vertical doping profiles (Fig. 12B) of a vertical ion implantation of the protrusions. The arrowed line represents the direction of ion implantation. In Figures 12A and 12B, the letter Y of the horizontal axis in each doping profile represents the vertical position in the protrusion. The doping concentration was measured along vertical dashed lines as shown in Figures 12A and 12B. As shown in FIG. 12A, for performing a wafer for oblique ion implantation according to the embodiment of the present disclosure, the implanted ions are mainly included in a region of the protrusion near a side of the receiving implant (diagonally shaded region) ). In this case, the vertical doping profile of the protrusions is relatively flat. On the other hand, as shown in FIG. 12B, for a wafer in which a vertical ion implantation is performed without performing an oblique ion implantation, the implanted ions are mainly buried in the region of the protrusion (the diagonally shaded region) and Parallel across one side of the protrusion to the other side. The depth and width of this buried region depends, for example, on the energy injected and the type of implanted ions and the material of the protrusions. In this case, the vertical doping profile of the protrusions is drastically varied. Thus, by means of the vertical doping profile of the protrusions of the measuring device it is possible to determine whether or not oblique ion implantation according to embodiments of the present disclosure is performed during manufacture of the device.
第13圖繪示依據本揭露一實施例的半導體裝置1300。半導體裝置1300依據本揭露的實施例的方法形成在基板1301上,例如上述的其中一個方法。特別的說,在半導體裝置1300的製造過程中,基板1301承受依據本揭露的實施例的斜向離子注入。 FIG. 13 illustrates a semiconductor device 1300 in accordance with an embodiment of the present disclosure. The semiconductor device 1300 is formed on the substrate 1301 in accordance with the method of the disclosed embodiments, such as one of the methods described above. In particular, during fabrication of semiconductor device 1300, substrate 1301 is subjected to oblique ion implantation in accordance with embodiments of the present disclosure.
如第13A圖所示,半導體裝置1300包含間隔1302、1304 和1306形成在基板1301上的突起部1307、1308、1309和1310之間。在一些實施例中,突起部1307、1308、1309和1310具有幾乎相同的高度,且間隔1302、1304和1306互不相同。間隔1302、1304和1306分別對應於區域1312、1314和1316形成在基板1301中並形成在相鄰的突起部1307、1308、1309和1310之間。 As shown in FIG. 13A, the semiconductor device 1300 includes intervals 1302 and 1304. And 1306 is formed between the protrusions 1307, 1308, 1309, and 1310 on the substrate 1301. In some embodiments, the protrusions 1307, 1308, 1309, and 1310 have nearly the same height, and the intervals 1302, 1304, and 1306 are different from each other. Intervals 1302, 1304, and 1306 are formed in the substrate 1301 corresponding to the regions 1312, 1314, and 1316, respectively, and are formed between adjacent protrusions 1307, 1308, 1309, and 1310.
舉例但不限制的,在第13圖中,間隔1302大於間隔1304,間隔1304又大於間隔1306。因此區域1312的寬度大於區域1314的寬度,區域1314的寬度又大於區域1316的寬度。因此斜向離子注入的結果就是對應於間隔1302的區域1312有最高的摻雜濃度,對應於間隔1304的區域1314有中等的摻雜濃度,而對應於間隔1306的區域1316有最低的摻雜濃度。而本領域具有通常知識者可理解的是,如果未執行依據本揭露的實施例的斜向離子注入,亦即沒有執行離子注入或者執行一垂直離子注入,區域1312、1314和1316的摻雜濃度會幾乎相同。 By way of example and not limitation, in FIG. 13, interval 1302 is greater than interval 1304, which is again greater than interval 1306. Thus the width of the region 1312 is greater than the width of the region 1314, which in turn is greater than the width of the region 1316. The result of the oblique ion implantation is that the region 1312 corresponding to the interval 1302 has the highest doping concentration, the region 1314 corresponding to the interval 1304 has a medium doping concentration, and the region 1316 corresponding to the interval 1306 has the lowest doping concentration. . It will be understood by those of ordinary skill in the art that doping concentrations of regions 1312, 1314, and 1316 are not performed if oblique ion implantation in accordance with embodiments of the present disclosure is not performed, i.e., no ion implantation is performed or a vertical ion implantation is performed. It will be almost the same.
本領域具有通常知識者依據本說明書和本發明揭露的實施方式容易想到其他實例。應當理解的是本說明書和這些例子僅是示範性的而非用以限定本發明。本揭露真正的保護範圍和精神在以下申請專利範圍所表示。 Other examples will be readily apparent to those skilled in the art from this disclosure and the embodiments disclosed herein. It is to be understood that the invention is not intended to be limited The true scope and spirit of the disclosure is expressed in the scope of the following claims.
500‧‧‧晶圓 500‧‧‧ wafer
502‧‧‧突起部 502‧‧‧Protruding
504‧‧‧基板 504‧‧‧Substrate
L1‧‧‧閘極長度 L1‧‧‧ gate length
H‧‧‧閘極高度 H‧‧‧ gate height
X1‧‧‧間隔 X1‧‧‧ interval
θ‧‧‧注入角度 θ ‧‧‧Injection angle
P‧‧‧間距 P‧‧‧ spacing
602‧‧‧離子 602‧‧‧ ions
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