TWI581314B - Semiconductor device and method for manufacturing the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present disclosure relates to the fabrication of semiconductor devices, and more particularly to implant processes during the fabrication of semiconductor devices.

The semiconductor device is formed on a wafer by a manufacturing process. In some cases, the semiconductor devices formed on a wafer are identical, that is, they have the same dimensions and the same characteristics. However, the manufacturing process of modern semiconductor devices may include tens or even hundreds of program steps, and program variations may result in dimensional deviations of the device. This device size deviation may cause variations in device characteristics, such as the threshold voltage Vth of the semiconductor device, or the breakdown voltage Vpt. Such variations may vary greatly as the size of the wafer increases or the size of each semiconductor device decreases.

The present disclosure provides a method of fabricating a semiconductor device including preparing a wafer including a plurality of protrusions formed on a substrate. These protrusions protrude upward on a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representative of the distribution of the spacing between adjacent protrusions, and calculating an injection angle based on the height and spacing distribution. The implantation angle is an angle between a normal direction of the substrate and an injection direction. This method also involves injecting ions at a calculated injection angle.

The present disclosure also provides a semiconductor device including a substrate and a plurality of protrusions formed on the substrate. These protrusions protrude upward on a surface of the substrate. The plurality of intervals of the adjacent protrusions are different from each other. The device also includes a plurality of doped regions formed in the substrate and formed between the protrusions. These doped regions correspond to these intervals and contain a plurality of different doping concentrations.

The features and advantages of the present disclosure are set forth in the description which follows, These features and advantages can be realized by the elements and combinations thereof particularly pointed out in the appended claims.

It is to be understood that the foregoing general descriptions

The accompanying drawings, which are incorporated in the specification of FIG

100, 500‧‧‧ wafer

102, 502, 1307, 1308, 1309, 1310‧‧ ‧ protrusions

104, 504, 1301‧‧‧ substrate

106, 106a, 106b, 1300‧‧‧ semiconductor devices

W‧‧‧ gate width

L, L1, L2‧‧‧ gate length

Vth‧‧‧ threshold voltage

Vpt‧‧‧crash voltage

H‧‧‧ gate height

P‧‧‧ spacing

X1, X2, 1302, 1304, 1306‧‧‧ interval

θ ‧‧‧Injection angle

Y‧‧‧Vertical position in the protrusion

602‧‧‧ ions

1312, 1314, 1316‧‧‧ areas

Figure 1 is a perspective view of a portion of a wafer including a plurality of protrusions formed on a substrate.

2A and 2B are cross-sectional views showing different portions of the wafer in Fig. 1.

3A and 3B are schematic diagrams showing a relationship between a threshold voltage or a breakdown voltage and a gate length or a gate width of the semiconductor device.

FIG. 4 is a schematic diagram showing the distribution of the threshold voltage and the breakdown voltage of the semiconductor device on a wafer.

5A, 5B, 6A, and 6B are cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment.

FIGS. 7A and 7B illustrate top views of a portion of a wafer by, for example, the manufacturing methods of FIGS. 5A, 5B, 6A, and 6B.

8A and 8B are schematic diagrams showing effects between a threshold voltage or a breakdown voltage and a gate length or a gate width of a semiconductor device in accordance with an embodiment of the present disclosure.

FIG. 9 is a schematic diagram showing the effect of the distribution of the threshold voltage or breakdown voltage of a semiconductor device on a wafer according to an embodiment of the present disclosure.

10A and 10B are schematic diagrams showing simulated impurity distributions of different portions of a wafer after self-aligned implantation is performed in accordance with an embodiment.

11A and 11B are line graphs of simulated threshold voltages and breakdown voltages of semiconductor devices having different gate lengths.

12A and 12B are schematic views showing a vertical doping profile of an oblique ion implantation protrusion and a comparison between the vertical ion implantation protrusions according to an embodiment of the present disclosure.

FIG. 13 is a schematic view showing different doping concentrations between adjacent protrusions of different intervals of a semiconductor device according to an embodiment of the present disclosure.

One embodiment of the present disclosure includes a method of fabricating a semiconductor device.

Embodiments of the present disclosure are described herein with reference to the drawings. Wherever possible, the same reference numerals in the drawings

FIG. 1 is a perspective view of a portion of a wafer 100 including a plurality of protrusions 102 formed on a substrate 104. The protrusions 102 are formed at a pitch P on the substrate 104. In this example, the protrusion 102 is a gate structure of the semiconductor device 106. The semiconductor device 106 can be, for example, a gold oxide half field effect transistor (MOSFET), a charge-trap memory cell, such as an oxide nitride oxide (ONO) memory cell or a floating gate memory cell. Each semiconductor device 106 is associated with a plurality of dimensional parameters, such as gate length L, gate width W, and gate height H, i.e., protrusions 102. The size parameters in the semiconductor device 106 on the wafer 100 can be different due to program variations. For example, FIGS. 2A and 2B illustrate cross-sectional views of semiconductor device 106a and semiconductor device 106b having different gate lengths L1 and L2, respectively, in different regions of wafer 100. Therefore, the electrical characteristics of the semiconductor device 106a and the semiconductor device 106b such as the threshold voltage Vth or the breakdown voltage Vpt may not be the same.

3A and 3B are schematic views showing the relationship between the threshold voltage Vth or the breakdown voltage Vpt of a semiconductor device and the gate length or the gate width. FIGS. 3A and 3B show the different doping concentrations in the substrate 104, respectively. Under the same doping conditions, a smaller device typically has a lower threshold voltage Vth or a breakdown voltage Vpt than a larger device, so the structural design margin for smaller devices is relatively small. Thus, when the device is scaled, the electrical characteristics of a smaller device are sensitive to complex thermal diffusion and program control. Accordingly, a smaller device has a limited operating current region that may be affected by a non-uniform doping profile. For example, a smaller device in a region with a high local doping concentration will have a larger threshold voltage Vth than a smaller device in a region with a low local doping concentration. On the other hand, a larger device may have a wider operating current region to balance the electrical changes caused by the non-uniform doping profile. In FIGS. 3A and 3B, the horizontal axis represents the gate length L or the gate width W, and the vertical axis represents the threshold voltage Vth or the breakdown voltage Vpt. Therefore, in Figures 3A and 3B, each curve represents four affiliations: threshold voltage Vth The relationship with the gate length L, the relationship between the threshold voltage Vth and the gate width W, the relationship between the breakdown voltage Vpt and the gate length L, and the relationship between the breakdown voltage Vpt and the gate width W.

Specifically, FIG. 3A shows a case where the doping concentration in the substrate 104 is relatively low and a short channel effect occurs. On the other hand, FIG. 3B shows a case where the doping concentration in the substrate 104 is relatively high and the reverse short channel effect occurs. As shown in FIGS. 3A and 3B, in either of the two cases, the threshold voltage Vth and the breakdown voltage Vpt are both large with devices having different gate lengths L or gate widths W. change. Thus, if semiconductor devices formed in different regions on the same wafer have different sizes, such as different gate lengths as shown in FIGS. 2A and 2B, then one or more device characteristics are, for example, on a wafer. The threshold voltage Vth or the breakdown voltage Vpt of the semiconductor device may be different, resulting in a device characteristic distribution, that is, device characteristics on the wafer are not uniform. FIG. 4 is a schematic diagram showing the distribution of the threshold voltage Vth or the breakdown voltage Vpt. In Fig. 4, the horizontal axis represents the threshold voltage Vth or the breakdown voltage Vpt, and the vertical axis represents the number of devices having a specific threshold voltage Vth or breakdown voltage Vpt. This distribution can be very broad due to program changes.

5A, 5B, 6A, and 6B are cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present disclosure. As shown in FIGS. 5A and 5B, the wafer 500 includes protrusions 502 formed on the substrate 504. The substrate 504 can be a semiconductor substrate, such as a germanium substrate or a top insulator (SOI) substrate. Even the substrate 504 can be n-type or p-type doped. In some embodiments, the semiconductor device is a transistor and the region of the substrate 504 that is covered by the protrusions 502 corresponds to the channel region of the transistor.

The protrusion 502 formed on the wafer 500 may be a structure formed during a manufacturing process of the semiconductor device, which may be removed or destroyed at a stage after the manufacturing process, or The person remains in the last device. In some embodiments, the protrusions 502 are included in a patterned layer formed of a single material, such as a dielectric such as an oxide, a nitride or an oxynitride, a semiconductor such as a single crystal germanium or A polysilicon, a metal, or a photoresist. In some embodiments, the protrusions 502 are included in a patterned layer formed of at least two materials, one of which is stacked over the other. The at least two materials can be selected, for example, from the above materials. In some embodiments, protrusion 502 is a gate structure of a transistor. These transistors may be, for example, gold oxide half field effect transistors (MOSFETs), charge extraction memory cells such as ONO memory cells or floating gate memory cells.

The protrusions 502 are formed at the same pitch P on the substrate 504 and have the same height H. FIG. 5A shows a first region of the wafer 500 in which the length of the protrusion 502 in the first region is L1 and the interval between adjacent protrusions 502 is X1. Figure 5B shows a second region of wafer 500 in which the length of protrusion 502 in the second region is L2 and the spacing between adjacent protrusions 502 is X2. In this case, due to the difference in length, L1 is greater than L2 and X1 is less than X2.

As shown in FIGS. 6A and 6B, ions 602 are implanted at an implantation angle θ on the wafer 500 as shown in FIGS. 5A and 5B to perform an ion implantation. This injection angle θ is an angle between a normal direction of the substrate 504 (dashed lines of FIGS. 6A and 6B) and an injection direction (solid lines of FIGS. 6A and 6B) in which the ions 602 are injected. The ions 602 may be at least one of an arsenic ion, a boron ion, an indium ion, a cerium ion, a nitrogen ion, a cerium ion, a carbon ion, or a phosphorus ion.

In an embodiment consistent with the present disclosure, the injection angle θ is selected such that the ions 602 in the first region shown in FIGS. 5A and 6A are completely blocked by the protrusions 502, and thus cannot be A region between adjacent protrusions 502 on the substrate 504. On the other hand, the ions 602 in the second region shown in FIGS. 5B and 6B are not completely blocked by the protrusions 502, so some ions 602 can reach the region between the adjacent protrusions 502 on the substrate 504. Such oblique implants in accordance with embodiments of the present disclosure are also referred to as self-aligned implants.

In accordance with an embodiment of the present disclosure, the injection angle θ is calculated based on an interval distribution of the height H of the protrusion 502 and the distribution of the spacing between adjacent protrusions 502 on the wafer 500. This spacing distribution may comprise a series of spacing values, such as 90 nm, 94 nm, 94 nm, 100 nm, ..., where each spacing value corresponds to the spacing between two adjacent protrusions. The spacing distribution may also include a statistical description of how many pairs of adjacent protrusions in each interval range have an interval within the interval. For example, the interval between 10 pairs of adjacent protrusions falls between 90 nm and 90 nm, and the interval between 20 pairs of adjacent protrusions falls between 91 nm and 92 nm, and so on.

In accordance with an embodiment of the present disclosure, in order to determine the injection angle θ, a first angle θ1 is calculated based on the height H of the protrusion 502 in the first region of the wafer 500 and the interval X1 between the adjacent protrusions 502, using A formula: θ1 = arctan (X1/H). Similarly, a second angle θ2 is calculated based on the height H of the protrusion 502 in the second region of the wafer 500 and the interval X2 between the adjacent protrusions 502, using a formula: θ2=arctan(X2/H) . Therefore, choose the injection angle θ to make θ1 θ < θ2.

In some embodiments, the spacing X1 between adjacent protrusions 502 in the first region of wafer 500 is the smallest of the spacing distributions. In some embodiments, the spacing X2 between adjacent protrusions 502 in the second region of wafer 500 is the largest interval in the spacing distribution. In some embodiments, X1 and X2 are the smallest and largest intervals in the interval distribution, respectively.

The interval distribution can be determined by various methods. In some embodiments, after the protrusions 502 are formed on the substrate 504, the same strip is cut from the wafer 500. The spacing between adjacent protrusions on the strip is measured and thus the spacing distribution on the strip (also referred to as "sample spacing distribution") is determined. This sample spacing distribution is used as an interval distribution across the wafer 500. As will be appreciated by those of ordinary skill in the art, the more protrusions 502 are included in the sample strip, the closer the sample spacing distribution is to the actual spacing distribution on the wafer 500.

In some embodiments, historical data can be used to determine the spacing distribution on wafer 500. Similar to one (or more) wafers of wafer 500 and the wafers and wafers 500 form a plurality of protrusions under similar conditions, the spacing on the wafer is measured to store the results. Therefore, the interval distribution (also referred to as "statistical interval distribution") is determined. It is used as an interval distribution on the wafer 500.

As described above, ion implantation in accordance with embodiments of the present disclosure is a tilted ion implantation. That is, this ion implantation is not performed along the normal direction of the substrate 504. The direction of ion implantation (also referred to as ion implantation direction) therefore has two components, namely a component in the horizontal direction and a component in the vertical direction. The component in the horizontal direction of the ion implantation direction is shown in a plan view of FIGS. 7A and 7B. The regions shown in FIGS. 7A and 7B may be the same portion or different portions of the wafer 500. In FIG. 7A, ion implantation is performed along the direction of the length L of the protrusion 502 (as indicated by the black arrow in FIG. 7A), that is, the normal direction of the substrate 504 and the length direction parallel to the protrusion 502. The plane of the injection is defined by a plane. This corresponds to the case of the cross-sectional views as shown in FIGS. 5A, 5B, 6A, and 6B. In this case, the interval distribution represents a distribution of the interval between adjacent protrusions 502 along the longitudinal direction of the protrusion 502. In some embodiments, the length direction of the protrusions 502 corresponds to a one-dimensional line direction on the wafer 500, and thus the spacing distribution represents bit lines along the wafer 500 between adjacent protrusions 502. The distribution of the spacing in the direction.

On the other hand, in FIG. 7B, ion implantation is performed along the direction of the length L of the protrusion 502 (as indicated by the black arrow in FIG. 7A), that is, by the normal direction of the substrate 504 and parallel to the protrusion A plane defined by the injection direction of the length direction of 502. This corresponds to the case of the cross-sectional views as shown in FIGS. 5A, 5B, 6A, and 6B. In this case, the interval distribution represents a distribution of the interval between adjacent protrusions 502 along the longitudinal direction of the protrusion 502. In some embodiments, the length direction of the protrusions 502 corresponds to a one-dimensional line direction on the wafer 500, and thus the spacing distribution represents an interval between the adjacent protrusions 502 along the bit line direction of the wafer 500. Distribution.

8A and 8B are schematic diagrams showing effects between a threshold voltage or a breakdown voltage and a gate length or a gate width of a semiconductor device in accordance with an embodiment of the present disclosure. In FIGS. 8A and 8B, the solid line curve corresponding to the relationship between the threshold voltage Vth or the breakdown voltage Vpt of the semiconductor device and the gate length L or the gate width W is similar to the curves of FIGS. 3A and 3B. . On the other hand, a broken line curve corresponding to the relationship between the threshold voltage Vth or the breakdown voltage Vpt of the semiconductor device and the gate length L or the gate width W is manufactured using the method according to the embodiment of the present disclosure. Similar to Figures 3A and 3B, each of the curves of Figures 8A and 8B represents four affiliations.

As shown in FIGS. 8A and 8B, the slave curves of the apparatus for manufacturing the program according to the embodiments of the present disclosure are flatter. Therefore, with the manufacturing method of the embodiment of the present disclosure, even if the program variation causes dimensional deviation, characteristics such as the electrical characteristics of the final semiconductor device on the wafer are relatively uniform. That is to say, the distribution of the threshold voltage Vth or the breakdown voltage Vpt on the wafer becomes relatively narrow, as shown by the broken line curve of FIG. In Figure 9, the solid curve generation The wafer of the table wafer is not used in accordance with the manufacturing procedure of the embodiment of the present disclosure, similar to the curve shown in FIG.

10A and 10B are schematic diagrams showing simulated impurity distribution of a wafer after self-aligned implantation is performed in accordance with an embodiment. In particular, FIG. 10A shows that a region of the wafer corresponds to the first region of the wafer 500 as shown in FIGS. 5A and 6A, and FIG. 10B shows that a region of the wafer corresponds to The second region of wafer 500 as shown in Figures 5B and 6B. In Figs. 10A and 10B, the projections are formed at the same pitch. The length of the protrusion in Fig. 10A is 110 nm, and the length of the protrusion in Fig. 10B is 94 nm. Two oblique implants (such as the arrow lines shown in Figs. 10A and 10B) were performed by injecting a dose of 3E13 atoms/cm ² of boron ions at an implantation angle of 35°, one injected from the left side and the other injected from the right side. In the region shown in Fig. 10A, ions are blocked by the protrusions. On the other hand, in the region shown in Fig. 10B, since the projections do not completely block the ions, ions are implanted into the modified region between the projections on the substrate and the impurity distribution. It should be noted that even in the 10A, there is still a small amount of ions injected through the region between the protrusions on the substrate into the modified region between the protrusions on the substrate and the impurity distribution, but with respect to FIG. The amount shown is less.

11A and 11B are line graphs of the simulated threshold voltage Vth and the breakdown voltage Vpt of the semiconductor device having different gate lengths. In FIGS. 11A and 11B, the curve with the diamond dots represents the self-aligned implantation of the semiconductor device without the embodiment of the present disclosure, and the curve with the square dots represents the semiconductor device used to inject a dose of 3E13 at an implantation angle of 35°. A self-aligned implant of atoms/cm ² , and a curve with a triangular point represents a self-aligned implant of a semiconductor device using a dose of 5E13 atoms/cm ² at an implantation angle of 35°. As shown in FIGS. 11A and 11B, with the self-aligned implantation according to the embodiment of the present disclosure, the threshold voltage Vth and the breakdown voltage Vpt in the device are relatively uniform in different dimensions, such as different gate lengths, that is, The threshold voltage Vth and the roll-off of the breakdown voltage Vpt are suppressed.

12A and 12B illustrate a vertical doping profile (FIG. 12A) of an oblique ion implantation protrusion according to an embodiment of the present disclosure, such as a gate structure formed on a wafer, according to an embodiment of the present disclosure; A schematic diagram of a comparison between vertical doping profiles (Fig. 12B) of a vertical ion implantation of the protrusions. The arrowed line represents the direction of ion implantation. In Figures 12A and 12B, the letter Y of the horizontal axis in each doping profile represents the vertical position in the protrusion. The doping concentration was measured along vertical dashed lines as shown in Figures 12A and 12B. As shown in FIG. 12A, for performing a wafer for oblique ion implantation according to the embodiment of the present disclosure, the implanted ions are mainly included in a region of the protrusion near a side of the receiving implant (diagonally shaded region) ). In this case, the vertical doping profile of the protrusions is relatively flat. On the other hand, as shown in FIG. 12B, for a wafer in which a vertical ion implantation is performed without performing an oblique ion implantation, the implanted ions are mainly buried in the region of the protrusion (the diagonally shaded region) and Parallel across one side of the protrusion to the other side. The depth and width of this buried region depends, for example, on the energy injected and the type of implanted ions and the material of the protrusions. In this case, the vertical doping profile of the protrusions is drastically varied. Thus, by means of the vertical doping profile of the protrusions of the measuring device it is possible to determine whether or not oblique ion implantation according to embodiments of the present disclosure is performed during manufacture of the device.

FIG. 13 illustrates a semiconductor device 1300 in accordance with an embodiment of the present disclosure. The semiconductor device 1300 is formed on the substrate 1301 in accordance with the method of the disclosed embodiments, such as one of the methods described above. In particular, during fabrication of semiconductor device 1300, substrate 1301 is subjected to oblique ion implantation in accordance with embodiments of the present disclosure.

As shown in FIG. 13A, the semiconductor device 1300 includes intervals 1302 and 1304. And 1306 is formed between the protrusions 1307, 1308, 1309, and 1310 on the substrate 1301. In some embodiments, the protrusions 1307, 1308, 1309, and 1310 have nearly the same height, and the intervals 1302, 1304, and 1306 are different from each other. Intervals 1302, 1304, and 1306 are formed in the substrate 1301 corresponding to the regions 1312, 1314, and 1316, respectively, and are formed between adjacent protrusions 1307, 1308, 1309, and 1310.

By way of example and not limitation, in FIG. 13, interval 1302 is greater than interval 1304, which is again greater than interval 1306. Thus the width of the region 1312 is greater than the width of the region 1314, which in turn is greater than the width of the region 1316. The result of the oblique ion implantation is that the region 1312 corresponding to the interval 1302 has the highest doping concentration, the region 1314 corresponding to the interval 1304 has a medium doping concentration, and the region 1316 corresponding to the interval 1306 has the lowest doping concentration. . It will be understood by those of ordinary skill in the art that doping concentrations of regions 1312, 1314, and 1316 are not performed if oblique ion implantation in accordance with embodiments of the present disclosure is not performed, i.e., no ion implantation is performed or a vertical ion implantation is performed. It will be almost the same.

Other examples will be readily apparent to those skilled in the art from this disclosure and the embodiments disclosed herein. It is to be understood that the invention is not intended to be limited The true scope and spirit of the disclosure is expressed in the scope of the following claims.

500‧‧‧ wafer

502‧‧‧Protruding

504‧‧‧Substrate

L1‧‧‧ gate length

H‧‧‧ gate height

X1‧‧‧ interval

θ ‧‧‧Injection angle

P‧‧‧ spacing

602‧‧‧ ions

Claims (29)

A method of fabricating a semiconductor device, comprising: preparing a wafer including a plurality of protrusions formed on a substrate, the protrusions protruding upward on a surface of the substrate and having a height measured from the surface of the substrate Determining a spacing distribution representative of the distribution of the spacing between adjacent protrusions, wherein the lengths of the protrusions are not identical; calculating an implantation angle based on the height and the spacing distribution, the implantation angle being the substrate An angle between a normal direction and an injection direction; and injecting ions at the calculated injection angle. The manufacturing method of claim 1, wherein the calculating the injection angle comprises: selecting a first interval and a second interval from the interval distribution, the first interval being smaller than the second interval; Calculating a first angle according to the height and the first interval; calculating a second angle based on the height and the second interval; and setting a third angle smaller than the second angle and greater than or equal to the first angle as the injection angle . The manufacturing method of claim 2, wherein the step of setting the third angle as the injection angle comprises setting the third angle to be equal to the first angle as the injection angle. The manufacturing method of claim 2, wherein the step of selecting the first interval and the second interval comprises: selecting a minimum interval from the interval distribution as the first interval; A maximum interval is selected from the interval distribution as the second interval. The manufacturing method of claim 1, wherein the step of preparing the wafer including the protrusions comprises preparing the wafer of a plurality of gate structures including a plurality of transistors. The manufacturing method of claim 5, wherein the step of preparing the wafers including the gate structures of the plurality of transistors comprises preparing the gate structures including a plurality of MOS field-effect transistors The wafer. The manufacturing method of claim 5, wherein the step of preparing the wafer including the gate structures of the transistors comprises preparing a plurality of oxide nitride oxide (ONO) memory cells. The gate structure of the wafer. The manufacturing method of claim 5, wherein the step of preparing the wafers including the gate structures of the plurality of transistors comprises preparing the gate structures including a plurality of floating memory cells Wafer. The manufacturing method of claim 1, wherein the step of preparing the wafer including the protrusions comprises preparing the wafer including a patterned layer formed of a single material. The manufacturing method of claim 9, wherein the step of preparing the wafer comprising the patterned layer formed of the single material comprises preparing to comprise an oxide, a nitride, an oxynitride, a The wafer of the patterned layer formed by a semiconductor, a metal or a photoresist. The manufacturing method of claim 1, wherein the step of preparing the wafer including the protrusions comprises preparing the wafer including a patterned layer formed of a multilayer material. The manufacturing method of claim 11, wherein the step of preparing the wafer comprising the patterned layer formed of the multilayer material comprises preparing to comprise an oxide, a nitride, an oxynitride, a Forming a patterned layer of at least two of a semiconductor, a metal or a photoresist The wafer, one of which is stacked on top of another material. The manufacturing method of claim 1, wherein the step of preparing the wafer including the protrusions comprises preparing the wafer including the protrusions formed on a substrate. The manufacturing method of claim 1, wherein the step of preparing the wafer including the protrusions comprises preparing the wafer including the protrusions formed on an upper insulator substrate. The manufacturing method of claim 1, wherein the step of determining the interval distribution comprises determining a distribution of intervals between adjacent ones of the protrusions along a direction of a word line of the wafer. Interval distribution. The manufacturing method of claim 1, wherein the step of determining the interval distribution comprises determining a distribution of intervals between adjacent ones of the protrusions along a one-dimensional line direction of the wafer. Interval distribution. The manufacturing method of claim 1, wherein the step of determining the interval distribution comprises: cutting the same strip from the wafer; measuring an interval between adjacent protrusions on the sample strip; and setting The same interval distribution representing the distribution of the intervals between the adjacent protrusions on the sample strip is distributed as the interval. The manufacturing method of claim 1, wherein the step of determining the interval distribution comprises: measuring an interval between adjacent protrusions on the same wafer similar to the wafer, the sample crystal a circle and the wafer form a plurality of protrusions under similar conditions; A statistical interval distribution representing a distribution of intervals between adjacent ones of the sample wafers is set as the interval distribution. The manufacturing method according to claim 1, wherein the step of implanting ions comprises implanting at least one of an arsenic ion, a boron ion, an indium ion, a cerium ion, a nitrogen ion, a cerium ion, a carbon ion, or a phosphorus ion. A semiconductor device comprising: a substrate; a plurality of protrusions formed on the substrate, the protrusions protruding upward on a surface of the substrate, the lengths of the protrusions are not completely the same, and the protrusions are adjacent The plurality of portions are different from each other; and a plurality of doped regions are formed in the substrate and formed between the protrusions, the doped regions are spaced apart and comprise a plurality of different doping concentrations. The semiconductor device of claim 20, wherein the doping concentrations in the doped regions are proportional to the intervals. The semiconductor device of claim 20, wherein the protrusions have substantially the same height. The semiconductor device of claim 20, wherein the protrusions comprise a plurality of gate structures of a plurality of transistors. The semiconductor device of claim 20, wherein the protrusions belong to a patterned layer. The semiconductor device of claim 20, wherein the patterned layer comprises a single material patterned layer. The semiconductor device of claim 20, wherein the patterned layer comprises a multi-layer material patterned layer. The semiconductor device according to claim 20, wherein the protrusion is disposed along a line direction of the semiconductor device. The semiconductor device according to claim 20, wherein the protrusion is disposed along a one-dimensional line direction of the semiconductor device. The semiconductor device according to claim 20, wherein the doped region is doped with at least one of an arsenic ion, a boron ion, an indium ion, a cerium ion, a nitrogen ion, a cerium ion, a carbon ion, or a phosphorus ion.