CN110828380B - Static memory cell and forming method thereof - Google Patents

Static memory cell and forming method thereof Download PDF

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Publication number
CN110828380B
CN110828380B CN201810923960.3A CN201810923960A CN110828380B CN 110828380 B CN110828380 B CN 110828380B CN 201810923960 A CN201810923960 A CN 201810923960A CN 110828380 B CN110828380 B CN 110828380B
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substrate
opening
region
source
drain
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CN110828380A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides a static memory unit and a forming method thereof.A first ion implantation process is firstly carried out on a source region in a fin part independently, and then a second ion implantation process is carried out on the source region and a drain region to form a source electrode and a drain electrode, so that the doping concentration of the source electrode is larger than that of the drain electrode, and when the static memory unit is subsequently read and written, the current from the source electrode to the drain electrode is not equal to the current from the drain electrode to the source electrode, namely the read current is not equal to the write current, thereby reducing the read/write margin and improving the reliability and performance of a device.

Description

Static memory cell and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for forming a static memory cell and a static memory cell.
Background
A Fin Field effect transistor (FinFET) in a static memory is a novel metal oxide semiconductor Field effect transistor, and compared with a conventional static memory, the FinFET has a smaller size and better performance, but the reliability and performance of the existing FinFET need to be improved.
Disclosure of Invention
The invention provides a static memory cell and a method for forming the same, which are used for improving the reliability and performance of the conventional fin field effect transistor.
In order to achieve the above object, the present invention provides a method for forming a static memory cell, including:
providing a substrate, wherein the substrate comprises a substrate and a fin part formed on the substrate, and the fin part comprises a source electrode region and a drain electrode region;
sequentially forming a polycrystalline silicon material layer covering the substrate and the fin part and a first dielectric layer covering the polycrystalline silicon material layer on the substrate;
forming a first opening corresponding to the source electrode region in the first dielectric layer, wherein a part of the polycrystalline silicon material layer is exposed out of the first opening;
forming a first side wall on the side wall of the first opening to form a second opening aligned with the source region, and performing a first ion implantation process to perform ion implantation on the source region;
removing the remaining first dielectric layer, the polysilicon material layer below the remaining first dielectric layer and the polysilicon material layer below the second opening to form a third opening aligned with the source region and a fourth opening aligned with the drain region;
performing a second ion implantation process to implant ions into the source region and the drain region to form a source and a drain.
Optionally, the ion implantation concentration of the source is higher than that of the drain.
Optionally, the ions implanted into the source region include arsenic ions and/or phosphorus ions, and the ions implanted into the drain region include boron ions and/or boron fluoride ions.
Optionally, in the first ion implantation process, the energy of ion implantation performed on the source region is greater than or equal to 105ev; in the second ion implantation process, the energy of the ion implantation performed on the source region and the drain region is less than 105ev。
Optionally, after the third opening and the fourth opening are formed and before the second ion implantation process is performed, the method for forming the static memory cell further includes:
removing the first side wall;
and forming second side walls on the side walls of the third opening and the fourth opening.
Optionally, the width of the cross section of the first side wall is 10nm to 15 nm.
Optionally, a second dielectric layer is further formed between the polysilicon material layer and the first dielectric layer, and the material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, or silicon oxynitride.
Optionally, gate dielectric layers are formed between the second dielectric layer and the polysilicon material layer and between the fin portion and the polysilicon material layer.
Optionally, the material of the first dielectric layer includes one of amorphous carbon or amorphous silicon.
The invention also provides a static storage unit, which comprises a plurality of static storage units, wherein the static storage unit comprises:
the substrate comprises a substrate and a fin part formed on the substrate, wherein a source electrode and a drain electrode are formed in the fin part, and the ion implantation concentration of the source electrode is greater than that of the drain electrode;
and the grid structure is positioned on the substrate, is positioned between the source electrode and the drain electrode and covers the top wall and the side wall of the fin part.
In the method for forming the static storage unit and the static storage unit, a first ion implantation process is performed on a source region in the fin part at first, and then a second ion implantation process is performed on the source region and a drain region to form a source electrode and a drain electrode, so that the doping concentration of the source electrode is larger than that of the drain electrode, and when the static storage unit is subjected to read-write operation subsequently, the current from the source electrode to the drain electrode is not equal to the current from the drain electrode to the source electrode, namely the read current is not equal to the write current, so that the read/write margin is reduced, and the reliability and the performance of a device are improved.
Drawings
FIG. 1 is a flow chart of a method for forming a static memory cell according to an embodiment of the present invention;
FIGS. 2-8 are schematic cross-sectional views of a semiconductor structure formed by the method for forming a static memory cell according to an embodiment of the present invention;
the structure comprises a substrate 1, a substrate 11, a fin part 12, a first oxide layer 21, a second oxide layer 22, a polycrystalline silicon material layer 3, a second dielectric layer 4, a first dielectric layer 5, a first side wall 61, a second side wall 62, a first opening 71, a second opening 72, a third opening 73, a fourth opening 74, a source 81, a drain 82 and a first side wall H.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, which is a flowchart illustrating a method for forming a static memory cell according to the present embodiment, the method for forming a static memory cell includes:
s1: providing a substrate, wherein the substrate comprises a substrate and a fin part formed on the substrate, and the fin part comprises a source electrode region and a drain electrode region;
s2: sequentially forming a polycrystalline silicon material layer covering the substrate and the fin part and a first dielectric layer covering the polycrystalline silicon material layer on the substrate;
s3: forming a first opening corresponding to the source electrode region in the first dielectric layer, wherein a part of the polycrystalline silicon material layer is exposed out of the first opening;
s4: forming a first side wall on the side wall of the first opening to form a second opening aligned with the source region, and performing a first ion implantation process to perform ion implantation on the source region;
s5: removing the remaining first dielectric layer, the polysilicon material layer below the remaining first dielectric layer and the polysilicon material layer below the second opening to form a third opening aligned with the source region and a fourth opening aligned with the drain region;
s6: performing a second ion implantation process to implant ions into the source region and the drain region to form a source and a drain.
According to the invention, firstly, the source region in the fin part is subjected to primary ion implantation, and then the source region and the drain region are subjected to primary ion implantation to form the source electrode and the drain electrode, so that the doping concentrations of the source electrode and the drain electrode are different, and when the static memory cell is subjected to subsequent read-write operation, the current from the source region to the drain region is unequal to the current from the drain region to the source region, namely the read current is unequal to the write current, so that the read/write allowance is reduced, and the reliability and the performance of the device are improved.
Specifically, referring to fig. 2 to 8, which are schematic cross-sectional views of a semiconductor structure formed by the method for forming a static memory cell according to the present embodiment, the method for forming a static memory cell according to the present invention will be further described with reference to fig. 2 to 8.
First, referring to fig. 2, a substrate 1 is provided, where the substrate 1 includes a substrate 11 and a fin portion 12, in this embodiment, the substrate 11 is a silicon substrate, of course, the material of the substrate 11 may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, the substrate 11 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, and optionally, the material of the fin portion 12 is the same as the material of the substrate 11. Specifically, the step of forming the substrate 1 includes: providing a silicon material layer, forming a patterned hard mask layer on the silicon material layer, etching the silicon material layer by using the hard mask layer as a mask to form a plurality of discrete protrusions, wherein the protrusions are fin portions 12, the etched silicon material layer is used as a substrate 11, further, the side walls of the fin portions 12 are perpendicular to the surface of the substrate 11, that is, the top size of the fin portions 12 is equal to the bottom size, in other embodiments, the top size of the fin portions 12 can also be smaller than the bottom size thereof, further, the fin portions 12 include source regions and drain regions which are arranged in a staggered manner, that is, the source regions and the drain regions on the fin portions 12 are alternately arranged in a source region-drain region-source region-drain region manner.
Referring to fig. 3, a first oxide layer 21, a polysilicon material layer 3, a second oxide layer 22 and a second dielectric layer 4 are sequentially formed on the substrate 1, the first oxide layer 21 covers the top wall and the sidewall of the fin portion 12, the polysilicon material layer 3 covers the first oxide layer 21, the second oxide layer 22 covers the polysilicon material layer 3, the first oxide layer 21 and the second oxide layer 22 are both gate dielectric layers which serve to isolate and protect the polysilicon material layer 3, and the first oxide layer 21 and the second oxide layer 22 are both made of high-k dielectric materials, wherein the high-k gate dielectric materials refer to gate dielectric materials having a relative dielectric constant greater than that of silicon oxide, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO 2 or Al2O 3. The second dielectric layer 4 covers the second oxide layer 22, the material of the second dielectric layer 4 may be one or more of silicon oxide, silicon nitride, or silicon oxynitride, and the second dielectric layer 4 may serve as a hard mask layer to protect the polysilicon material layer 3 in a subsequent etching process. And then forming a first dielectric layer 5 on the second dielectric layer 4, wherein the material of the first dielectric layer 5 can be an amorphous material, such as amorphous carbon and/or amorphous silicon. The method for forming the first oxide layer 21, the polysilicon material layer 3, the second oxide layer 22, the second dielectric layer 4 and the first dielectric layer 5 may be chemical vapor deposition, physical vapor deposition or atomic layer deposition, which is not limited in the present invention.
Next, referring to fig. 4 to 5, an etching process is used to remove a portion of the first dielectric layer 5, and a plurality of first openings 71 are formed, so that the first dielectric layer 5 is patterned, where the positions of the first openings 71 may correspond to the source regions of the fins 12, and the size of the first openings 71 may be slightly larger than the size of the source regions, so as to leave positions for the first sidewalls 61 to be formed subsequently. Then, as shown in fig. 5, a first sidewall 61 is formed on a sidewall of the first opening 71 to form a second opening 72, and it can be understood that the first sidewall 61 occupies a portion of the first opening 71, which results in a reduction in the size of the first opening 71, thereby forming the second opening 72, and the second opening 72 is still aligned with the source region. Optionally, an annealing process may be performed on the first side wall 61 to enhance the compactness of the first side wall 61, further, the cross-sectional width H of the first side wall 61 may be consistent with the length of a subsequently formed gate, and optionally, the cross-sectional width H of the first side wall 61 is 10nm to 15nm, and of course, the cross-sectional width H of the first side wall 61 may be adjusted according to the length of a gate of a device that is formed according to actual needs, which is not illustrated here.
Referring to fig. 5, a first ion implantation process is performed on the source region of the fin 12 by using the first sidewall 61 and the remaining first dielectric layer 5 AS masks, the implanted impurity ions are N-type impurity ions, such AS Arsenic (AS) ions and/or phosphorus (P) ions, and the portion of the fin 12 blocked by the first sidewall 61 and the remaining first dielectric layer 5 is not doped with impurity ions. Further, since a plurality of thicker film layers still remain above the fin portion 12, the implantation energy of the first ion implantation process may be larger, for example, larger than or equal to 100000eV, so as to ensure the depth of ion implantation, so that the impurity ions are implanted into the fin portion 12.
Referring to fig. 6, the remaining first dielectric layer 5 is removed, and then the second dielectric layer 4, the second oxide layer 22 and the polysilicon material layer 3 under the second opening 72 and the remaining first dielectric layer 5 are etched to remove the third opening 73 and the fourth opening 74, while only the second dielectric layer 4, the second oxide layer 22 and the polysilicon material layer 3 under the first sidewall 61 are remained, and at this time, the remaining polysilicon material layer 3 is used as a gate electrode, and forms a gate structure together with a sidewall and a gate dielectric layer which are subsequently formed to be protected on the sidewall of the polysilicon material layer 3. As shown in fig. 6, the third opening 73 is aligned with the source region, and the fourth opening 74 is aligned with the drain region.
Referring to fig. 7 to 8, the first sidewall 61 is removed, a second sidewall 62 is formed on the sidewalls of the third opening 73 and the fourth opening 74, and an annealing process is performed on the second sidewall 62, wherein the second sidewall 62 and the first sidewall 61 may be made of silicon oxide, so as to protect the sidewalls of the polysilicon material layer 3, and thus, the periphery of the polysilicon material layer 3 is isolated and protected by an insulating material. Finally, referring to fig. 8, a second ion implantation process is performed on the source region aligned with the third opening 73 and the drain region aligned with the fourth opening 73, so that the source region forms a source 81 and the drain region forms a drain 82. At this time, since the source region is subjected to ion implantation twice (first ion implantation process and second ion implantation process), and the drain region is subjected to ion implantation only once (second ion implantation process), the ion implantation concentration of the source region 81 is formed to be greater than that of the drain region 82. Further, the impurity ions implanted twice into the source region may be kept uniform, and the impurity ions implanted into the drain region may be P-type impurity ions, such as boron (B) ions and/or boron fluoride (BF2) ions. Since only one layer of the first oxide layer 21 is formed above the fin 12, the energy of the ion implantation in the second ion implantation process may be reduced accordingly, for example, may be smaller than 100000 eV.
After two ion implantation processes, the impurity ion concentration of the source 81 is greater than that of the drain 82, and further, during reading/writing, the current flowing from the source 81 to the drain 82 is not equal to the current flowing from the drain 82 to the source 81, that is, the reading current is not equal to the writing current, so that the reading/writing margin is reduced, and the reliability and performance of the device are improved.
The embodiment also provides a static memory cell, and the static memory cell is formed by adopting the forming method of the static memory cell.
Specifically, as shown in fig. 8, the static memory cell includes a substrate 1, where the substrate 1 includes a substrate 11 and a fin portion 12 formed on the substrate 11, a source 81 and a drain 82 are formed in the fin portion 12, and an ion implantation concentration of the source 81 is greater than an ion implantation concentration of the drain 82; and the gate structure is positioned on the substrate 1, is positioned between the source electrode 81 and the drain electrode 82 and covers the top wall and the side wall of the fin part 12.
Optionally, the gate structure includes a gate electrode made of a polysilicon material, and a gate dielectric layer and a second sidewall surrounding the gate electrode, where the gate dielectric layer and the second sidewall are used to protect the gate electrode from being damaged.
In summary, in the method for forming a static memory cell and the static memory cell provided in the embodiments of the present invention, a first ion implantation process is performed on a source region in the fin portion, and then a second ion implantation process is performed on the source region and a drain region to form a source and a drain, so that a doping concentration of the source is higher than a doping concentration of the drain, and when a read/write operation is performed on the static memory cell subsequently, a current from the source to the drain is not equal to a current from the drain to the source, that is, a read current is not equal to a write current, thereby reducing a read/write margin and improving reliability and performance of a device.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A method for forming a static memory cell, the method comprising:
providing a substrate, wherein the substrate comprises a substrate and a fin part formed on the substrate, and the fin part comprises a source electrode region and a drain electrode region;
sequentially forming a polycrystalline silicon material layer covering the substrate and the fin part and a first medium layer covering the polycrystalline silicon material layer on the substrate;
forming a first opening corresponding to the source electrode region in the first dielectric layer, wherein a part of the polycrystalline silicon material layer is exposed out of the first opening;
forming a first side wall on the side wall of the first opening to form a second opening aligned with the source electrode region, and performing a first ion implantation process to implant ions into the source electrode region;
removing the remaining first dielectric layer, the polysilicon material layer below the remaining first dielectric layer and the polysilicon material layer below the second opening to form a third opening aligned with the source region and a fourth opening aligned with the drain region;
performing a second ion implantation process to implant ions into the source region and the drain region to form a source and a drain.
2. The method of claim 1, wherein the source is implanted with ions at a higher concentration than the drain.
3. The method of claim 2, wherein the source region implanted ions comprise arsenic ions and/or phosphorous ions and the drain region implanted ions comprise boron ions and/or boron fluoride ions.
4. The method of claim 1, wherein the first ion implantation is performed with an energy of 10 or more for implanting ions into the source region5ev; in the second ion implantation process, the energy of the ion implantation performed on the source region and the drain region is less than 105ev。
5. The method of claim 1, wherein after forming the third opening and the fourth opening and before performing the second ion implantation process, the method further comprises:
removing the first side wall;
and forming second side walls on the side walls of the third opening and the fourth opening.
6. The method of claim 1, wherein the first sidewall spacers have a cross-sectional width of 10nm to 15 nm.
7. The method of claim 1, wherein a second dielectric layer is formed between the polysilicon material layer and the first dielectric layer, and the second dielectric layer comprises one or more of silicon oxide, silicon nitride, or silicon oxynitride.
8. The method of claim 7, wherein gate dielectric layers are formed between the second dielectric layer and the polysilicon material layer and between the fin and the polysilicon material layer.
9. The method of claim 1, wherein a material of the first dielectric layer comprises one of amorphous carbon or amorphous silicon.
10. A static memory cell formed by the method of any of claims 1 to 9, the static memory cell comprising:
the substrate comprises a substrate and a fin part formed on the substrate, wherein a source electrode and a drain electrode are formed in the fin part, and the ion implantation concentration of the source electrode is greater than that of the drain electrode;
and the grid structure is positioned on the substrate, is positioned between the source electrode and the drain electrode and covers the top wall and the side wall of the fin part.
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