WO2009040707A2 - Method of manufacturing a finfet - Google Patents

Method of manufacturing a finfet Download PDF

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Publication number
WO2009040707A2
WO2009040707A2 PCT/IB2008/053801 IB2008053801W WO2009040707A2 WO 2009040707 A2 WO2009040707 A2 WO 2009040707A2 IB 2008053801 W IB2008053801 W IB 2008053801W WO 2009040707 A2 WO2009040707 A2 WO 2009040707A2
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Prior art keywords
fin
finfet
gate
extension regions
channel
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PCT/IB2008/053801
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French (fr)
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WO2009040707A3 (en
Inventor
Gerben Doornbos
Bartlomiej Jan Pawlak
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Nxp B.V.
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Publication of WO2009040707A2 publication Critical patent/WO2009040707A2/en
Publication of WO2009040707A3 publication Critical patent/WO2009040707A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the invention relates to a method of manufacturing a fin field effect transistor, hereinafter termed a finFET, having a semiconductor fin protruding upward from a substrate, the fin comprising source and drain regions laterally disposed either side of a channel each separated therefrom by respective extension regions, and a gate disposed on at least one side of the channel and insulated therefrom by a gate dielectric layer.
  • a finFET having a semiconductor fin protruding upward from a substrate, the fin comprising source and drain regions laterally disposed either side of a channel each separated therefrom by respective extension regions, and a gate disposed on at least one side of the channel and insulated therefrom by a gate dielectric layer.
  • CMOS complementary metal-oxide-semiconductor
  • CMOS 32nm node onwards From the CMOS 32nm node onwards, conventional planar bulk MOSFETs are assumed to suffer too severely from SCEs to be considered as the primary technology architecture for CMOS circuits. Also, mainly due to drain induced barrier lowering resulting from electric field penetration through the underlying buried oxide, single gate thin-body silicon on insulator (SOI) is unlikely to provide a scalable alternative to conventional planar bulk CMOS.
  • SOI silicon on insulator
  • Multi-gate transistors look to provide a promising alternative to the well- established single-gate MOSFET to enable further scaling down.
  • a thin semiconductor channel is controlled from more than one side giving better control over any SCEs.
  • multi-gate architectures the planar dual gate, the vertical dual gate and the finFET.
  • planar dual gate transistor appears most similar to the conventional bulk MOSFET. It imposes the least changes on circuit layout level, and thus it is the preferred multi-gate architecture, especially by designers. Unfortunately, the device is technologically very difficult to fabricate; the very tight alignment requirements of top and bottom gate being the bottleneck. In the vertical dual gate, both the channel and the current flow are out of plane; this architecture is not considered on large scale due to layout issues.
  • the current flows parallel to the carrier wafer, so that in top view a finFET is still quite similar to a planar MOSFET.
  • the channels are (predominantly) vertical located in the fin which exposes two or three sides through which a gate can influence the conduction channels.
  • Figure 1 shows, in very simplified form, a perspective view of finFET 10 on a substrate 11.
  • the device comprises a semiconductor fin 12 protruding upward from the substrate 11.
  • the fin comprises a conduction channel (not visible), current through which is controlled by the overlying 'all-round' gate 15. Either side of the channel, the fin comprises a doped source region 16 and a drain region 18 between which current flows via the channel. Directly adjacent the channel, the fin 12 comprises source and drain extension regions 20 having a lower doping level than the respective source and drain regions 16,18.
  • Alternative terms used in the art for the extension regions 20 include field-relief regions or lightly doped drain (LDD) regions, whilst alternative terms used for the source and drain regions 16,18 include heavily doped drain (HDD).
  • the gate 15 is insulated from the channel by a gate dielectric layer 22.
  • the gate shown in Figure 1 is disposed around all three exposed sides of the channel, it is quite possible, for example, for the device to instead comprise two separate gates, each one disposed on one of the vertical exposed sides of the channel region of the fin 12, thus leaving the top surface of the fin uncovered.
  • US-2005/0186742 discloses such a finFET.
  • an oblique ion implantation technique is employed to implant dopant species into the exposed surfaces of the fin to form source and drain regions. This involves implanting dopant ions at an angle to ensure that the ions are implanted into both the sidewalls and the top surface of the fin, i.e. to reach a certain level of conformality.
  • Doping the side walls of the fin from top to bottom is particularly important in the extension regions, because those regions must form a lowly- resistive path between heavily doped source/drain regions and the inversion channels under the gate, which are predominantly vertical and extend from top to bottom.
  • One possible method to dope the fin all the way from top to bottom would be an ion implantation in the vertical direction, or under a small tilt angle, as is typically done in planar devices.
  • a high-energy implant is needed in combination with a thermal step to distribute the dopants vertically by diffusion.
  • dopants also diffuse in the lateral direction, which is perfectly acceptable for the heavily doped source/drain, but excessive diffusion of dopants from the extension regions into the channel under the gate would lead to severe short-channel effects. Therefore, like in planar devices, it is not favoured for the extension regions to be formed by high energy ion implantation.
  • FIG. 2 shows a sectional view through four fins 12 which are positioned adjacent, and having their elongate axes parallel, to one another.
  • the figure shows a typical layout (in simplified form) for a CMOS circuit having pMOS (p-type doped) 30 and nMOS (n-type doped) devices 40 next to one another on the same substrate 11.
  • a masking layer 50 of photoresist material is deposited and patterned to cover the nMOS device fins 12 so as to prevent p-type dopant from being implanted therein.
  • the photoresist has a finite overlay which, when comparable to the fin pitch (i.e. distance between adjacent fins), and in combination with the height of the covered fin, limits the angle at which the subsequent implant 100 can take place in order to reach the bottom of the side wall to be implanted. In other words, the fin cannot be implanted at the preferred angle of, say, 45 degrees.
  • the result is non-conformal doping with the upper region of the implanted fin receiving a significantly higher dose than the 'shadowed' lower part, leading to a non-optimal trade-off between extension resistance and short-channel effects.
  • PLAD Plasma Doping
  • VPD Vapour Phase Doping
  • SSD Solid State Diffusion
  • a method of fabricating a finFET as described in the opening paragraph, the method comprising the steps of: forming the fin by patterning a semiconductor layer; forming the gate on at least one side of a portion of the fin, said portion defining the channel; then, implanting a diffusion inhibiting species into the extension regions; then, forming spacers adjacent the gate, the spacers serving to mask said extension regions; then, forming the source and drain regions comprising dopant species; then, performing a thermal anneal to diffuse the dopant species into said extension regions.
  • the (relatively heavy dose of) implanted ions for the source and drain can be diffused into the extension regions, by 10 to 30nm for example, in a controlled manner by performing an anneal.
  • the carbon serves to slow down the diffusion of the source/drain dopant ions thus allowing the diffusion outcome to be fine-tuned by application of the desired anneal conditions.
  • the mechanism of reducing the transient-enhanced diffusion results in a steeper dopant profile and, significantly, presents a conformal doping profile throughout the height of the extension regions.
  • the gate is formed around all exposed sides of the portion of the fin corresponding to the channel.
  • the gate itself can then serve to mask the channel during the diffusion inhibiting species implant.
  • the implant is then self-aligned to the gate.
  • the invention is particularly suited to the application of a rapid thermal anneal (RTA) in which the dopant species are diffused and activated over a short period of time at a high temperature, for example within the range of 900 to 1200°C.
  • RTA rapid thermal anneal
  • the method further comprises the step of performing an implant to render at least part of the extension regions amorphous. Such an amorphising step further slows down the diffusion of the dopant ions thus providing a more controllable dopant profile within the extension region.
  • a plurality of finFETs manufactured in accordance with the invention are disposed on a substrate wherein the fin of respective finFETs have elongate axes which are parallel to one another, the fins being spaced by no more than 200nm.
  • the substrate may support a mixture of pMOS devices, having p-type doped source and drain regions, and nMOS devices having n-type doped source and drain regions, i.e. a CMOS arrangement.
  • the manufacture of such a CMOS device may involve masking the nMOS devices whilst implanting p-type dopant species in the source/drain regions of the pMOS devices, and vice-versa.
  • Figure 2 shows a highly simplified schematic sectional view of one stage of a known method of manufacturing finFETs in a CMOS process
  • Figure 3 shows a schematic plan view of a finFET manufactured in accordance with the invention
  • Figures 4a, 5a, 6a and 7a show schematic sectional views of a finFET, taken along the line A-A of Figure 3, at various stages of the method according to a first embodiment of the invention
  • Figures 4b, 5b, 6b and 7b show schematic sectional views of a finFET, taken along the line B-B of Figure 3, at various stages of the method according to a first embodiment of the invention;
  • Figure 8 shows a highly simplified schematic perspective view of two finFET devices manufactured in accordance with a second embodiment of the invention;
  • Figure 9 shows a plot of experimental results for diffusion of boron ions at various RTA temperatures in combination with an amorphising implant.
  • Figure 10 shows a plot of experimental results for diffusion of phosphorous ions at various RTA temperatures in combination with an amorphising implant.
  • Figure 3 shows a plan view of the finFET device of figure 1. It will be appreciated that figures 3 to 7 show only one device and many thousands will typically be disposed on a single wafer. For the sake of simplicity, the method will be described with reference to one device only.
  • the view shown in figure 3 is of the finFET 10 after gate patterning.
  • the method according to a first embodiment of the invention will now be described with reference to figures 4 to 7.
  • a semiconductor fin 12 is formed on a substrate 11 as shown in figures 4a and 4b.
  • the substrate may typically comprise a silicon on insulator (SOI) wafer wherein the silicon thickness typically varies between 20 to 100nm.
  • SOI silicon on insulator
  • the fin 12 is formed by patterning the silicon layer by a combination of lithography (optical or e-beam) and etch. Following the etch, thermal steps in oxygen, nitrogen or hydrogen ambient can be applied to cure the damage caused by etching, and to optimize the fin shape.
  • the final height of the fin 12 typically ranges from 20 to 100nm
  • the width of the fin 12 typically ranges from 5 to 30nm. It is envisaged that there are a number of methods in which the fin can be formed on the substrate as will be known by a person skilled in the art.
  • a gate dielectric layer 22 is thermally grown on the fin, as shown in figure 5.
  • the gate oxide can deposited.
  • a metal layer, or stack of metal layers, having a total thickness of around 100nm is deposited over the substrate as shown in figure 5.
  • the gate stack may comprise a single metal layer or, more typically, a thin metal layer (having a thickness of around 10nm) and a thicker layer of polysilicon.
  • the polysilicon may be converted to suicide using known methods.
  • the gate stack needs to be thick enough to block the deep HDD implant from the channel later in the process.
  • the gate stack is patterned using photolithography to form a gate 15 over the three exposed sides of a portion of the fin 12, the portion defining the channel 25 as shown in figure 6b.
  • the width of the gate 15 will determine the channel length.
  • the gate 15 of this described embodiment is disposed on all three exposed sides of the channel 25.
  • this provides a superior control of the conduction channel in the device.
  • this embodiment includes an 'all-round' gate
  • a dual gate arrangement may instead be adopted wherein two electrically separated gates may be disposed on separate parts of the fin 12.
  • Such an arrangement may give more flexibility to circuit designers for example.
  • the gate oxide on top of the fin is much thicker than on the sides, so that an inversion channel does not form in the top region of the fin.
  • the gate on the top surface is then removed so that the front and back gate (i.e. those disposed on the sidewalls of the fin) are electrically isolated, and the two inversion channels can be switched individually. Turning back to the all-round gate, following the formation of the gate
  • carbon ions are implanted into the exposed surface of the fin 12 as referenced at 200 in figure 6.
  • the carbon atoms will serve as a diffusion inhibiter during subsequent diffusion steps later in the process.
  • Carbon is implanted at an energy within the range of 1 to 10 keV, more typically 4 to 6keV, and at a concentration of approximately 1 e15cm "2 .
  • germanium ions are implanted at an energy of between 5 and 20keV, and at a dose in the range of 3e14 to 1 e15cm "2 , to render at least part of the extension regions 20 amorphous.
  • Substitutional carbon serves to slow down diffusion because it binds to silicon interstitials created by the amorphising implant of germanium.
  • germanium for the amorphising implant
  • silicon atoms can instead be used.
  • other species may be used in place of carbon to serve as diffusion inhibiters such as fluorine or nitrogen for example.
  • spacers 32 are formed against the side walls of the gate 15.
  • the spacers 32 are formed by depositing a silicon nitride layer for example, and performing a wet etch.
  • the spacers 32 serve to mask the extension regions 20 adjacent the channel 25 as shown in figure 7b.
  • the spacers have a width in the range of 10 to 30nm.
  • ions are implanted into the source and drain regions 16,18 from above as referenced at 100 in figure 7.
  • the dopants are n-type, such as phosphorus and/or arsenic, whereas for PMOS devices the dopants are p-type, such as boron for example. Therefore, the implant 100 serves to render the source 16 and drain 18 n-type or p-type.
  • a thermal anneal is then carried out to diffuse the dopant species into the extension regions 20.
  • the thermal anneal comprises heating the finFET to a temperature in the range of 900 to 1200 0 C. It will be appreciated that the thermal anneal conditions such as the temperature and duration determine the distance at which these dopant species diffuse into the extension regions 20 towards the channel 25.
  • the presence of carbon atoms in the extension region slows down the diffusion process so as to create a steep dopant profile between the extension region 20 and the channel 25 throughout the entire height of the fin.
  • the inhibition of diffusion also allows for greater control of the process by varying the anneal parameters.
  • Suicide contacts (not shown) to the source 16 and drain 18 are then formed in a self-aligned fashion by depositing a metal layer over the fin, performing a sequence of anneal steps, which convert part of the metal on the exposed silicon surface into suicide, and removing the un-reacted metal as is known readily in the art.
  • the metal layer may be of cobalt, nickel or platinum for example.
  • further layers are deposited and patterned for the back end processing. This may typically include depositing insulating and conducting layers over the substrate 11 and forming contacts to the finFETs (and other components) through vias which are etched in the insulating layers. This process is known to the skilled person and will not be described any further because it is not critical to the present invention.
  • FIG. 8 shows two finFET devices formed adjacent one another, one being an pMOS device 30, and the other an nMOS device 40, each sharing a common gate 15. It should be appreciated that adjacent transistors need not share a gate and is determined by the requirements of the overall circuit.
  • the invention presents particular advantages to arrangements wherein pMOS and nMOS devices are fabricated adjacent one another on a wafer. This is typical in a dense static random access memory (SRAM) for example, and where the fin pitch cannot be relaxed due to the requirement for a small cell area.
  • SRAM static random access memory
  • the elongate axes 50 of the respective finFETs 30, 40 are parallel to one another wherein the fins 12 are spaced by no more than 100nm so as to achieve a densely populated wafer.
  • the fin 12 of the nMOS device 40 is masked whilst the pMOS fin is implanted with p-type dopant species.
  • the invention allows for the omission of a dedicated extension implant and the associated non-conformal doping thereof. By exploiting the heavily doped source and drain implant which provides a more conformal doping profile, in combination with a diffusion inhibiting species implant a conformal extension doping profile can be achieved for such a CMOS arrangement.
  • the source and drain regions can be doped by providing an in-situ doped layer instead of, or as well as, implanting the dopant species after the spacer formation.
  • selective epitaxial growth is employed to grow the exposed silicon of the source and drain regions by, say, 40nm, in controlled conditions.
  • SEG can also be used in the above-described embodiment to simply increase the height and width of the exposed fin before the implant of dopant species is carried out.
  • this can lower the contact resistance between the subsequent suicide and doped silicon.
  • silicon can be replaced by alternative semiconductor materials such as silicon-germanium.
  • a method of fabricating a finFET wherein diffusion inhibiting species, e.g. carbon, ions are implanted from above into the extension regions before spacers are formed adjacent the gate and a thermal anneal is carried out to activate the source/drain dopants.
  • the anneal conditions are selected to cause the dopant ions to diffuse from the heavily doped source and drain regions into the neighbouring extension regions under the spacers, thus avoiding the need for a dedicated extension implant step and providing a conformal doping profile.
  • the diffusion inhibiting species implant, and optionally an amorphising implant to the extension regions, the rate and profile of the diffusion can be easily controlled by adjusting the anneal parameters.

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Abstract

A method of fabricating a fin field effect transistor (finFET) (10) is provided wherein diffusion inhibiting species, e.g. carbon, ions are implanted from above into the extension regions (20) before spacers are formed adjacent the gate (15) and a thermal anneal is carried out to activate the source/drain dopants. The anneal conditions are selected to cause the dopant ions to diffuse from the source and drain regions (16,18) into the neighbouring extension regions (20), thus avoiding the need for a dedicated extension implant step and providing a conformal doping profile. Furthermore, by providing the diffusion inhibiting species implant, and optionally an amorphising implant to the extension regions, the rate and profile of the diffusion can be easily controlled by adjusting the anneal parameters.

Description

DESCRIPTION
METHOD OF MANUFACTURING A FINFET
The invention relates to a method of manufacturing a fin field effect transistor, hereinafter termed a finFET, having a semiconductor fin protruding upward from a substrate, the fin comprising source and drain regions laterally disposed either side of a channel each separated therefrom by respective extension regions, and a gate disposed on at least one side of the channel and insulated therefrom by a gate dielectric layer. In particular, the invention relates to finFETs integrated in a complementary metal-oxide-semiconductor (CMOS) architecture which comprises both pMOS and nMOS transistors on the same wafer.
The consumer desire to incorporate more and more electronic functionality into small volumes places a constant demand on semiconductor technology to continually reduce the size of individual transistors and on designers to integrate more devices onto a unit area of wafer. As transistor devices get smaller, then more technical hurdles present themselves in the form of electrical side-effects caused by bringing the transistor components closer together. For example, as the channel of a field effect transistor (FET) is made progressively shorter, Short Channel Effects (SCEs) reduce the control of which the gate has on the conduction channel leading to low threshold voltages, thus increased leakage currents.
From the CMOS 32nm node onwards, conventional planar bulk MOSFETs are assumed to suffer too severely from SCEs to be considered as the primary technology architecture for CMOS circuits. Also, mainly due to drain induced barrier lowering resulting from electric field penetration through the underlying buried oxide, single gate thin-body silicon on insulator (SOI) is unlikely to provide a scalable alternative to conventional planar bulk CMOS.
Multi-gate transistors look to provide a promising alternative to the well- established single-gate MOSFET to enable further scaling down. In these, a thin semiconductor channel is controlled from more than one side giving better control over any SCEs. In principle there are three multi-gate architectures: the planar dual gate, the vertical dual gate and the finFET.
The planar dual gate transistor appears most similar to the conventional bulk MOSFET. It imposes the least changes on circuit layout level, and thus it is the preferred multi-gate architecture, especially by designers. Unfortunately, the device is technologically very difficult to fabricate; the very tight alignment requirements of top and bottom gate being the bottleneck. In the vertical dual gate, both the channel and the current flow are out of plane; this architecture is not considered on large scale due to layout issues.
Therefore, most industrial attention is at present focused on the finFET architecture. In a finFET, the current flows parallel to the carrier wafer, so that in top view a finFET is still quite similar to a planar MOSFET. However, the channels are (predominantly) vertical located in the fin which exposes two or three sides through which a gate can influence the conduction channels.
Figure 1 shows, in very simplified form, a perspective view of finFET 10 on a substrate 11. The device comprises a semiconductor fin 12 protruding upward from the substrate 11.
The fin comprises a conduction channel (not visible), current through which is controlled by the overlying 'all-round' gate 15. Either side of the channel, the fin comprises a doped source region 16 and a drain region 18 between which current flows via the channel. Directly adjacent the channel, the fin 12 comprises source and drain extension regions 20 having a lower doping level than the respective source and drain regions 16,18. Alternative terms used in the art for the extension regions 20 include field-relief regions or lightly doped drain (LDD) regions, whilst alternative terms used for the source and drain regions 16,18 include heavily doped drain (HDD).
The gate 15 is insulated from the channel by a gate dielectric layer 22. Although the gate shown in Figure 1 is disposed around all three exposed sides of the channel, it is quite possible, for example, for the device to instead comprise two separate gates, each one disposed on one of the vertical exposed sides of the channel region of the fin 12, thus leaving the top surface of the fin uncovered.
US-2005/0186742 discloses such a finFET. During the manufacture of the device, an oblique ion implantation technique is employed to implant dopant species into the exposed surfaces of the fin to form source and drain regions. This involves implanting dopant ions at an angle to ensure that the ions are implanted into both the sidewalls and the top surface of the fin, i.e. to reach a certain level of conformality.
Doping the side walls of the fin from top to bottom is particularly important in the extension regions, because those regions must form a lowly- resistive path between heavily doped source/drain regions and the inversion channels under the gate, which are predominantly vertical and extend from top to bottom.
One possible method to dope the fin all the way from top to bottom would be an ion implantation in the vertical direction, or under a small tilt angle, as is typically done in planar devices. However, to obtain homogeneous doping from top to bottom, a high-energy implant is needed in combination with a thermal step to distribute the dopants vertically by diffusion. Unfortunately, dopants also diffuse in the lateral direction, which is perfectly acceptable for the heavily doped source/drain, but excessive diffusion of dopants from the extension regions into the channel under the gate would lead to severe short-channel effects. Therefore, like in planar devices, it is not favoured for the extension regions to be formed by high energy ion implantation. In order to obtain a certain level of conformality in the extension regions with low-energy implantation, a high tilt angle between the implantation beam and the vertical direction is needed, say 45 degrees. This is feasible for isolated fins, but when other features, such as other fins, poly lines or photoresist layers, are close, the tilt angle is limited by shadowing by those features. The problem is illustrated in Figure 2 which shows a sectional view through four fins 12 which are positioned adjacent, and having their elongate axes parallel, to one another. The figure shows a typical layout (in simplified form) for a CMOS circuit having pMOS (p-type doped) 30 and nMOS (n-type doped) devices 40 next to one another on the same substrate 11.
A masking layer 50 of photoresist material is deposited and patterned to cover the nMOS device fins 12 so as to prevent p-type dopant from being implanted therein. The photoresist has a finite overlay which, when comparable to the fin pitch (i.e. distance between adjacent fins), and in combination with the height of the covered fin, limits the angle at which the subsequent implant 100 can take place in order to reach the bottom of the side wall to be implanted. In other words, the fin cannot be implanted at the preferred angle of, say, 45 degrees. The result is non-conformal doping with the upper region of the implanted fin receiving a significantly higher dose than the 'shadowed' lower part, leading to a non-optimal trade-off between extension resistance and short-channel effects.
Several methods have been reported to achieve more conformal doping, such as Plasma Doping (PLAD), Vapour Phase Doping (VPD) and Solid State Diffusion (SSD). In PLAD, rather than shooting dopant ions in a well-defined direction towards the wafer, the wafer is brought in the vicinity of a plasma. The ions in the plasma move towards the wafer (by Coulomb forces) at low kinetic energy, and because of their mutual collisions they hit the surface from dispersed directions. Often, the ion impact energy is so low that they are deposited on the fin sides rather then entering the silicon. A certain degree of conformality has been demonstrated; however PLAD results in a highly damaged surface, and suffers from a marginal process control of total 'implanted' dose. In VPD, a gas carrying the dopant atoms flows over the wafer. Dopant atoms adhere to the silicon surface after which a heat step is applied to drive them further into the silicon. Good results have been obtained for doping deep trenches, but the concentrations and implantation depth are out of the desired range for ultra-small finFETs. Finally, in SSD a sacrificial solid material containing the dopant atoms is deposited over the surface to be doped, after which a thermal step diffuses the dopant atoms into the silicon. This method results in an ill-defined surface; etching off the sacrificial layer without attacking the relatively thin fin or the underlying substrate is cumbersome. Therefore, it is an object of the invention to provide an improved method of fabricating a finFET device. It is a further object of the invention to improve the uniformity of the doping level throughout the height of a finFET in the source and drain extension regions.
According to the invention there is provided a method of fabricating a finFET as described in the opening paragraph, the method comprising the steps of: forming the fin by patterning a semiconductor layer; forming the gate on at least one side of a portion of the fin, said portion defining the channel; then, implanting a diffusion inhibiting species into the extension regions; then, forming spacers adjacent the gate, the spacers serving to mask said extension regions; then, forming the source and drain regions comprising dopant species; then, performing a thermal anneal to diffuse the dopant species into said extension regions. By implanting a diffusion inhibiting species, such as carbon, into the extension regions before the spacers are formed, the (relatively heavy dose of) implanted ions for the source and drain can be diffused into the extension regions, by 10 to 30nm for example, in a controlled manner by performing an anneal. The carbon serves to slow down the diffusion of the source/drain dopant ions thus allowing the diffusion outcome to be fine-tuned by application of the desired anneal conditions. Furthermore, the mechanism of reducing the transient-enhanced diffusion results in a steeper dopant profile and, significantly, presents a conformal doping profile throughout the height of the extension regions.
In a preferred embodiment, the gate is formed around all exposed sides of the portion of the fin corresponding to the channel. Advantageously, the gate itself can then serve to mask the channel during the diffusion inhibiting species implant. Moreover, the implant is then self-aligned to the gate. The invention is particularly suited to the application of a rapid thermal anneal (RTA) in which the dopant species are diffused and activated over a short period of time at a high temperature, for example within the range of 900 to 1200°C. Preferably the method further comprises the step of performing an implant to render at least part of the extension regions amorphous. Such an amorphising step further slows down the diffusion of the dopant ions thus providing a more controllable dopant profile within the extension region.
In another preferred embodiment, a plurality of finFETs manufactured in accordance with the invention are disposed on a substrate wherein the fin of respective finFETs have elongate axes which are parallel to one another, the fins being spaced by no more than 200nm. The substrate may support a mixture of pMOS devices, having p-type doped source and drain regions, and nMOS devices having n-type doped source and drain regions, i.e. a CMOS arrangement. The manufacture of such a CMOS device may involve masking the nMOS devices whilst implanting p-type dopant species in the source/drain regions of the pMOS devices, and vice-versa.
Embodiments of the invention will now be described, by way of example only, with reference to the following drawings in which Figure 1 shows a highly simplified schematic perspective view of a finFET device;
Figure 2 shows a highly simplified schematic sectional view of one stage of a known method of manufacturing finFETs in a CMOS process;
Figure 3 shows a schematic plan view of a finFET manufactured in accordance with the invention;
Figures 4a, 5a, 6a and 7a show schematic sectional views of a finFET, taken along the line A-A of Figure 3, at various stages of the method according to a first embodiment of the invention;
Figures 4b, 5b, 6b and 7b show schematic sectional views of a finFET, taken along the line B-B of Figure 3, at various stages of the method according to a first embodiment of the invention; Figure 8 shows a highly simplified schematic perspective view of two finFET devices manufactured in accordance with a second embodiment of the invention;
Figure 9 shows a plot of experimental results for diffusion of boron ions at various RTA temperatures in combination with an amorphising implant; and,
Figure 10 shows a plot of experimental results for diffusion of phosphorous ions at various RTA temperatures in combination with an amorphising implant.
It will be appreciated that the Figures are merely schematic. The same reference numerals are used throughout the Figures to denote the same or similar parts.
Figure 3 shows a plan view of the finFET device of figure 1. It will be appreciated that figures 3 to 7 show only one device and many thousands will typically be disposed on a single wafer. For the sake of simplicity, the method will be described with reference to one device only. The view shown in figure 3 is of the finFET 10 after gate patterning. The method according to a first embodiment of the invention will now be described with reference to figures 4 to 7. In a first step a semiconductor fin 12 is formed on a substrate 11 as shown in figures 4a and 4b. The substrate may typically comprise a silicon on insulator (SOI) wafer wherein the silicon thickness typically varies between 20 to 100nm. Although this embodiment is described with reference to a SOI wafer it is envisaged that bulk wafers can also be adopted to form the finFET device 10 thereon.
The fin 12 is formed by patterning the silicon layer by a combination of lithography (optical or e-beam) and etch. Following the etch, thermal steps in oxygen, nitrogen or hydrogen ambient can be applied to cure the damage caused by etching, and to optimize the fin shape. The final height of the fin 12 typically ranges from 20 to 100nm The width of the fin 12 typically ranges from 5 to 30nm. It is envisaged that there are a number of methods in which the fin can be formed on the substrate as will be known by a person skilled in the art.
Following the patterning of the fin 12, a gate dielectric layer 22 is thermally grown on the fin, as shown in figure 5. Alternatively, particularly in the case of high-k dielectrics such as HfOx, the gate oxide can deposited.
Following the deposition of the gate dielectric layer 22, a metal layer, or stack of metal layers, having a total thickness of around 100nm is deposited over the substrate as shown in figure 5. The gate stack may comprise a single metal layer or, more typically, a thin metal layer (having a thickness of around 10nm) and a thicker layer of polysilicon. At some stage in the fabrication process, the polysilicon may be converted to suicide using known methods. The gate stack needs to be thick enough to block the deep HDD implant from the channel later in the process.
The gate stack is patterned using photolithography to form a gate 15 over the three exposed sides of a portion of the fin 12, the portion defining the channel 25 as shown in figure 6b.
It will be appreciated that the width of the gate 15 will determine the channel length. The gate 15 of this described embodiment is disposed on all three exposed sides of the channel 25. Advantageously, this provides a superior control of the conduction channel in the device.
Although this embodiment includes an 'all-round' gate, it is envisaged that a dual gate arrangement may instead be adopted wherein two electrically separated gates may be disposed on separate parts of the fin 12. Such an arrangement may give more flexibility to circuit designers for example. In the fabrication thereof (not shown), the gate oxide on top of the fin is much thicker than on the sides, so that an inversion channel does not form in the top region of the fin. The gate on the top surface is then removed so that the front and back gate (i.e. those disposed on the sidewalls of the fin) are electrically isolated, and the two inversion channels can be switched individually. Turning back to the all-round gate, following the formation of the gate
15, carbon ions are implanted into the exposed surface of the fin 12 as referenced at 200 in figure 6. The carbon atoms will serve as a diffusion inhibiter during subsequent diffusion steps later in the process. Carbon is implanted at an energy within the range of 1 to 10 keV, more typically 4 to 6keV, and at a concentration of approximately 1 e15cm"2. Furthermore, germanium ions are implanted at an energy of between 5 and 20keV, and at a dose in the range of 3e14 to 1 e15cm"2, to render at least part of the extension regions 20 amorphous. Substitutional carbon serves to slow down diffusion because it binds to silicon interstitials created by the amorphising implant of germanium.
Although the described embodiment employs germanium for the amorphising implant, it is envisaged that silicon atoms can instead be used. Furthermore, other species may be used in place of carbon to serve as diffusion inhibiters such as fluorine or nitrogen for example.
Following the implant of carbon and germanium, spacers 32 are formed against the side walls of the gate 15. The spacers 32 are formed by depositing a silicon nitride layer for example, and performing a wet etch. The spacers 32 serve to mask the extension regions 20 adjacent the channel 25 as shown in figure 7b. The spacers have a width in the range of 10 to 30nm.
It should be noted at this stage that no dedicated extension implant has been carried out as per conventional processing. Once the spacers 32 are in place, ions are implanted into the source and drain regions 16,18 from above as referenced at 100 in figure 7. For an NMOS device the dopants are n-type, such as phosphorus and/or arsenic, whereas for PMOS devices the dopants are p-type, such as boron for example. Therefore, the implant 100 serves to render the source 16 and drain 18 n-type or p-type. A thermal anneal is then carried out to diffuse the dopant species into the extension regions 20. The thermal anneal comprises heating the finFET to a temperature in the range of 900 to 12000C. It will be appreciated that the thermal anneal conditions such as the temperature and duration determine the distance at which these dopant species diffuse into the extension regions 20 towards the channel 25.
The presence of carbon atoms in the extension region slows down the diffusion process so as to create a steep dopant profile between the extension region 20 and the channel 25 throughout the entire height of the fin. The inhibition of diffusion also allows for greater control of the process by varying the anneal parameters.
Suicide contacts (not shown) to the source 16 and drain 18 are then formed in a self-aligned fashion by depositing a metal layer over the fin, performing a sequence of anneal steps, which convert part of the metal on the exposed silicon surface into suicide, and removing the un-reacted metal as is known readily in the art. The metal layer may be of cobalt, nickel or platinum for example. Subsequently further layers are deposited and patterned for the back end processing. This may typically include depositing insulating and conducting layers over the substrate 11 and forming contacts to the finFETs (and other components) through vias which are etched in the insulating layers. This process is known to the skilled person and will not be described any further because it is not critical to the present invention.
As has been mentioned above, in a typical CMOS process flow many thousands of individual finFET devices 10 will be fabricated on the same substrate 11. By way of example only, Figure 8 shows two finFET devices formed adjacent one another, one being an pMOS device 30, and the other an nMOS device 40, each sharing a common gate 15. It should be appreciated that adjacent transistors need not share a gate and is determined by the requirements of the overall circuit. The invention presents particular advantages to arrangements wherein pMOS and nMOS devices are fabricated adjacent one another on a wafer. This is typical in a dense static random access memory (SRAM) for example, and where the fin pitch cannot be relaxed due to the requirement for a small cell area. In a common arrangement the elongate axes 50 of the respective finFETs 30, 40 are parallel to one another wherein the fins 12 are spaced by no more than 100nm so as to achieve a densely populated wafer. As has already been described with reference to figure 2 in the introduction, the fin 12 of the nMOS device 40 is masked whilst the pMOS fin is implanted with p-type dopant species. The invention allows for the omission of a dedicated extension implant and the associated non-conformal doping thereof. By exploiting the heavily doped source and drain implant which provides a more conformal doping profile, in combination with a diffusion inhibiting species implant a conformal extension doping profile can be achieved for such a CMOS arrangement.
Experimental results for the diffusion of boron (figure 9) and phosphorus (figure 10) demonstrate that a carbon co-implantation together with a pre- amorphization implant provides for a sharper doping profile having the depth of diffusion dependant strongly on the anneal conditions in a tuneable fashion. In an alternative embodiment to that described above, the source and drain regions can be doped by providing an in-situ doped layer instead of, or as well as, implanting the dopant species after the spacer formation. In this case selective epitaxial growth (SEG) is employed to grow the exposed silicon of the source and drain regions by, say, 40nm, in controlled conditions. SEG can also be used in the above-described embodiment to simply increase the height and width of the exposed fin before the implant of dopant species is carried out. Advantageously, this can lower the contact resistance between the subsequent suicide and doped silicon.
It will be appreciated by the skilled person that silicon can be replaced by alternative semiconductor materials such as silicon-germanium.
In summary, there is provided a method of fabricating a finFET wherein diffusion inhibiting species, e.g. carbon, ions are implanted from above into the extension regions before spacers are formed adjacent the gate and a thermal anneal is carried out to activate the source/drain dopants. The anneal conditions are selected to cause the dopant ions to diffuse from the heavily doped source and drain regions into the neighbouring extension regions under the spacers, thus avoiding the need for a dedicated extension implant step and providing a conformal doping profile. Furthermore, by providing the diffusion inhibiting species implant, and optionally an amorphising implant to the extension regions, the rate and profile of the diffusion can be easily controlled by adjusting the anneal parameters. From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the design, manufacture and use of semiconductors and which may be used in addition to or instead of features described herein.
Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of disclosure also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to any such features and/or combinations of such features during the prosecution of the present application or of any further applications derived therefrom.

Claims

1. A method of fabricating a fin field effect transistor, hereinafter termed a finFET, having a semiconductor fin protruding upward from a substrate, the fin comprising source and drain regions laterally disposed either side of a channel each separated therefrom by respective extension regions, and a gate disposed on at least one side of the channel and insulated therefrom by a gate dielectric layer, the method comprising the steps of:
- forming the fin by patterning a semiconductor layer; - forming the gate on at least one side of a portion of the fin, said portion defining the channel; then,
- implanting a diffusion inhibiting species into the extension regions; then,
- forming spacers adjacent the gate, the spacers serving to mask said extension regions; then,
- forming the source and drain regions comprising dopant species; then,
- performing a thermal anneal to diffuse the dopant species into said extension regions.
2. A method according Claim 1 , wherein the gate is formed around all exposed sides of said portion of the fin.
3. A method according to Claims 1 or 2, wherein the diffusion inhibiting species comprises carbon.
4. A method according to Claims 1 , 2 or 3, wherein said dopant species diffuse into said extension regions by 10 to 30nm.
5. A method according to any preceding claim, wherein said thermal anneal comprises heating the finFET to a temperature in the range of 900 to
1200°C.
6. A method according to any preceding claim further comprising the step of:
- performing an implant to render at least part of the extension regions amorphous.
7. A method of fabricating a plurality of finFETs fabricated in accordance with any preceding claim, wherein the fin of respective finFETs have elongate axes which are parallel to one another, the fins being spaced by no more than 200nm.
8. A method according to Claim 7, wherein the dopant species is n-type in a first finFET and p-type in a second finFET which is adjacent said first finFET.
9. A method according to Claim 8, wherein the fin of said second finFET is covered by a mask whilst said dopant species are implanted into the source and drain of said first finFET.
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