CN102543747A - Manufacturing method of MOS (Metal Oxide Semiconductor) transistor - Google Patents
Manufacturing method of MOS (Metal Oxide Semiconductor) transistor Download PDFInfo
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- CN102543747A CN102543747A CN2010106204644A CN201010620464A CN102543747A CN 102543747 A CN102543747 A CN 102543747A CN 2010106204644 A CN2010106204644 A CN 2010106204644A CN 201010620464 A CN201010620464 A CN 201010620464A CN 102543747 A CN102543747 A CN 102543747A
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Abstract
The invention discloses a manufacturing method of an MOS (Metal Oxide Semiconductor) transistor. The method comprises the following steps of: providing a semiconductor substrate and forming a grid structure on the semiconductor substrate; performing first ion injection on the semiconductor substrate on both sides of the grid structure by adopting at least one first impurity to form a first doping region, wherein the concentration distribution curve of the first impurity in the first doping region is provided with a first peak value; performing second ion injection on the semiconductor substrate on both sides of the grid structure by adopting a second impurity to form a second doping region, wherein the concentration distribution curve of the second impurity in the second doping region is provided with a second peak value, and the second peak value is positioned below the first peak value; forming a side wall encircling the side wall of the grid structure; and forming a source/drain region. According to an MOS tube formed by using the MOS tube manufacturing method, a transient enhanced diffusion effect is reduced while a hot carrier effect is weakened, and the electric performance of the MOS tube is optimized.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of manufacturing approach of MOS transistor.
Background technology
Along with integrated circuit develops to very lagre scale integrated circuit (VLSIC), the current densities of IC interior is increasing, and the number of elements that is comprised is also more and more.Along with further developing of semiconductor integrated circuit, the size of semiconductor element also reduces thereupon, and MOS transistor basic structure comprises three main region: source electrode (source), drain electrode (drain) and gate electrode (gate).Wherein source electrode and drain electrode according to the type of device difference, can be divided into n type doping (NMOS) and p type doping (PMOS) through highly doped formation.
In the scaled process of device; Drain voltage does not reduce thereupon; This just causes the increase of the raceway groove electric field between source/drain electrode, and under the highfield effect, electronics can accelerate to the speed than much higher times of heat movement speed between twice collision; Thereby cause thermoelectronic effect (Hot Carrier Issue, HCI).Said HCI effect can cause that hot electron injects to gate dielectric layer, forms gate electrode electric current and substrate current, influences the reliability of device and circuit, even causes the puncture of device to burn.
In order to overcome said HCI, prior art has developed multiple to the improving one's methods of mos transistor structure, and for example two injecting structure, buried channel structure, discrete grid structures, buries drain structure etc.; Wherein study morely and practical value is bigger a kind of be lightly doped drain (lightly doped drain, LDD) structure.The effect of LDD structure is to reduce the channel region electric field, and then can significantly improve thermoelectronic effect.
Referring to figs. 1 to Fig. 4, show the sketch map that prior art comprises metal-oxide-semiconductor manufacturing approach one embodiment of LDD structure.With reference to figure 1, on Semiconductor substrate 100, form gate dielectric layer 110 and grid 120 successively; With reference to figure 2, lightly doped LDD is carried out in source region 130 and drain region 140 inject, and the injection ion is spread in said Semiconductor substrate 100 through annealing process; As shown in Figure 3, form side wall 150 in said grid 120 both sides; As shown in Figure 4, carry out heavily doped source/drain electrode and inject, form heavily doped region 170,180, because the barrier effect of said side wall 150, the lightly doped region that forms when the zone of said side wall 150 belows is still injected for LDD constitutes LDD structure 130a and 140a.
Yet,, also have some shortcomings though the LDD structure has significant effect to reducing thermoelectronic effect.
How to optimize the LDD structure, when making said LDD structure effectively improve the HCI effect, avoid the performance decrease of other electricity of metal-oxide-semiconductor, become those skilled in the art's problem demanding prompt solution.The improvement technical scheme of more LDD structure please refer to the U.S. Patent application etc. that publication number is US20040150014A1.
Summary of the invention
The problem that the present invention solves provides a kind of manufacturing approach of metal-oxide-semiconductor, to optimize the electrology characteristic of formed metal-oxide-semiconductor.
For addressing the above problem, the present invention provides a kind of manufacturing approach of metal-oxide-semiconductor, comprising:
Semiconductor substrate is provided, on Semiconductor substrate, forms grid structure;
Adopt at least a first impurity that the Semiconductor substrate of said grid structure both sides is carried out first ion and inject, form first doped region, the concentration profile of first impurity has first peak value in said first doped region;
Adopting second impurity that the Semiconductor substrate of said grid structure both sides is carried out second ion injects; Form second doped region; The concentration profile of second impurity has second peak value in said second doped region, and said second peak value is positioned at the below of said first peak value;
Form the side wall that surrounds said grid structure sidewall;
Formation source/drain region.
Compared with prior art, the present invention has the following advantages: the metal-oxide-semiconductor that metal-oxide-semiconductor manufacturing approach of the present invention forms has also reduced the transient enhanced diffusion effect when weakening hot carrier's effect, optimized the electric property of metal-oxide-semiconductor.
Description of drawings
Fig. 1 to Fig. 4 shows the sketch map of prior art LDD structure making process one embodiment;
Fig. 5 shows the sketch map of metal-oxide-semiconductor manufacturing approach first execution mode of the present invention;
Fig. 6 to Figure 10 shows the sketch map of metal-oxide-semiconductor manufacturing approach first embodiment of the present invention;
Figure 11 illustrates the curve chart that metal-oxide-semiconductor manufacturing approach intermediate ion of the present invention injects angle of inclination and raceway groove electric field;
Figure 12 shows the sketch map of metal-oxide-semiconductor manufacturing approach second execution mode of the present invention;
Figure 13 to Figure 14 shows the sketch map of metal-oxide-semiconductor manufacturing approach second embodiment of the present invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
The present invention provides a kind of manufacturing approach of metal-oxide-semiconductor.With reference to figure 5, show the schematic flow sheet of metal-oxide-semiconductor manufacturing approach first execution mode of the present invention, the manufacturing approach of said metal-oxide-semiconductor may further comprise the steps:
Step S1 provides Semiconductor substrate, on Semiconductor substrate, forms grid structure;
Step S2 adopts at least a first impurity that the Semiconductor substrate of said grid structure both sides is carried out first ion and injects, and forms first doped region, and the concentration profile of first impurity has first peak value in said first doped region;
Step S3; Adopting second impurity that the Semiconductor substrate of said grid structure both sides is carried out second ion injects; Form second doped region, the concentration profile of second impurity has second peak value in said second doped region, and said second peak value is positioned at the below of said first peak value;
Step S4 forms the side wall that surrounds said grid structure sidewall;
Step S5, formation source/drain region.
Below in conjunction with specific embodiment and accompanying drawing, further describe the technical scheme of metal-oxide-semiconductor manufacturing approach of the present invention.To Figure 10, show the side schematic view of metal-oxide-semiconductor one embodiment of metal-oxide-semiconductor manufacturing approach formation of the present invention with reference to figure 6, present embodiment is an example with the NMOS pipe.
Execution in step S1 with reference to figure 6, provides Semiconductor substrate 200, is formed with isolation structure 201 in the said Semiconductor substrate 200, and the zone between the said isolation structure 201 is an active area.Be formed with gate dielectric layer 202 and grid 203 on the said Semiconductor substrate 200 successively, said gate dielectric layer 202 constitutes grid structure with grid 203.
Wherein, said Semiconductor substrate 200 can be silicon (Si) or silicon-on-insulator (SOI).Said isolation structure 201 can leave (STI) structure or selective oxidation silicon (LOCOS) isolation structure for shallow trench isolation.
Said gate dielectric layer 202 can be silica (SiO
2) or silicon oxynitride (SiNO).At the following process node of 65nm, the characteristic size of grid is very little, gate dielectric layer 202 preferred high-k (high K) materials.Said hafnium comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.The formation technology of gate dielectric layer 202 can adopt any prior art well known to those skilled in the art; Comparative optimization be chemical vapour deposition technique, the thickness of gate dielectric 202 be 15～60
Said grid 203 can be the sandwich construction that comprises semi-conducting material, for example silicon, germanium, metal or its combination.The formation technology of said grid 203 can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, for example low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technology.The thickness of grid 203 is 800 to 3000 dusts.
Execution in step S2 with reference to figure 7, adopts at least a first impurity that the Semiconductor substrate 200 of said grid structure both sides is carried out first ion and injects, and forms first doped region 204.
For the step that ion injects, inventor of the present invention has simulated the curve chart (shown in figure 11) of tilted ion implantation angle of the present invention and raceway groove electric field.Among Figure 11, E represents the raceway groove electric field, and D is the distance of channel direction, and α represents the tilted ion implantation angle, and said tilted ion implantation angle is the direction of beam line (ion beam) and the angle of wafer normal direction.Shown in figure 11, for the same position D1 of raceway groove, α is 0 when spending, and the raceway groove electric field is E1; α is 15 when spending, and the raceway groove electric field is E2; α is 30 when spending, and the raceway groove electric field is E3, and α is 45 when spending, and the raceway groove electric field is E4, and wherein E1＞E4＞E3＞E2 that is to say that the mode of selecting for use the angle of inclination to inject can reduce the raceway groove electric field.The mode of injecting at angle of inclination of the present invention, the angle of inclination that ion injects are in the scope of 15～45 degree, and preferably, the angle of inclination that said ion injects is in the scope of 20～25 degree.
The inventor finds in second doped region that makes follow-up formation; Second peak value of second impurities concentration distribution is positioned at the below of first peak value of first impurities concentration distribution; The atomic number of said first impurity needs the atomic number greater than said second impurity; That is to say the atomic mass of the atomic mass of first impurity greater than second impurity; Thereby when carrying out the ion injection, said second impurity can form darker doped region, realizes that the concentration profile peak value of second impurity is positioned at the concentration profile peak value below of first impurity.
In the present embodiment; Said first impurity adopts heavier V group element antimony of atomic mass (Sb) and arsenic (As); Carry out first ion through Sb and As and inject, form first doped region 204, particularly; The condition that said first ion injects is: the injection energy of Sb is in the scope of 5KeV～30KeV, and implantation dosage is at 5E14～3E15/cm
2Scope in, the angle of inclination is in 15～38 ° the scope; The injection energy of As is in the scope of 2KeV～10KeV, and implantation dosage is at 5E14～3E15/cm
2Scope in, the angle of inclination is in 15～38 ° the scope.
Need to prove that the present invention does not limit Sb and As carries out the sequencing that ion injects.
Fig. 7 has also shown first doped region 204 that Sb and As form; Impurities concentration distribution curve L in said first doped region 204; Said concentration profile has the first peak value X1; Because adopt the ion injection mode at angle of inclination, the said first peak value X1 is positioned at the below of gate dielectric layer 202, and has first distance Y 1 with said gate dielectric layer 202.
Need to prove that in other embodiments, said first impurity can also only select Sb element or As to carry out the injection of first ion.Perhaps; The atomic number that can also select other is the V group element of big (atomic mass is heavier); For example bismuth (Bi) carries out the injection of first ion, perhaps adopts Bi element and/or As to carry out first ion and injects, wherein; The injection energy of said bismuth ion is in the scope of 5KeV/～30KeV, and implantation dosage is at 5E14～3E15/cm
2Scope in, the angle of inclination is in 15～38 ° the scope.
Before carrying out the ion injection, need utilize mask (mask), carry out photoetching process, on Semiconductor substrate 200, form the photoresist of patterning, said photoresist exposed portions serve Semiconductor substrate; Be mask with said photoresist then, the Semiconductor substrate of exposing carried out first ion inject, form first doped region 204, similar with prior art, no longer detail.
Step S3 adopts second impurity that the Semiconductor substrate 200 of said grid structure both sides is carried out second ion and injects, and forms second doped region 205, and said subsequently first doped region 204 and second doped region 205 can form the LDD structure.
The mode that said second ion implantation process adopts the angle of inclination to inject equally, particularly, the angle of inclination that said ion injects is in the scope of 15～45 degree.Preferably, the angle of inclination of said ion injection is in the scope of 20～25 degree.
Said second ion injects the regional identical of formed second doped region 205 and said first doped region 204, and preferably, said second doped region 205 surrounds said first doped region 204.
In the present embodiment, said second impurity is phosphorus (P), and the condition that adopts P to carry out the injection of second ion is: the energy that ion injects is in the scope of 2～15Kev, and implantation dosage is from 1E12～1E14/cm
2Scope in, the angle of inclination of injection 15～38 the degree scope in.
Also show the concentration profile M (shown in the dotted line) of the second impurity P among Fig. 8; The peak value X2 of the concentration profile M of the said second impurity P is second distance Y2 apart from the distance of substrate surface; Said second distance Y2 that is to say that greater than said first distance Y 1 position of the said second peak value X2 is positioned at the below of the said first peak value X1.
Because the second peak value X2 is positioned at first peak value X1 below; So for the LDD structure that has first doped region 204 and second doped region 205 to form subsequently; The peak value of impurity concentration is between Y1 and Y2 in the LDD structure; That is to say that the peak value of the impurity concentration of the LDD structure that the present invention forms is positioned at the peak value below of first doped region, 204 first impurity concentrations; This makes the distance of raceway groove electric field distance gate dielectric far away, can avoid the injection of hot electron to gate dielectric layer, and then avoids forming grid current and substrate current;
Meanwhile, compare with second doped region 205, source/ohmic leakage that LDD structure of the present invention forms is bigger, can further reduce raceway groove electric field strength, weakens the HCI effect.
Execution in step S4; With reference to figure 9; Form the silicon nitride layer (figure does not show) that conformal covers said grid 203, gate dielectric layer 202, remove through etching and be positioned at Semiconductor substrate 200 bottoms, grid 203 lip-deep silicon nitride layers, form the side wall 223 that surrounds said grid 203 and gate dielectric layer 202.The technology of said formation side wall is identical with prior art, repeats no more at this.
Execution in step S5; With reference to Figure 10; The substrate that side wall 223 is exposed carries out heavy doping; Formation source/drain region 220, the zone of side wall 223 belows are first doped region 204 and second doped region 205 that forms among step S3 and the step S4, and first doped region 204 and second doped region 205 that are positioned at the side wall below constitute the LDD structure.
The metal-oxide-semiconductor with LDD structure that the present invention forms has good electrology characteristic, and the inventor finds that through simulation the present invention can make substrate current reduce to have reduced junction leakage more than 30%.
In the prior art, also developed bag shape (pocket) ion implantation technique, yet; Has bag metal-oxide-semiconductor of shape injection region; Its transient enhanced diffusion effect (Transistent Enhanced Diffusion, TED) stronger, said transient enhanced diffusion effect has not only caused transistorized short-channel effect (ShortChannel effect; SCE) and anti-short-channel effect (Reverse Short Channel Effect, RSCE).To the metal-oxide-semiconductor that forms marsupial shape injection region, inventor of the present invention has carried out further optimization and improvement to its technical scheme, to address the above problem.
With reference to Figure 12, show the sketch map of metal-oxide-semiconductor manufacturing approach second execution mode of the present invention, said metal-oxide-semiconductor manufacturing approach may further comprise the steps:
Step S11 provides Semiconductor substrate, on Semiconductor substrate, forms grid structure;
Step S12 adopts at least a first impurity that the Semiconductor substrate of said grid structure both sides is carried out first ion and injects, and forms first doped region, and the concentration profile of first impurity has first peak value in said first doped region;
Step S13; Adopting second impurity that the Semiconductor substrate of said grid structure both sides is carried out second ion injects; Form second doped region, the concentration profile of second impurity has second peak value in said second doped region, and said second peak value is positioned at the below of said first peak value;
Step S14 forms the defective adsorption zone that surrounds said first doped region and second doped region;
Step S15 forms the bag shape injection region that surrounds said first doped region and second doped region;
Step S16 forms the side wall that surrounds said grid structure sidewall;
Step S17, formation source/drain region.
This execution mode repeats no more with the something in common of first execution mode, step S14 is done further describing below in conjunction with accompanying drawing to step S17.
With reference to figures 13 to Figure 14, the sketch map of metal-oxide-semiconductor second embodiment of metal-oxide-semiconductor manufacturing approach formation of the present invention is shown.
Shown in figure 13; In Semiconductor substrate 300, form isolation structure 301, formed the gate dielectric layer 302 and grid 303 that are positioned on the Semiconductor substrate 300, formed first doped region 304 and second doped region 305; Execution in step 14 subsequently; As shown in Figure 3, form the defective adsorption zone 306 that surrounds first doped region 304 and second doped region 305
In the present embodiment; Inject the said defective adsorption zone 306 of formation through the angle of inclination ion, particularly, the Semiconductor substrate 300 of said grid structure both sides is carried out injection of carbon (C) ion or the injection of fluorine (F) ion; Form defective adsorption zone 306; The condition that said angle of inclination ion injects is, ion implantation energy is in the scope of 2～15Kev, and ion implantation dosage is at 5E12～8E14/cm
2Scope in, the angle of inclination 2～35 the degree scope in.
Carbon ion in the said defective adsorption zone 306 or fluorine ion can be with the defective absorption that forms in the Semiconductor substrate 300; Form group bunch with defective; Thereby defective is pricked surely around carbon ion or fluorine ion; Reduced the number of free defective like this, avoided the dopant ion diffusion of defective, reduced the transient enhanced diffusion effect in follow-up bag shape injection region.
Simultaneously, because defective and carbon ion or fluorine ion form group bunch, make the Semiconductor substrate of part of the group of formation bunch form irregular lattice arrangement; Defective can't be destroyed the atom of Semiconductor substrate 300 and arrange; The rule more thereby the feasible atom of Semiconductor substrate is on the whole arranged, lattice is more orderly, and this reduces bag scattering that the dopant ion of shape injection region receives; Thereby the diffusivity of said dopant ion reduces, and has further reduced the transient enhanced diffusion effect.
Preferably, said defective adsorption zone 306 is identical with the position of the bag shape injection region of follow-up formation, and perhaps defective adsorption zone 306 surrounds the bag shape injection region of follow-up formation, so that carry out defective absorption better.
Execution in step S16 with reference to Figure 14, after forming defective adsorption zone 306, forms before the side wall, injects through the bag shape, forms the bag shape injection region 307 that surrounds said first doped region and second doped region; The angle of inclination that general said bag shape injects is 15～35 degree, and in the present embodiment, said defective adsorption zone 306 surrounds said bag shape injection region 307.
The metal-oxide-semiconductor that metal-oxide-semiconductor manufacturing approach of the present invention forms has also reduced the transient enhanced diffusion effect when weakening hot carrier's effect, optimized the performance of metal-oxide-semiconductor.
In the foregoing description, be example with the NMOS pipe, but the present invention being not restricted to this, can also be the PMOS pipe, and those skilled in the art can also be out of shape, replace and revise according to the description of the foregoing description and execution mode accordingly.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (14)
1. the manufacturing approach of a metal-oxide-semiconductor is characterized in that, comprising:
Semiconductor substrate is provided, on Semiconductor substrate, forms grid structure;
Adopt at least a first impurity that the Semiconductor substrate of said grid structure both sides is carried out first ion and inject, form first doped region, the concentration profile of first impurity has first peak value in said first doped region;
Adopting second impurity that the Semiconductor substrate of said grid structure both sides is carried out second ion injects; Form second doped region; The concentration profile of second impurity has second peak value in said second doped region, and said second peak value is positioned at the below of said first peak value;
Form the side wall that surrounds said grid structure sidewall;
Formation source/drain region.
2. manufacturing approach as claimed in claim 1 is characterized in that the atomic number of said second impurity is less than the atomic number of said first impurity.
3. manufacturing approach as claimed in claim 2 is characterized in that, said metal-oxide-semiconductor is the NMOS pipe.
4. manufacturing approach as claimed in claim 3 is characterized in that, the step of said formation first doped region comprises that carrying out first ion through antimony ion and/or arsenic ion injects.
5. manufacturing approach as claimed in claim 3 is characterized in that, the step of said formation first doped region comprises that carrying out first ion through bismuth ion and/or arsenic ion injects.
6. like claim 4 or 5 described manufacturing approaches, it is characterized in that, carry out second ion through phosphonium ion and inject.
7. manufacturing approach as claimed in claim 4 is characterized in that, the injection energy of said antimony ion is in the scope of 5KeV～30KeV, and implantation dosage is at 5E14～3E15/cm
2Scope in, the angle of inclination is in 15～38 ° the scope.
8. like claim 4 or 5 described manufacturing approaches, it is characterized in that the injection energy of arsenic ion is in the scope of 2KeV～10KeV, implantation dosage is at 5E14～3E15/cm
2Scope in, the angle of inclination is in 15～38 ° the scope.
9. manufacturing approach as claimed in claim 6 is characterized in that, the step that adopts phosphonium ion to carry out the injection of second ion comprises: the injection energy of said phosphonium ion is in the scope of 2KeV～5KeV, and implantation dosage is at 1E12/cm
2～1E14/cm
2Scope in, the angle of inclination is in 15～38 ° the scope.
10. manufacturing approach as claimed in claim 5 is characterized in that, the injection energy of said bismuth ion is in the scope of 5KeV～30KeV, and implantation dosage is at 5E14/cm
2～3E15/cm
2Scope in, the angle of inclination is in 15～38 ° the scope.
11. manufacturing approach as claimed in claim 1 is characterized in that, also is included in formation second doped region and forms before the side wall afterwards, forms the defective adsorption zone that surrounds said first doped region and second doped region; After forming the defective adsorption zone, form before the side wall, form the bag shape injection region that surrounds said first doped region and second doped region.
12. manufacturing approach as claimed in claim 11 is characterized in that, said defective adsorption zone surrounds said bag shape injection region with the regional identical or said defective adsorption zone of bag shape injection region.
13. manufacturing approach as claimed in claim 11 is characterized in that, said metal-oxide-semiconductor is the NMOS pipe, carries out ion through carbon ion or fluorine ion and injects formation defective adsorption zone.
14. manufacturing approach as claimed in claim 13 is characterized in that, the ion implantation step of said carbon ion or fluorine ion comprises: the injection energy of carbon ion or fluorine ion is in the scope of 2KeV～15KeV, and implantation dosage is at 5E12～8E14/cm
2Scope in, the angle of inclination is in 2～35 ° the scope.
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| JP2001250945A (en) * | 2000-03-08 | 2001-09-14 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| CN1731588A (en) * | 2004-08-04 | 2006-02-08 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
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| JP2001250945A (en) * | 2000-03-08 | 2001-09-14 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| CN1731588A (en) * | 2004-08-04 | 2006-02-08 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
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