KR20030054854A - Method for Fabricating of Semiconductor Device - Google Patents
Method for Fabricating of Semiconductor Device Download PDFInfo
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- KR20030054854A KR20030054854A KR1020010085285A KR20010085285A KR20030054854A KR 20030054854 A KR20030054854 A KR 20030054854A KR 1020010085285 A KR1020010085285 A KR 1020010085285A KR 20010085285 A KR20010085285 A KR 20010085285A KR 20030054854 A KR20030054854 A KR 20030054854A
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- polysilicon film
- ions
- semiconductor device
- polysilicon layer
- manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims abstract description 39
- -1 nitrogen ions Chemical class 0.000 claims abstract description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000002245 particle Substances 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 230000005465 channeling Effects 0.000 abstract description 8
- 238000000137 annealing Methods 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자에 관한 것으로 특히, 게이트 채널링(Gate Channeling)을 방지하기 위한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a semiconductor device for preventing gate channeling.
이하, 첨부된 도면을 참조하여 종래 기술에 따른 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 제조공정 단면도이다.1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the prior art.
우선, 도 1a에 도시된 바와 같이, 소자분리 영역(12)이 형성되고 엔모스(NMOS) 영역 및 피모스(PMOS) 영역이 정의된 반도체 기판(11)상에 게이트 산화막(13)을 형성하고, 상기 게이트 산화막(13)상에 미세한 주상형(Columnar) 구조의 폴리 실리콘막(14)을 형성한다.First, as shown in FIG. 1A, a gate oxide layer 13 is formed on a semiconductor substrate 11 on which a device isolation region 12 is formed and an NMOS region and a PMOS region are defined. The polysilicon layer 14 having a fine columnar structure is formed on the gate oxide layer 13.
이어, 도 1b에 도시된 바와 같이, 상기 폴리 실리콘막(14)상에 포토레지스트(15)를 도포하고 노광 및 현상 공정으로 엔모스(NMOS) 영역에 형성된 폴리 실리콘막(14)이 노출되도록 상기 포토레지스트(15)를 패터닝한다.Subsequently, as shown in FIG. 1B, the photoresist 15 is coated on the polysilicon layer 14, and the polysilicon layer 14 formed in the NMOS region is exposed through an exposure and development process. The photoresist 15 is patterned.
이어, 상기 패터닝된 포토레지스트(15)를 마스크로 인(P) 이온을 주입하여 상기 폴리 실리콘막(14)의 상부 800∼1000Å을 비정질화시킨다.Subsequently, phosphorus (P) ions are implanted using the patterned photoresist 15 as a mask to amorphousize the upper portion of the polysilicon layer 14 to 800 to 1000 Å.
이어, 후속 열처리 공정을 실시하면 엔모스 영역의 폴리 실리콘막(14)은 인(P) 이온이 주입된 부분뿐만 아니라 그 하부의 폴리 실리콘막(14)까지 입자 크기가 커지게 된다.Subsequently, when the subsequent heat treatment process is performed, the particle size of the polysilicon film 14 in the NMOS region is increased not only to the portion in which phosphorus (P) ions are implanted but also to the polysilicon film 14 below.
이때, 상기 폴리 실리콘막(14)의 입자 크기가 증가하는 이유는 폴리 실리콘막 증착 직후, 폴리 실리콘막(14)의 구조가 아직 열역학적으로 안정화되지 않은 상태에서 인(P) 이온이 주입된 후 어닐 될 때 폴리 실리콘막(14)의 구조가 열적으로 안정화되어 가는 상태에서 인(P) 이온이 입자를 성장시켜 주기 때문이다.In this case, the particle size of the polysilicon film 14 is increased because the annealing after phosphorus (P) ions are injected after the polysilicon film 14 is not yet thermodynamically stabilized after the polysilicon film deposition. This is because phosphorus (P) ions grow particles in a state where the structure of the polysilicon film 14 is thermally stabilized.
이후, 도 1c에 도시된 바와 같이 포토 및 식각 공정으로 상기 폴리 실리콘막(14)과 게이트 산화막(13)을 선택적으로 제거하여 게이트(15)를 완성한다.Thereafter, as illustrated in FIG. 1C, the gate 15 is completed by selectively removing the polysilicon layer 14 and the gate oxide layer 13 by photo and etching processes.
이와 같은 게이트(15)는 폴리 실리콘막(14)의 입자가 크기 때문에 도 1c에 도시된 바와 같이 채널링(Channeling)에 취약해 지게 된다.Such a gate 15 is vulnerable to channeling (channeling), as shown in Figure 1c because the particles of the polysilicon film 14 is large.
채널링이란, 불순물 주입 공정인 임플란트(Implant) 공정에서 주입된 이온들이 어떤 결정 구조를 갖는 타겟(Target) 속으로 진행되어 이온의 진행방향이 결정 내부의 틈(Interstitial Site)들이 연속적으로 연결된 채널 방향으로 입사될 때 일어나는 현상으로, 예상 주입 범위(Projection Range)보다 훨씬 깊은 지점까지 도달하는 불순물 분포를 말한다.Channeling means that ions implanted in an implant process, which is an impurity implantation process, proceed into a target having a certain crystal structure, and thus the direction of the ions travels in a channel direction in which interstitial sites in the crystal are continuously connected. An incident phenomenon occurs when impurity distribution reaches a point far deeper than the expected projection range.
그러나, 상기와 같은 종래의 반도체 소자의 제조방법은 게이트 전극의 입자가 커서 채널링에 취약하므로 소자 특성이 열화되는 문제점이 있다.However, the conventional method of manufacturing a semiconductor device as described above has a problem in that device characteristics are degraded because particles of the gate electrode are large and vulnerable to channeling.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 게이트의 입자 크기가 과도하게 성장하는 것을 억제하므로써 채널링을 방지하기에 적합한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device suitable for preventing channeling by suppressing excessive growth of the particle size of the gate.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 제조공정 단면도1A to 1C are cross-sectional views of a manufacturing process of a semiconductor device according to the related art.
도 2a 내지 도 2b는 본 발명의 실시예에 따른 반도체 소자의 제조공정 단면도2A through 2B are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 3은 질소 이온을 주입하고 어닐 공정을 실시한 후에 게이트 전극을 촬영한 탬(TEM) 사진3 is a TEM photograph of a gate electrode after nitrogen ion is implanted and an annealing process is performed
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
21 : 반도체 기판 22 : 게이트 산화막21 semiconductor substrate 22 gate oxide film
23 : 폴리 실리콘막23: polysilicon film
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 반도체 기판상에 게이트 산화막과 게이트 전극용 폴리 실리콘막을 차례로 형성하는 단계와, 상기 폴리 실리콘막에 질소 이온을 주입하고 열처리하여 상기 폴리 실리콘막의 입자를 미세화시키는 단계와, 상기 폴리 실리콘막에 인 이온을 주입하는 단계를 포함하여 형성함을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of sequentially forming a gate oxide film and a polysilicon film for a gate electrode on a semiconductor substrate, injecting nitrogen ions into the polysilicon film and heat-treated to And miniaturizing particles of the polysilicon film, and implanting phosphorus ions into the polysilicon film.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2b는 본 발명의 실시예에 따른 반도체 소자의 제조공정 단면도이고, 도 3은 질소 이온을 주입하고 어닐 공정을 실시한 후에 게이트 전극을 촬영한 탬(TEM) 사진이다.2A and 2B are cross-sectional views illustrating fabrication processes of a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 3 is a TEM photograph of a gate electrode after implanting nitrogen ions and performing an annealing process.
본 발명에 따른 반도체 소자의 제조방법은 우선, 도 2a에 도시된 바와 같이, 반도체 기판(21)상에 게이트 산화막(22)과 게이트 전극용 폴리 실리콘막(23)을 차례로 형성한다.In the method of manufacturing a semiconductor device according to the present invention, first, as shown in FIG. 2A, a gate oxide film 22 and a polysilicon film 23 for a gate electrode are sequentially formed on a semiconductor substrate 21.
여기서, 상기 폴리 실리콘막(23)은 미세한 구조의 주상형(Columnar) 폴리 실리콘막이다.Here, the polysilicon film 23 is a columnar polysilicon film having a fine structure.
이어, 상기 반도체 기판(21)의 전면 또는 엔모스 영역에만 1014∼1016Ions/cm2의 농도를 갖는 질소(N2) 이온을 주입하여 상기 폴리 실리콘막(23)의 상부를 비정질화한다.Subsequently, nitrogen (N 2 ) ions having a concentration of 10 14 to 10 16 Ions / cm 2 are implanted into only the entire surface or the NMOS region of the semiconductor substrate 21 to amorphousize the upper portion of the polysilicon layer 23. .
이때, 상기 질소 이온은 10∼60Kev의 에너지로 주입하며 상기 폴리 실리콘막(23) 내부로 50∼1000Å의 깊이로 주입될 수 있도록 한다.In this case, the nitrogen ions are implanted at an energy of 10 to 60 Kev, and the nitrogen ions can be implanted to a depth of 50 to 1000 kV into the polysilicon film 23.
그리고, 상기 질소 이온이 폴리 실리콘막(23) 내부로 주입되는 깊이를 조절하기 위하여 틸트(Title)각을 가지고 이온 주입하여도 무방하다.In addition, in order to control the depth at which the nitrogen ions are injected into the polysilicon layer 23, the ion may be implanted with a tilt angle.
이어, 1∼60분간 700∼1000℃로 노(Furnace)를 이용한 열처리 공정 또는 1∼120초 동안 700∼1100℃로 RTP(Rapid Thermal Process) 공정을 실시하면 폴리 실리콘막(23) 상부의 입자가 미세하게 변형된다.Subsequently, when a heat treatment process using a furnace at 700 to 1000 ° C. for 1 to 60 minutes or a rapid thermal process (RTP) process at 700 to 1100 ° C. for 1 to 120 seconds is performed, particles on the top of the polysilicon film 23 are formed. It is finely deformed.
이때, 상기 질소 원자가 폴리 실리콘막(23)의 입자를 미세화시키는 작용을 하기 때문에 상기 폴리 실리콘막(23)의 입자는 조밀한 상태로 안정되게 된다.At this time, since the nitrogen atom acts to refine the particles of the polysilicon film 23, the particles of the polysilicon film 23 are stabilized in a dense state.
도 3은 질소 주입 및 어닐링 공정 이후에 안정화된 폴리 실리콘막(23)의 상태를 촬영한 사진으로, 폴리 실리콘막(23) 상부의 입자 크기가 하부 입자 크기에 비해 상당히 미세해 졌음을 알 수 있다.3 is a photograph of the state of the stabilized polysilicon film 23 after the nitrogen injection and annealing process, and it can be seen that the particle size of the upper part of the polysilicon film 23 is considerably finer than the lower particle size. .
이어, 도 2b에 도시된 바와 같이 상기 폴리 실리콘막(23)에 인(P) 이온을 주입한다.Subsequently, phosphorus (P) ions are implanted into the polysilicon film 23 as shown in FIG. 2B.
이어, 어닐링(Annealing) 공정을 실시하면 인(P) 이온이 주입되었던 폴리 실리콘막(23)의 상부만이 재결정화되면서 입자 크기가 증가하게 된다.Subsequently, when the annealing process is performed, only the upper portion of the polysilicon film 23 into which phosphorus (P) ions have been implanted is recrystallized, thereby increasing the particle size.
따라서, 폴리 실리콘막(23)을 전체적으로 보면, 상부 900∼1100Å만 입자가 큰 상태이고, 그 하부는 미세한 구조를 갖게 된다.Therefore, when the polysilicon film 23 is viewed as a whole, only 900-1100 kW of particles are in a large state, and the lower part has a fine structure.
상기와 같은 본 발명의 반도체 소자의 제조방법은 후속 이온 주입시 발생하는 채널링을 방지할 수 있는 효과가 있다.The method of manufacturing a semiconductor device of the present invention as described above has the effect of preventing channeling generated during subsequent ion implantation.
Claims (4)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11204793A (en) * | 1997-10-24 | 1999-07-30 | Lsi Logic Corp | Electronic device gate oxide hardening method and semiconductor device |
| KR20000044883A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming ldd structure of semiconductor device |
| KR20010020009A (en) * | 1999-08-31 | 2001-03-15 | 박종섭 | Method For Forming The Gate Electrode Of Semiconductor Device |
| JP2001250945A (en) * | 2000-03-08 | 2001-09-14 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| KR20010098183A (en) * | 2000-04-28 | 2001-11-08 | 윤종용 | Method of forming oxide film for semiconductor device |
-
2001
- 2001-12-26 KR KR1020010085285A patent/KR20030054854A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11204793A (en) * | 1997-10-24 | 1999-07-30 | Lsi Logic Corp | Electronic device gate oxide hardening method and semiconductor device |
| KR20000044883A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming ldd structure of semiconductor device |
| KR20010020009A (en) * | 1999-08-31 | 2001-03-15 | 박종섭 | Method For Forming The Gate Electrode Of Semiconductor Device |
| JP2001250945A (en) * | 2000-03-08 | 2001-09-14 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| KR20010098183A (en) * | 2000-04-28 | 2001-11-08 | 윤종용 | Method of forming oxide film for semiconductor device |
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