KR100322889B1 - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor device Download PDFInfo
- Publication number
- KR100322889B1 KR100322889B1 KR1019990067134A KR19990067134A KR100322889B1 KR 100322889 B1 KR100322889 B1 KR 100322889B1 KR 1019990067134 A KR1019990067134 A KR 1019990067134A KR 19990067134 A KR19990067134 A KR 19990067134A KR 100322889 B1 KR100322889 B1 KR 100322889B1
- Authority
- KR
- South Korea
- Prior art keywords
- type
- well
- ions
- semiconductor device
- manufacturing
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000007943 implant Substances 0.000 claims description 75
- 150000002500 ions Chemical class 0.000 claims description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims description 35
- 238000010438 heat treatment Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 6
- 238000001816 cooling Methods 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 17
- 230000007547 defect Effects 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
본 발명은 반도체장치의 제조방법에 관한 것으로서, 샐로우 트리플 웰(shallow triple well) 형성공정시 레트로그레이드 웰(retrograde well)의 이온주입시 소오스/드레인 영역과 레트로그레이드 웰의 스페이싱을 조절하여 쓰레딩 디스로케이션(threading dislocation)의 영향을 줄여 낮은 누설전류 특성을 갖도록 함으로써 신뢰성 높은 고품질의 소자를 제조할 수 있는 이점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a spacing of a source / drain region and a retrograde well is controlled by ion implantation of a retrograde well during a shallow triple well forming process. By reducing the influence of threading dislocation to have a low leakage current characteristics, there is an advantage that can be manufactured with high quality and high reliability.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 보다 상세하게는 샐로우 트리플 웰(shallow triple well) 형성공정시 레트로그레이드 웰(retrograde well)의 이온주입시 소오스/드레인 영역과 레트로그레이드 웰의 스페이싱을 조절하여 쓰레딩 디스로케이션(threading dislocation)의 영향을 줄여 낮은 누설전류 특성을 갖도록 하는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to spacing source / drain regions and retrograde wells during ion implantation of retrograde wells in a shallow triple well forming process. The present invention relates to a method of manufacturing a semiconductor device that has a low leakage current characteristic by reducing the influence of threading dislocation by adjusting.
요즈음은 반도체장치의 초고집적화가 급속히 추진됨에 따라 불순물이나 격자결함들이 극미량이라도 소자 구동영역에 존재할 경우에는 소자의 전기적 특성을 크게 저하시키기 때문에 반도체 공정 중 불순물이나 격자 결함들의 생성을 최대한 억제시키거나 또는 공정 중에 이를 제거해야만 한다.Nowadays, as ultra-high integration of semiconductor devices is rapidly promoted, even when a very small amount of impurities or lattice defects are present in the device driving region, the electrical characteristics of the device are greatly degraded, thereby minimizing the generation of impurities or lattice defects during the semiconductor process. It must be removed during the process.
도 1내지 도 6은 종래 방법에 의한 반도체장치의 제조방법을 설명하기 위한도면들이다.1 to 6 are diagrams for explaining a method of manufacturing a semiconductor device by a conventional method.
도 1에 도시된 바와 같이 P타입 실리콘 기판(10)에 STI공정을 진행하여 필드산화막(20)을 형성한다. 그런 다음 도 2와 같이 감광막을 이용하여 N_R 웰 (retrograde n-well) 임플란트 감광막 패턴(30)을 형성한 후 고에너지 이온 주입기를 사용하여 N_R 웰 임플란트를 수행하여 N_R 웰 영역(40)을 형성한다.As shown in FIG. 1, an STI process is performed on the P-type silicon substrate 10 to form a field oxide film 20. Then, as shown in FIG. 2, an N_R well (retrograde n-well) implant photoresist pattern 30 is formed using a photoresist film, and an N_R well implant is performed using a high energy ion implanter to form an N_R well region 40. .
그런 다음 도 3과 같이 N_R 웰 임플란트 감광막 패턴(30)을 제거한 후 다시 감광막을 이용하여 N-웰 임플란트 감광막 패턴(50)을 형성한 다음, 고에너지 이온 주입기를 사용하여 중간의 N-웰 임플란트와, P채널 필드 정지 임플란트를 수행하여 N-웰 임플란트 영역(60)과 P채널 필드 정지 임플란트 영역(70)을 형성하여 N-웰을 완성한다. 'A'그래프는 이온 주입량을 나타낸 프로파일이다.Then, after removing the N_R well implant photoresist pattern 30 as shown in FIG. 3, the N-well implant photoresist pattern 50 is again formed using the photoresist layer, and then the intermediate N-well implant is formed using a high energy ion implanter. The P-channel field stop implant is performed to form the N-well implant region 60 and the P-channel field stop implant region 70 to complete the N-well. 'A' graph is a profile showing the ion implantation amount.
그런 다음 도 4와 같이 N-웰 임플란트 감광막 패턴(50)을 제거한 후 다시 감광막을 이용하여 P-웰 임플란트 감광막 패턴(80)을 형성한 다음, 역시 고에너지 이온 주입기를 사용하여 P-웰 임플란트와, N채널 필드 정지 임플란트 공정을 수행하여 제 1내지 제 2 P-웰 임플란트 영역(90)(92)과, 제 1내지 제 2 N채널 필드 정지 임플란트 영역(100)(102)을 형성하여 제 1 P-웰 및 제 2 P-웰을 완성한다.Then, after removing the N-well implant photoresist pattern 50 as shown in FIG. 4, the P-well implant photoresist pattern 80 is again formed by using the photoresist layer, and the P-well implant is also used using a high energy ion implanter. And performing the N-channel field stop implant process to form the first to second P-well implant regions 90 and 92 and the first to second N-channel field stop implant regions 100 and 102. Complete the P-well and the second P-well.
그리고, 도 5와 같이 P-웰 임플란트 감광막 패턴(80)을 제거한 후 가열로에서 열처리를 수행하여 N-웰(110)과, P-웰(120)(122)을 활성화시켜 웰 형성공정을 완성하게 된다.Then, the P-well implant photoresist pattern 80 is removed and heat treatment is performed in a heating furnace to activate the N-well 110 and the P-wells 120 and 122 to complete the well formation process. Done.
이후, 도 6과 같이 제 1 P-웰(120)과 N_R 웰(110)로 둘러쌓인 제 2 P-웰(122) 등 2개의 P-웰(120)(122)과 1개의 N-웰(110)이 형성된다. 따라서, 제 2P-웰(122)에 형성되는 트랜지스터(132)는 제 1 P-웰(120)에 형성되는 트랜지스터(130)와 다른 독립적인 트랜지스터를 형성할 수도 있으며, N-R 웰(110)로 둘러싸여 있어 갑자기 유입되는 외부 전압이나 노이즈로부터 보호되는 장점이 있다.Subsequently, as shown in FIG. 6, two P-wells 120 and 122 and one N-well (eg, a second P-well 122 surrounded by the first P-well 120 and the N_R well 110) 110 is formed. Accordingly, the transistor 132 formed in the second P-well 122 may form an independent transistor different from the transistor 130 formed in the first P-well 120 and may be surrounded by the NR well 110. There is an advantage to be protected from the sudden external voltage or noise.
그러나, 각각의 N-웰, P-웰, N_R 웰을 형성할 때 이온주입 조건이 적절하지 않으면 큰 접합 누설전류를 유발하기도 하는데, 특히 고에너지 이온 주입기를 사용하여 N_R웰 임플란트를 수행할 때 이용하는31P 이온에 의한 손상은 이온 주입량이 비교적 낮아 소자 특성에는 별다른 영향을 주지 않을 것으로 알려져 있으나, 도 7에서 보는 바와 같이 3×1013정도에서도 변화가 큰 접합누설전류를 유발하고 있는 것으로 보아 RP(projected range) 뿐만 아니라 도 8과 같이 소오스/드레인 영역의 표면에 이르기까지 'B'와 같이 실모양의 쓰레딩 디스로케이션(threading dislocation)을 포함한 많은 미세결함을 생성시킴으로써 취약한 누설전류 특성을 나타내고 있다.However, inadequate ion implantation conditions in the formation of each N-well, P-well, or N_R well can lead to large junction leakage currents, especially when performing N_R well implants using high energy ion implanters. It is known that the damage caused by 31 P ions does not affect the device characteristics because the ion implantation amount is relatively low. However, as shown in FIG. 7, R P causes a large change in junction leakage current even at about 3 × 10 13 . As well as (projected range), as shown in FIG. 8, the microscopic defects including the threading dislocations, such as 'B', are formed to reach the surface of the source / drain regions, thereby exhibiting a weak leakage current characteristic.
이에 대한 해결책으로 N_R 웰 임플란트의 도즈량을 감소시켜 누설전류 특성을 개선하기도 하였으나 최근 들어 측벽으로의 확산을 우려하여 샐로우 트리플 웰 (shallow triple well)구조를 적용시 N_R 웰 임플란트의 이온 주입량이 1.5×1013이하임에도 불구하고 접합 누설전류가 취약하다는 문제점이 있다.As a solution to this, the dose of N_R well implants was reduced to improve leakage current characteristics. However, in recent years, since the shallow triple well structure is applied due to the fear of diffusion into the sidewall, the ion implantation amount of the N_R well implant is 1.5. Despite being less than 10 13 , the junction leakage current is vulnerable.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 이온주입공정에서 필연적으로 생성되는 결함은 대부분 RP에서부터 시작되기 때문에 낮은 도즈의 N_R 웰 임플란트 공정시 발생되는 쓰레딩 디스로케이션 등과 같은 미세결함의 생성위치를 적절히 공간적으로 조절해서 이들 결함이 누설전류 특성에 영향을 주지 않는 범위 내에서 N_R웰 이온주입 에너지를 결정하여 반도체장치를 제조하는 반도체장치의 제조방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is that the defects inevitably generated in the ion implantation process, since most of the defects originate from R P , threading dislocations generated during the low dose N_R well implant process. The present invention provides a method of manufacturing a semiconductor device in which a semiconductor device is fabricated by appropriately adjusting the location of generation of microdefects such as such that the defects do not affect the leakage current characteristics to determine the N_R well ion implantation energy.
도 1내지 도 6은 종래 방법에 의한 반도체장치의 제조방법을 설명하기 위한 도면들이다.1 to 6 are diagrams for explaining a method of manufacturing a semiconductor device by a conventional method.
도 7은 종래 방법에 의한 반도체장치에서의 이온주입량에 따른 누설전류값을 나타낸 그래프이다.7 is a graph showing a leakage current value according to an ion implantation amount in a semiconductor device by a conventional method.
도 8은 종래 방법에 의한 반도체장치에서의 쓰레딩 디스로케이션 결함을 나타낸 도면이다.8 is a diagram illustrating a threading dislocation defect in a semiconductor device according to a conventional method.
도 9내지 도 13은 본 발명에 의한 반도체장치의 제조방법을 설명하기 위한 도면들이다.9 to 13 are views for explaining a method of manufacturing a semiconductor device according to the present invention.
도 14는 본 발명에 의한 반도체장치에서의 이온주입량에 따른 누설전류값을 나타낸 그래프이다.14 is a graph showing a leakage current value according to an ion implantation amount in a semiconductor device according to the present invention.
도 15는 본 발명에 의한 반도체장치에서의 쓰레딩 디스로케이션 결함을 나타낸 도면이다.15 is a view showing a threading dislocation defect in a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 기판 20 : 필드산화막10: substrate 20: field oxide film
30 : N_R 웰 임플란트 감광막 패턴30: N_R well implant photoresist pattern
40 : N_R 웰 영역 50 : N-웰 임플란트 감광막 패턴40: N_R well region 50: N-well implant photoresist pattern
60 : N-웰 임플란트 영역 70 : P채널 필드 정지 임플란트 영역60: N-well implant area 70: P-channel field stop implant area
80 : P-웰 임플란트 감광막 패턴80: P-well implant photoresist pattern
90, 92 : 제 1내지 제 2 P-웰 임플란트 영역90, 92: first to second P-well implant regions
100, 102 : 제 1내지 제 2 N채널 필드 정지 임플란트 영역100 and 102: first to second N-channel field stop implant region
상기와 같은 목적을 실현하기 위한 본 발명은 샐로우 트리플 웰 구조의 반도체장치의 제조방법에 있어서, 제 1타입 반도체 기판에 STI공정을 진행하여 필드산화막을 형성하는 단계와, 상기 제 1타입 반도체 기판 상부에 제 2타입 레트로그레이드 임플란트 감광막 패턴을 형성한 후 제 2타입 이온을 주입하여 제 2타입 레트로그레이드 웰을 형성하는 단계와, 상기 제 2타입 레트로그레이드 임플란트 감광막 패턴을 제거한 후 제 2타입 웰 임플란트 감광막 패턴을 형성한 다음, 제 2타입 이온을 주입하여 제 2타입 웰 임플란트 공정과 제 1타입 채널 필드 정지 임플란트를 공정을 수행하여 제 2타입 웰을 형성하는 단계와, 상기 제 2타입 웰 임플란트 감광막 패턴을 제거한 후 제 1타입 웰 임플란트 감광막 패턴을 형성한 다음 제 1타입 이온을 주입하여 제 1타입 웰 임플란트 공정과 제 2타입 필드 정지 임플란트 공정을 수행하여 제 1타입의 제 1내지 제 2웰을 형성하는 단계와, 상기 제 1타입 웰 임플란트 감광막 패턴을 제거한 후 가열로를 사용하거나 가열로와 RTP를 순차적으로 사용하여 웰을 활성화시키는 단계로 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a shallow triple well structure semiconductor device, the method comprising: forming a field oxide film by performing an STI process on a first type semiconductor substrate; Forming a second type retrograde implant photoresist pattern on the upper part of the second type retrograde implant photoresist layer by implanting second type ions and then removing the second type retrograde implant photoresist pattern Forming a photoresist pattern, and then implanting a second type of ion to form a second type well by performing a second type well implant process and a first type channel field stop implant; and forming the second type well implant photoresist layer. After removing the pattern, the first type well implant photoresist pattern was formed, and then the first type well was implanted to inject the first type well. Forming a first to second well of a first type by performing an implant process and a second type field stop implant process; and removing the first type well implant photoresist pattern and then using a heating furnace or a heating furnace and RTP. It is characterized by consisting of steps of activating the well using sequentially.
위와 같이 이루어진 본 발명은 N_R 웰 임플란트 공정시 소오스/드레인과 N_R 웰 영역의 스페이싱을 조절하여 쓰레딩 디스로케이션에 의한 미세결함의 영향을 줄여 낮은 누설전류 특성을 갖도록 한다.The present invention made as described above has a low leakage current characteristic by reducing the effect of microdefects due to threading dislocation by adjusting the spacing of the source / drain and N_R well region during the N_R well implant process.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도 9내지 도 13은 본 발명에 의한 반도체장치의 제조방법을 설명하기 위한 도면들이다.9 to 13 are views for explaining a method of manufacturing a semiconductor device according to the present invention.
도 9에 도시된 바와 같이 P타입 실리콘 기판(10)에 STI공정을 진행하여 필드산화막(20)을 형성한다. 그런 다음 도 10와 같이 감광막을 이용하여 N_R 웰 (retrograde n-well) 임플란트 감광막 패턴(30)을 형성한 후 고에너지 이온 주입기를 사용하여31P 이온을 0.6∼3.0 MeV의 에너지로 5×1012ions/㎠∼1×1015ions/㎠ 만큼 주입하여 N_R 웰 임플란트 공정을 수행하여 N_R 웰 영역(40)을 형성한다.As shown in FIG. 9, an STI process is performed on the P-type silicon substrate 10 to form a field oxide film 20. Then, as shown in FIG. 10, after the N_R well (retrograde n-well) implant photoresist pattern 30 was formed using the photoresist layer, 31 P ions were converted into 5 × 10 12 with energy of 0.6 to 3.0 MeV using a high energy ion implanter. The N_R well region 40 is formed by implanting ions / cm 2 to 1 × 10 15 ions / cm 2 to perform an N_R well implant process.
이때 고에너지 이온 주입기를 사용하여 N_R 웰 임플란트 공정을 행할 때 이온 주입에너지는 P+ S/D에서 N_R 웰 스페이싱을 최소 0.95㎛ 이상이 되도록 결정한다.At this time, when the N_R well implant process is performed using a high energy ion implanter, the ion implantation energy is determined so that the N_R well spacing is at least 0.95 µm at P + S / D.
그리고, N_R 웰 임플란트 감광막 패턴(30)은 고에너지 이온 주입 전용으로 사용되는 것으로서 밀도가 1∼10g/㎤ 정도이고 두께는 2.5㎛이상이 되도록 형성한다.The N_R well implant photosensitive film pattern 30 is used for high energy ion implantation only, and is formed to have a density of about 1 to 10 g / cm 3 and a thickness of 2.5 μm or more.
그런 다음 도 11과 같이 N_R 웰 임플란트 감광막 패턴(30)을 제거한 후 다시 감광막을 이용하여 N-웰 임플란트 감광막 패턴(50)을 형성한 다음, 고에너지 이온 주입기를 사용하여 중간의 N-웰 임플란트와, P채널 필드 정지 임플란트를 수행하여 N-웰 임플란트 영역(60)과 P채널 필드 정지 임플란트 영역(70)을 형성하여 N-웰을 완성한다.Then, after removing the N_R well implant photoresist pattern 30 as shown in FIG. 11, the N-well implant photoresist pattern 50 is formed again using the photoresist layer, and then the intermediate N-well implant is formed using a high energy ion implanter. The P-channel field stop implant is performed to form the N-well implant region 60 and the P-channel field stop implant region 70 to complete the N-well.
이때 중간의 N-웰 임플란트 공정은31P 이온을 500KeV∼1.0 MeV 에너지로 5×1012ions/㎠∼5×1013ions/㎠ 만큼 주입하여 수행하고, P채널 필드 정지 임플란트 공정을31P 이온을 150KeV∼300KeV 에너지로 5×1011ions/㎠∼1×1013ions/㎠ 만큼 주입하여 수행한다.In this case, the intermediate N-well implant process is performed by implanting 31 P ions by 5 × 10 12 ions / cm 2 to 5 × 10 13 ions / cm 2 with 500 KeV ~ 1.0 MeV energy, and performing the P-channel field stop implant process with 31 P ions. Is carried out by injecting 5 × 10 11 ions / cm 2 to 1 × 10 13 ions / cm 2 with 150 KeV to 300 KeV energy.
'C'그래프는 이온 주입량을 나타낸 프로파일이다.'C' graph is a profile showing the ion implantation amount.
그런 다음 도 12와 같이 N-웰 임플란트 감광막 패턴(50)을 제거한 후 다시 감광막을 이용하여 P-웰 임플란트 감광막 패턴(80)을 형성한 다음, 역시 고에너지 이온 주입기를 사용하여 P-웰 임플란트와, N채널 필드 정지 임플란트 공정을 수행하여 제 1내지 제 2 P-웰 임플란트 영역(90)(92)과, 제 1내지 제 2 N채널 필드 정지 임플란트 영역(100)(102)을 형성하여 제 1 P-웰 및 제 2 P-웰을 완성한다.Then, after removing the N-well implant photoresist pattern 50 as shown in FIG. 12, the P-well implant photoresist pattern 80 is again formed by using the photoresist layer, and the P-well implant is also used using a high energy ion implanter. And performing the N-channel field stop implant process to form the first to second P-well implant regions 90 and 92 and the first to second N-channel field stop implant regions 100 and 102. Complete the P-well and the second P-well.
이때, 제 1내지 제 2 P-웰 임플란트 공정을 수행할 때 이온주입량은 1×1013ions/㎠∼5×1013ions/㎠ 이고, 이온주입 에너지는 180KeV∼300KeV 으로 진행한다.At this time, the first to the second and the ion injection amount when performing a P- well implant step is 1 × 10 13 ions / ㎠~5 × 10 13 ions / ㎠, ion implantation energy, the process proceeds to 180KeV~300KeV.
그리고, N채널 필드 정지 임플란트 공정을 수행할 때 이온주입량은 5×1011ions/㎠∼1×1013ions/㎠ 이고, 이온주입 에너지는 80KeV∼100KeV 으로 진행한다.When the N-channel field stationary implant process is performed, the ion implantation amount is 5 × 10 11 ions / cm 2 to 1 × 10 13 ions / cm 2, and the ion implantation energy proceeds at 80 KeV to 100 KeV.
그리고, 도 13과 같이 P-웰 임플란트 감광막 패턴(80)을 제거한 후 가열로를 사용하거나 가열로와 RTP를 순차적으로 사용하여 N-웰(110)과 P-웰(120)(122)을 활성화시킨다.Then, after removing the P-well implant photoresist pattern 80 as shown in FIG. 13, the N-well 110 and the P-well 120 and 122 are activated by using a heating furnace or sequentially using the heating furnace and RTP. Let's do it.
이때 가열로의 온도는 900℃∼1000℃로, 30분∼1.5시간으로 진행한다.At this time, the temperature of a heating furnace is 900 degreeC-1000 degreeC, and it progresses to 30 minutes-1.5 hours.
그리고, 가열로와 RTP를 순차적으로 사용할 때는 RTP온도를 900℃∼1100℃로 30초∼5분으로 진행하고, RTP 열처리시 승온속도는 30℃/초∼250℃/초로 한다.And when using a heating furnace and RTP sequentially, RTP temperature advances to 900 to 1100 degreeC for 30 second-5 minutes, and the temperature increase rate during RTP heat processing shall be 30 degreeC / sec-250 degreeC / sec.
또한, 가열로와 RTP를 순차적으로 사용할 때 RTP 열처리시 분위기를 N2를 1∼20 slpm으로 흘리면서 N2분위기에서 진행한다.In addition, a sloppy atmosphere during the heat treatment when using the RTP and the RTP in the N 2 heating sequentially by 1~20 slpm proceeds in the N 2 atmosphere.
그리고, RTP 냉각시 냉각속도는 50∼100℃/sec로 진행한다.In addition, the cooling rate during RTP cooling proceeds at 50 to 100 ° C / sec.
본 발명에 의한 방법으로 고에너지 이온 주입기를 사용하여 N_R웰 임플란트를 수행할 때 이용하는31P 이온에 의한 손상을 도 14에 도시하였다.The damage by 31 P ions used when performing an N_R well implant using a high energy ion implanter by the method according to the invention is shown in FIG. 14.
여기에서 보는 바와 같이 'B'로 표시된 실모양의 쓰레딩 디스로케이션(threading dislocation)은 소오스/드레인 영역과 일정한 공간을 두고생성되어 누설전류 특성을 감소시키고 있다.As shown here, the thread-shaped threading dislocation indicated by 'B' is generated with a certain space with the source / drain region to reduce the leakage current characteristic.
도 15에 도시된 바와 같이 N_R 웰 임플란트시 RP값을 0.95㎛로 했을 때의 누설전류값 그래프(D)와 RP값을 0.75㎛로 했을 때의 누설전류값 그래프(E)를 비교해보면 현저하게 누설전류값이 감소하고 있음을 알 수 있다.As shown in FIG. 15, the leakage current value graph (D) when the R P value is 0.95 μm and the leakage current value graph (E) when the R P value is 0.75 μm is significant when the N_R well implant is used. It can be seen that the leakage current value is decreasing.
이렇게 N_R 웰 스페이싱을 즉, RP값을 0.2㎛ 증가시겼을 접합 누설전류값이 1차수 적어지고 있음을 알 수 있다.Thus, it can be seen that the junction leakage current value decreases by one order when the N_R well spacing, that is, the RP value is increased by 0.2 µm.
상기한 바와 같이 본 발명은 샐로우 트리플 웰 형성공정시 레트로그레이드 웰의 이온주입시 소오스/드레인 영역과 레트로그레이드 웰의 스페이싱을 조절하여 쓰레딩 디스로케이션의 영향을 줄여 낮은 누설전류 특성을 갖도록 함으로써 신뢰성 높은 고품질의 소자를 제조할 수 있는 이점이 있다.As described above, the present invention controls the spacing of the source / drain region and the retrograde well during ion implantation of the retrograde well during the shallow triple well forming process, thereby reducing the influence of threading dislocation to have a low leakage current characteristic. There is an advantage that a high quality device can be manufactured.
Claims (11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990067134A KR100322889B1 (en) | 1999-12-30 | 1999-12-30 | Method for manufacturing a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990067134A KR100322889B1 (en) | 1999-12-30 | 1999-12-30 | Method for manufacturing a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010059613A KR20010059613A (en) | 2001-07-06 |
| KR100322889B1 true KR100322889B1 (en) | 2002-02-09 |
Family
ID=19634252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990067134A KR100322889B1 (en) | 1999-12-30 | 1999-12-30 | Method for manufacturing a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100322889B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8716097B2 (en) * | 2012-08-13 | 2014-05-06 | Texas Instruments Incorporated | MOS transistors having reduced leakage well-substrate junctions |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183393A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Fabrication of semiconductor device |
| US5501993A (en) * | 1994-11-22 | 1996-03-26 | Genus, Inc. | Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation |
| KR19990015385A (en) * | 1997-08-06 | 1999-03-05 | 윤종용 | Triple well formation method of semiconductor device |
| JPH11168145A (en) * | 1997-12-02 | 1999-06-22 | Nippon Steel Corp | Manufacture of semiconductor device |
| US5985709A (en) * | 1996-04-16 | 1999-11-16 | United Microelectronics Corp. | Process for fabricating a triple-well structure for semiconductor integrated circuit devices |
-
1999
- 1999-12-30 KR KR1019990067134A patent/KR100322889B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183393A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Fabrication of semiconductor device |
| US5501993A (en) * | 1994-11-22 | 1996-03-26 | Genus, Inc. | Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation |
| US5985709A (en) * | 1996-04-16 | 1999-11-16 | United Microelectronics Corp. | Process for fabricating a triple-well structure for semiconductor integrated circuit devices |
| KR19990015385A (en) * | 1997-08-06 | 1999-03-05 | 윤종용 | Triple well formation method of semiconductor device |
| JPH11168145A (en) * | 1997-12-02 | 1999-06-22 | Nippon Steel Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010059613A (en) | 2001-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100283712B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR20010006284A (en) | Method of controlling dopant concentrations by implanting gettering atoms | |
| KR100324931B1 (en) | Method of Fabricating a Twin Well CMOS Device | |
| KR100322889B1 (en) | Method for manufacturing a semiconductor device | |
| KR100445055B1 (en) | Method for fabricating semiconductor device with triple well structure | |
| KR100328455B1 (en) | Method of manufacuring a semiconductor device | |
| KR100294644B1 (en) | Triple Well Forming Method of Semiconductor Device_ | |
| KR100429556B1 (en) | Method for fabricating semiconductor device improved channel property | |
| KR100513445B1 (en) | Method for manufacturing semiconductor device | |
| KR100524465B1 (en) | Method of manufacturing in semiconductor device | |
| KR100308653B1 (en) | Method of forming BILLI well of semiconductor device | |
| JP2004080028A (en) | Method for manufacturing mos transistor | |
| KR100406589B1 (en) | Manufacturing method of semiconductor device | |
| KR100474505B1 (en) | Manufacturing method of semiconductor device | |
| KR100294643B1 (en) | Triple Well Forming Method of Semiconductor Device_ | |
| KR100799020B1 (en) | Method of manufacturing a semiconductor memory device | |
| KR100422325B1 (en) | Fabricating method of semiconductor device | |
| KR100468695B1 (en) | Method for fabricting high performance MOS transistor having channel doping profile to improve short channel effect | |
| KR20000027654A (en) | Method for fabricating semiconductor devices | |
| KR100671595B1 (en) | Method of forming a triple-well in a semiconductor device | |
| KR100316019B1 (en) | Method for forming triple well of semiconductor device | |
| KR0172523B1 (en) | Method of fabricating semiconductor device well | |
| KR100600244B1 (en) | Method for fabricating the multi-gate of semiconductor device | |
| KR20000041401A (en) | Method for fabricating semiconductor device | |
| JPS58178561A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101224 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |