KR0172523B1 - Method of fabricating semiconductor device well - Google Patents
Method of fabricating semiconductor device well Download PDFInfo
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- KR0172523B1 KR0172523B1 KR1019950050979A KR19950050979A KR0172523B1 KR 0172523 B1 KR0172523 B1 KR 0172523B1 KR 1019950050979 A KR1019950050979 A KR 1019950050979A KR 19950050979 A KR19950050979 A KR 19950050979A KR 0172523 B1 KR0172523 B1 KR 0172523B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000005468 ion implantation Methods 0.000 claims abstract description 29
- 239000012535 impurity Substances 0.000 claims description 23
- 150000002500 ions Chemical class 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 8
- 238000009826 distribution Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 프로파일드 웰(Profiled Well)의 P-채널(Channel)이 형성되는 영역(N-웰의 표면)의 바로 밑 부분에 Ph를 소오스로 도핑한 후, NMOS 트랜지스터의 문턱전압 이온주입과 PMOS 트랜지스터의 문턱전압 이온주입을 동시에 진행하는 반도체 소자의 웰 형성 방법에 관한 것으로, PMOS 트랜지스터의 문턱전압이 P-채널의 농도만으로 조절되는 것이 아니라 그 밑 영역의 N-형 불순물 농도에 의해서도 결정되므로, NMOS 및 PMOS 지역의 문턱전압 이온주입을 동시에 실시하면서, 각 트랜지스터의 특성을 독립적으로 최적화 시키는 효과가 있다.According to the present invention, after doping Ph with a source directly under a region where a P-channel of a profiled well is formed (a surface of an N-well), a threshold voltage ion implantation and a PMOS of an NMOS transistor are performed. The present invention relates to a method for forming a well of a semiconductor device which simultaneously performs a threshold voltage ion implantation of a transistor. While simultaneously performing threshold voltage ion implantation in the NMOS and PMOS regions, there is an effect of independently optimizing the characteristics of each transistor.
Description
제1도는 확산에 의한 웰의 깊이에 따른 농도 분포도.1 is a concentration distribution according to the depth of a well by diffusion.
제2도는 확산에 의한 웰에 문턱전압 조절을 위한 이온주입 후의 깊이에 따른 농도 분포도.Figure 2 is a concentration distribution according to the depth after ion implantation for adjusting the threshold voltage in the well by diffusion.
제3도는 프로파일드 웰의 깊이에 따른 농도 분포도.3 is a distribution of concentrations depending on the depth of the profiled well.
제4도는 본 발명에 따른 웰의 깊이에 따른 농도 분포도.4 is a concentration distribution according to the depth of the well according to the present invention.
제5도는 트윈 웰 구조 단면도.5 is a cross-sectional view of a twin well structure.
제6도는 트리플 웰 구조 단면도.6 is a cross-sectional view of a triple well structure.
본 발명은 반도체 소자 제조 공정중 웰(well) 형성 방법에 관한 것이다.The present invention relates to a method of forming a well during a semiconductor device manufacturing process.
DRAM이 고집적화함에 따라 제조 공정의 공정 단순화는 공정시간단축, 공정 비용 감소, 수율 향상 등의 측면에서 점점 중요성을 더하고 있다. 한편 트랜지스터 형성은 집적 공정의 초기 공정으로 이의 공정 단순화는 소자 특성을 좌우하므로 트랜지스터 최적화에 걸림돌이 된다.As DRAMs become more integrated, process simplification is becoming increasingly important in terms of process time reduction, process cost reduction, and yield improvement. Transistor formation, on the other hand, is an initial step in the integration process, and its simplification depends on device characteristics, which impedes transistor optimization.
공정 단순화의 한가지 방안으로 NMOS 트랜지스터와 PMOS 트랜지스터가 동시에 사용되는 소자에서 NMOS 트랜지스터의 문턱전압 이온주입과 PMOS 트랜지스터의 문턱전압 이온주입을 동시에 진행하는 방법을 생각할 수 있다.As a method of simplifying the process, a method of simultaneously performing the threshold voltage ion implantation of the NMOS transistor and the threshold voltage ion implantation of the PMOS transistor in a device in which the NMOS transistor and the PMOS transistor are used simultaneously can be considered.
그러나, NMOS 트랜지스터의 문턱전압 이온주입과 PMOS 트랜지스터의 문턱전압 이온주입을 동시에 진행하는 방법은 다음과 같은 문제점을 갖는다.However, the method of simultaneously performing the threshold voltage ion implantation of the NMOS transistor and the threshold voltage ion implantation of the PMOS transistor has the following problems.
제1도 및 제2도에 도시된 바와 같이 웰의 깊은 지역과 낮은 지역 모두 농도가 유사한 구조인 확산에 의한 웰(Diffused Well) 구조(제1도)에서는 NMOS 트랜지스터의 문턱전압 이온주입과 PMOS 트랜지스터의 문턱전압 이온주입을 동시에 진행하게되면(제2도), NMOS 트랜지스터의 문턱전압을 높이기 위해 이온주입 도스(Dose)를 높일 경우 N-웰에 있는 PMOS의 문턱전압이 낮아지고, 반대로 NMOS 트랜지스터의 문턱전압을 낮추기 위해 이온주입 도스(Dose)를 낮출 경우 N-웰에 있는 PMOS의 문턱전압이 높아진다.As shown in FIG. 1 and FIG. 2, in a diffused well structure (FIG. 1) in which the deep and low regions of the well are similar in concentration, the threshold voltage ion implantation and the PMOS transistor of the NMOS transistor are shown. If the ion implantation is simultaneously performed (Figure 2), increasing the ion implantation dose to increase the threshold voltage of the NMOS transistor lowers the threshold voltage of the PMOS in the N-well, and conversely, Lowering the ion implantation dose to lower the threshold voltage increases the threshold voltage of the PMOS in the N-well.
그러므로, NMOS 트랜지스터 및 PMOS 트랜지스터의 문턱전압을 원하는 값으로 동시에 얻기 위해서는 초기에 PMOS 트랜지스터가 형성되는 N-웰의 농도를 결정해 주어야 한다.Therefore, in order to simultaneously obtain the threshold voltages of the NMOS transistor and the PMOS transistor at a desired value, the concentration of the N-well in which the PMOS transistor is formed must be determined initially.
그러나, N-웰의 농도를 결정해주면, Well의 농도에 의해서 결정되는 전기적 특성들(Junction Breakdown, Junction Capacitance, Punchthrough 등)이 서로 연결되어 이들 각각을 독립적으로 최적화시킬수 없으며 최종적으로는 트랜지스터를 최적화 시키는데 한계가 있게 된다.However, when the concentration of N-well is determined, the electrical characteristics (Junction Breakdown, Junction Capacitance, Punchthrough, etc.) determined by the concentration of Well are connected to each other and cannot be optimized independently of each other. There is a limit.
따라서, 본 발명은 트랜지스터의 특성을 최적화 시키면서 소자를 구성하는 NMOS 트랜지스터의 문턱전압 이온주입과 PMOS 트랜지스터의 문턱전압 이온주입을 동시에 진행하여 공정 단순화를 가져오는 웰 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a well-forming method for simplifying the process by simultaneously performing the threshold voltage ion implantation of the NMOS transistor constituting the device and the threshold voltage ion implantation of the PMOS transistor optimizing the characteristics of the transistor.
상기 목적을 달성하기 위하여 본 발명은 반도체 소자의 웰 형성 방법에 있어서; 반도체 기판의 소정 부위에 제1웰 마스크를 형성하고 제1불순물을 이온주입하여 제1웰을 형성하는 단계; 상기 제1웰 마스크를 제거한 후, 제2웰 마스크를 형성하고 제2불순물을 1MeV 이상의 높은 에너지로 이온주입하여 제2웰을 형성하는 단계; 상기 제2웰 마스크가 형성된 상태에서 제2불순물을 200KeV 이상의 에너지로 이온주입하는 단계; 상기 제2웰 마스크가 형성된 상태에서 제2불순물을 70 KeV 내지 90 KeV 에너지로 이온주입하는 단계; 상기 제2웰 마스크를 제거하고, 제1웰 및 제2웰에 동시에 문턱전압 조절을 위한 이온주입을 실시하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a well of a semiconductor device; Forming a first well mask on a predetermined portion of the semiconductor substrate and ion implanting the first impurity to form a first well; Removing the first well mask, forming a second well mask and ion implanting the second impurity with a high energy of 1 MeV or more to form a second well; Ion implanting a second impurity with energy of 200 KeV or more in the state where the second well mask is formed; Ion implanting a second impurity with 70 KeV to 90 KeV energy in a state where the second well mask is formed; Removing the second well mask, and simultaneously performing ion implantation on the first well and the second well to adjust the threshold voltage.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
제3도에 도시된 바와 같이 프로파일드 웰(Profiled Well)이란 높은 에너지의 이온주입장비를 이용하여 열 공정을 거치지 않고 원하는 깊이에 불순물(Impurity)을 위치시키고 이를 여러 가지 에너지와 도스로 진행하여 도핑(Doping) 농도가 프로파일를 갖도록 한 웰 구조를 말한다.As shown in FIG. 3, a profiled well is a high energy ion implanter, which places impurities at a desired depth without undergoing a thermal process and proceeds to various energies and doses to doping. Doping refers to a well structure that has a profile.
이와 같이 열 공정을 거치지 않으므로 웰 영여과 표면 영역의 농도를 서로 독립적으로 제어할 수 있는 장점이 있다. 이러한 웰 구조를 이용하여, NMOS 트랜지스터의 문턱전압 이온주입과 PMOS 트랜지스터의 문턱전압 이온주입을 동시에 진행하면, NMOS 트랜지스터 및 PMOS 트랜지스터의 특성을 독립적으로 최적화 할 수 있다.As such, since the thermal process is not performed, the concentration of the well filtration and the surface region may be independently controlled. By using the well structure, the threshold voltage ion implantation of the NMOS transistor and the threshold voltage ion implantation of the PMOS transistor are simultaneously performed to independently optimize the characteristics of the NMOS transistor and the PMOS transistor.
즉, 제4도에 도시된 바와 같이 P-채널(Channel)이 형성되는 영역(N-웰의 표면)의 바로 밑 부분에 Ph를 소오스로 도핑한 후, NMOS 트랜지스터의 문턱전압 이온주입과 PMOS 트랜지스터의 문턱전압 이온주입을 동시에 진행하는 것이다.That is, as shown in FIG. 4, after doping Ph with a source directly below a region where the P-channel is formed (the surface of the N-well), the threshold voltage ion implantation of the NMOS transistor and the PMOS transistor are performed. The threshold voltage ion implantation is performed simultaneously.
이때, 문턱전압 조절 이온주입의 농도는 NMOS 문턱전압 타겟(Target)에 맞추고, NMOS 문턱전압 타겟은 P-채널 하부의 농도로 맞춘다.In this case, the concentration of the threshold voltage adjusting ion implantation is adjusted to the NMOS threshold voltage target, and the NMOS threshold voltage target is adjusted to the concentration under the P-channel.
이는 P-채널 밑의 N-형 불순물 농도에 따라 P-채널 영역의 디플레션(Depletion) 정도가 달라져 PMOS의 문턱전압이 변하게 된다.This is because the degree of deflation of the P-channel region varies according to the concentration of N-type impurities below the P-channel, thereby changing the threshold voltage of the PMOS.
본 발명의 일실시예는 제5도와 같은 트윈 웰 구조를 형성하는 방법이다.One embodiment of the present invention is a method of forming a twin well structure as shown in FIG.
먼저, 실리콘 기판상에 P-웰 마스크를 형성하고 P형 불순물을 이온주입하여 P-웰을 형성한다.First, a P-well mask is formed on a silicon substrate and P-wells are formed by ion implantation of P-type impurities.
이어서, P-웰 마스크를 제거하고, N-웰 마스크를 형성한 후, N형 불순물을 1MeV 내지 1.5MeV이상의 높은 에너지로 이온주입하여 N-웰을 형성한다. 이때 실리콘 기판의 손상 및 불순물 이온의 채널링을 방지하기 위해 실리콘 기판상에 산화막과 같은 절연막을 형성한후 높은 에너지 이온주입을 실시한다. 그리고 반도체 기판을 일정한 온도로 유지한다.Subsequently, after removing the P-well mask and forming an N-well mask, N-type impurities are implanted at a high energy of 1 MeV to 1.5 MeV or more to form an N-well. At this time, in order to prevent damage to the silicon substrate and channeling of impurity ions, an insulating film such as an oxide film is formed on the silicon substrate, and then high energy ion implantation is performed. The semiconductor substrate is maintained at a constant temperature.
이어서, N-웰의 아이솔레이션 특성 확보를 위해 N-웰 마스크가 형성된 상태에서 N형 불순물을 220KeV 내지 280KeV 이상의 에너지로 이온주입한다.Subsequently, in order to secure isolation characteristics of the N-well, the N-type impurity is ion implanted with an energy of 220 KeV to 280 KeV or more in a state where an N-well mask is formed.
이어서, N-웰 마스크가 형성된 상태에서 N형 불순물을 70 내지 90 KeV 에너지로 이온주입하여 P-채널 하부에 N 형 불순물을 분포시킨다.Subsequently, in the state where the N-well mask is formed, the N-type impurity is implanted at 70 to 90 KeV energy to distribute the N-type impurity under the P-channel.
이어서, N-웰 마스크를 제거하고, P-웰 및 N-웰에 동시에 문턱전압 조절을 위한 이온주입을 실시한다. 문턱전압 조절을 위한 이온주입은 NMOS 문턱전압 타겟에 맞추는데 통상적으로 40KeV 내지 50KeV 이하의 낮은 에너지로 이온주입한다.Subsequently, the N-well mask is removed, and ion implantation for adjusting the threshold voltage is simultaneously performed on the P-well and the N-well. Ion implantation for threshold voltage regulation is tailored to the NMOS threshold voltage target, which is typically implanted at low energy below 40KeV to 50KeV.
본 발명은 다른 실시예로서, 제6도와 같은 트리플(triple) 웰에도 적용할 수 있는데, 그 방법은 상기 제5도와 같은 트윈을 형성하기 위한 방법을 실시하기 이전에 마스크를 사용하지 않고, N형 불순물을 1.5MeV 내지 2MeV의 에너지로 이온주입한 다음, 동일한 공정을 진행함으로써 얻을 수 있다.In another embodiment, the present invention can be applied to a triple well as shown in FIG. 6, wherein the method does not use a mask before performing a method for forming a twin as shown in FIG. Impurities may be obtained by ion implantation at an energy of 1.5 MeV to 2MeV and then proceeding with the same process.
이상, 상술한 바와 같은 본 발명은 PMOS 트랜지스터의 문턱전압이 P-채널의 농도만으로 조절되는 것이 아니라 그 밑 영역의 N-형 불순물 농도에 의해서도 결정되므로, NMOS 및 PMOS 지역의 문턱전압 이온주입을 동시에 실시하면서, 각 트랜지스터의 특성을 독립적으로 최적화 시키는 효과가 있다.As described above, in the present invention, the threshold voltage of the PMOS transistor is determined not only by the concentration of the P-channel but also by the N-type impurity concentration in the underlying region, so that the threshold voltage ion implantation in the NMOS and PMOS regions is simultaneously performed. In practice, there is an effect of independently optimizing the characteristics of each transistor.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950050979A KR0172523B1 (en) | 1995-12-16 | 1995-12-16 | Method of fabricating semiconductor device well |
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| KR1019950050979A KR0172523B1 (en) | 1995-12-16 | 1995-12-16 | Method of fabricating semiconductor device well |
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| KR970053943A KR970053943A (en) | 1997-07-31 |
| KR0172523B1 true KR0172523B1 (en) | 1999-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950050979A KR0172523B1 (en) | 1995-12-16 | 1995-12-16 | Method of fabricating semiconductor device well |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172523B1 (en) |
-
1995
- 1995-12-16 KR KR1019950050979A patent/KR0172523B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970053943A (en) | 1997-07-31 |
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