CN103531542A - Manufacturing method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device for reducing back bias voltage and temperature instability - Google Patents
Manufacturing method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device for reducing back bias voltage and temperature instability Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
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- 229910052796 boron Inorganic materials 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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Abstract
The invention provides a manufacturing method of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device for reducing back bias voltage and temperature instability. The manufacturing method comprises the following steps: step 1, carrying out trap injection in a substrate to form a P type trap and an N type trap; step 2, manufacturing a grid electrode oxidized layer on the surface of the substrate; step 3, depositing a grid electrode layer on the surface of the grid electrode oxidized layer; step 4, carrying out photo-etching on the grid electrode layer to form a PMOS (P-channel Metal Oxide Semiconductor) grid electrode on the P type trap; forming an NMOS (N-channel Metal Oxide Semiconductor) grid electrode on the N type trap; step 5, respectively manufacturing grid electrode side walls I at the side edges of the PMOS grid electrode and the NMOS grid electrodes; step 6, carrying out light dope injection to form a PMOS light dope source drain structure and forming an NMOS light dope source drain structure in the N type trap; step 7, depositing a silicon nitride thin film on the surface of the device; step 8, irradiating on a silicon wafer by using UV (Ultraviolet) light; step 9, manufacturing a side wall II at one side edge of each grid electrode side wall I; and step 10, carrying out source drain injection formation so as to form a PMOS source drain electrode in the P type trap and form an NMOS source drain electrode in the P type trap.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of cmos device manufacture method that reduces Negative Bias Temperature Instability (NBTI:Negative Bias Temperature Instability).
Background technology
Along with developing rapidly of very large scale integration technology, the size of MOSFET device is constantly reducing.Due to sharply reducing of mosfet transistor size, it is even thinner that the thickness of gate oxide is decreased to 2nm.In the scaled size of MOS device, operating voltage is correspondingly equal proportion reduction not, and this significantly increases raceway groove electric field and the electric field across oxide of MOS device, and the degeneration that NBTI effect causes is day by day remarkable.NBTI, Negative Bias Temperature Instability, is often referred to PMOS pipe and shows to obtain device performance degeneration under high temperature, the effect of high field minus gate voltage.Electrically temperature is in the scope of 80-250 degree, as shown in Figure 1.The NBTI off-state current (Ioff) show as device of degenerating increases, the drift of threshold voltage (Vth) negative sense, and mutual conductance (Gm) and leakage current (Ids) reduce etc.In addition, in order to improve transistor performance, reduce the leakage current of gate oxide, in gate oxide, introducing N atom has become a kind of technological standards, and still, being introduced in of N atom aggravated device NBTI degeneration to a certain extent.
In to the research of NBTI degradation mechanism, generally believe that the dangling bonds of the Si that is the generation of SiO2/Si interface cause.In NBTI stress path, Fixed oxide charge and the interface trap (Si3 Ξ Si) that participates in producing due to surface voids are the main causes that causes NBTI effect.And Si-H key has all play a part crucial in the NBTI effect that fixed charge and interface trap cause.Under NBTI stress condition, hole can make Si-H key decompose under the effect of electric field, thereby forms interface trap, as shown in Figure 2 A and 2 B, causes the degeneration of device.Reaction equation is as follows:
Interface falls into spells Si
3≡ SiH → Si
3≡ Si ten H
0
Si
3≡ SiH ten H
+→ Si
3→ Si ten H
2
Oxide trapped charge O
3→ SiH → O
3≡ Si ten H
0
O
3three S's iH ten H
+→ O
3≡ Si ten H
2
But in cmos device gate oxide, H becomes key material as fixed charge and Si in interface trap main, is the most common and inevitable impurity, and plays a major role in NBTI course of reaction.In present cmos process flow, taked related measure to suppress NBTI effect.Such as at SiO
2/ Si interface, by the defect passivation of deuterium (D), is having great advantage aspect raising device reliability.Because according to kinetic isotope effect, break the Si-D key ratio forming with deuterium more difficult with the Si-H key that hydrogen forms.But in technique, realize and in this passivation, also exist important problem.On existing production line, normally by the deuterium gas after through hole forms, annealed the deuterate at interface, still in the deuterate at execution interface, production line posterior segment.Another method is to reduce SiO by reducing the introducing of H in device making technics
2the Si-H number of keys of/Si interface also can significantly improve the NBTI performance of device.But due in the manufacturing process of device, in much technique, such as there is hydrogen in film deposit, etching, Implantation and cleaning etc., these hydrogen, under the driving of heat budget, can be diffused into SiO
2/ Si interface, is combined with Si dangling bonds and forms Si-H key, thereby aggravated NBTI effect
Therefore, how to provide a kind of process that can reduce to introduce in MOS device fabrication processes hydrogen, thereby reduce SiO
2the number of/Si interface Si-H key, and then can improve NBTI performance, become an important problem.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, and a kind of cmos device manufacture method that can reduce Negative Bias Temperature Instability is provided.
In order to realize above-mentioned technical purpose, according to the present invention, provide a kind of cmos device manufacture method that reduces Negative Bias Temperature Instability, it comprises:
First step carries out trap and injects formation P type trap and N-type trap in substrate;
Second step, makes grid oxic horizon at substrate surface;
Third step, carries out the deposit of grid layer on grid oxic horizon surface;
The 4th step, carries out photoetching to grid layer and forms PMOS grid to be formed on P type trap, forms NMOS grid on N-type trap;
The 5th step, makes respectively grid curb wall one at the side of PMOS grid and NMOS grid;
The 6th step, carries out light dope and is infused in and in P type trap, forms PMOS lightly-doped source drain structure, and in N-type trap, form NMOS lightly-doped source drain structure;
The 7th step, at device surface deposition silicon nitride film;
The 8th step, utilizes UV light to irradiate silicon chip;
The 9th step, makes and forms side wall two at grid curb wall one side;
The tenth step, carries out source and leaks injection formation, thereby form PMOS source-drain electrode in P type trap, forms NMOS source-drain electrode in N-type trap.
Preferably, described in reduce Negative Bias Temperature Instability cmos device manufacture method also comprise: the 11 step, for making medium before metal, through hole, metal plug and metal level.
Preferably, in first step, by phosphorus doping, form N trap, by B, adulterate and form P trap.
Preferably, in third step, the material of the grid layer of deposit is polysilicon.
Preferably, in the 5th step, the formation of grid curb wall one comprises the oxidation of polysilicon gate and the deposit of SiN.
Preferably, in the 6th step, light dope impurity is boron fluoride.
Preferably, in the 8th step, utilizing the temperature that UV light irradiates silicon chip is 450-480 ℃, and irradiation time is 100-150S.
Preferably, in the 9th step, the formation of side wall two comprises the deposit of oxide, the deposit of SiN and the etching of SiN.
Preferably, in the tenth step, by the doping of P type, inject the source-drain electrode that forms P type, described P type is doped to boron doping.
This method provides a kind of a kind of new technique of semiconductor integrated circuit technique in order to improve the NBTI effect of MOS device.In the semiconductor MOS device fabrication processes traditional, before dry etching forms second silicon nitride side wall and after silicon nitride film deposit, with UV light, wafer is irradiated to remove some the residual hydrogen atoms in silicon nitride film, hydrogen molecule and steam, the protium in the silicon nitride side wall of avoiding forming is diffused into grid oxic horizon lower surface SiO
2being combined with the Si of interface dangling bonds in/Si interface, reaches and reduce SiO
2/ Si interface Si-H number of keys, thus the NBTI performance in MOS device improved, and then improve cmos device performance.Improve technique with the NBTI of traditional technique and compare, this technique have technique simple, be easy to the features such as realization.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily to the present invention, there is more complete understanding and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows NBTI effect.
Fig. 2 A and Fig. 2 B schematically show Si/SiO
2the one-tenth bond structure at interface.
Fig. 3 schematically shows the flow chart of the cmos device manufacture method that reduces according to the preferred embodiment of the invention Negative Bias Temperature Instability.
Fig. 4-Figure 14 schematically shows the device sectional view of each step of the cmos device manufacture method that reduces according to the preferred embodiment of the invention Negative Bias Temperature Instability.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 3 schematically shows the flow chart of the cmos device manufacture method that reduces according to the preferred embodiment of the invention Negative Bias Temperature Instability.
As shown in Figure 3, the cmos device manufacture method that reduces according to the preferred embodiment of the invention Negative Bias Temperature Instability comprises:
First carry out first step S0, in substrate, carry out trap and inject formation P type trap 100 and N-type trap 200.In the present embodiment, by phosphorus doping, form N trap 200; By B, adulterate and form P trap 100, as shown in Figure 4.
Then carry out second step S1, at substrate surface, make grid oxic horizon 300, as shown in Figure 5.
Then continue third step S2, on grid oxic horizon 300 surfaces, carry out the deposit of grid layer 400, for example, the material of the grid layer 400 of deposit is polysilicon, as shown in Figure 6.
Then continue the 4th step S3, grid layer 400 is carried out to photoetching and to be formed on P type trap 100, form PMOS grid 401, on N-type trap 200, form NMOS grid 402, as shown in Figure 7.
Then continue the 5th step S4, at the side of PMOS grid 401 and NMOS grid 402, make respectively grid curb wall one 11,21; For example, the formation of grid curb wall one 11,12 comprises the oxidation of polysilicon gate and the deposit of SiN, as shown in Figure 8.
Then continue the 6th step S5, carry out light dope and be infused in and in P type trap 100, form PMOS lightly-doped source drain structure 12 and 13, and in N-type trap 200, form NMOS lightly-doped source drain structure 22 and 23, as shown in Figure 9.In the present embodiment, described light dope impurity is boron fluoride.
Then continue the 7th step S6, at device surface deposition silicon nitride film 500, as shown in figure 10
Then continue the 8th step S7, utilize UV light (ultraviolet light) to irradiate silicon chip, as shown in figure 11.In this example, the UV irradiation wafer by proper temperature and appropriate time is in order to remove some hydrogen atoms, hydrogen molecule and steam residual in silicon nitride film growth course.Wherein the appropraite condition of UV light is extremely important, preferably, temperature 450-480 ℃, the time, 100-150S was proper.Too low temperature is not enough to drive protium and steam: too high temperature is again than trap injects and lightly-doped source leaks the ion injecting activation and the diffusion that are easier to affect in previous process.The UV irradiation of above-mentioned condition can be removed hydrogen atom and the hydrogen molecule in silicon nitride film effectively, avoids silicon nitride side wall to form rear protium and is diffused into grid oxic horizon lower surface SiO
2being combined with the Si of interface dangling bonds in/Si interface, reaches and reduce SiO
2/ Si interface Si-H number of keys, thus the NBTI performance in MOS device improved, and then improve cmos device performance.
Then continue the 9th step S8, at grid curb wall one 11,21 sides, make and form side wall 2 14,14, as shown in figure 12.For example, the formation of side wall two comprises the deposit of oxide, the deposit of SiN and the etching of SiN.
Then continue the tenth step S9, carry out source and leak injection formation, thereby in P type trap 100, form PMOS source- drain electrode 15,16, in N-type trap 200, form NMOS source- drain electrode 25,26, as shown in figure 13.In the present embodiment, by the doping of P type, inject the source-drain electrode that forms P type, described P type is doped to boron doping.
Then the 11 step S10 be can continue, the front medium 600 of metal, through hole 700, metal plug and metal level (not shown) etc. finally made, as shown in figure 14.
In the metal-oxide-semiconductor manufacture method of above-mentioned improved NBTI, the light-struck temperature and time of UV in the 8th step S7 is extremely important: general temperature 450-480 ℃, the time, 100-150S was proper.This condition both there will not be can not drive away protium and steam, also there will not be too high temperature can affect trap (Well) injects and lightly-doped source leaks the ion of (LDD) injection activation and the diffusion in previous process.
This method provides a kind of a kind of new technique of semiconductor integrated circuit technique in order to improve the NBTI effect of MOS device.In the semiconductor MOS device fabrication processes traditional, before dry etching forms second silicon nitride side wall and after silicon nitride film deposit, with UV light, wafer is irradiated to remove some the residual hydrogen atoms in silicon nitride film, hydrogen molecule and steam, the protium in the silicon nitride side wall of avoiding forming is diffused into grid oxic horizon lower surface SiO
2being combined with the Si of interface dangling bonds in/Si interface, reaches and reduce SiO
2/ Si interface Si-H number of keys, thus the NBTI performance in MOS device improved, and then improve cmos device performance.Improve technique with the NBTI of traditional technique and compare, this technique have technique simple, be easy to the features such as realization.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the descriptions such as the term in specification " first ", " second ", " the 3rd " are only for distinguishing each assembly, element, step of specification etc., rather than for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclosure as above, yet above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (9)
1. a cmos device manufacture method that reduces Negative Bias Temperature Instability, is characterized in that comprising:
First step carries out trap and injects formation P type trap and N-type trap in substrate;
Second step, makes grid oxic horizon at substrate surface;
Third step, carries out the deposit of grid layer on grid oxic horizon surface;
The 4th step, carries out photoetching to grid layer and forms PMOS grid to be formed on P type trap, forms NMOS grid on N-type trap;
The 5th step, makes respectively grid curb wall one at the side of PMOS grid and NMOS grid;
The 6th step, carries out light dope and is infused in and in P type trap, forms PMOS lightly-doped source drain structure, and in N-type trap, form NMOS lightly-doped source drain structure;
The 7th step, at device surface deposition silicon nitride film;
The 8th step, utilizes UV light to irradiate silicon chip;
The 9th step, makes and forms side wall two at grid curb wall one side;
The tenth step, carries out source and leaks injection formation, thereby form PMOS source-drain electrode in P type trap, forms NMOS source-drain electrode in N-type trap.
2. the cmos device manufacture method that reduces Negative Bias Temperature Instability according to claim 1, characterized by further comprising: the 11 step, and for making medium before metal, through hole, metal plug and metal level.
3. the cmos device manufacture method that reduces Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in first step, by phosphorus doping, forms N trap, by B, is adulterated and is formed P trap.
4. the cmos device manufacture method that reduces Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in third step, the material of the grid layer of deposit is polysilicon.
5. the cmos device manufacture method that reduces Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the 5th step, the formation of grid curb wall one comprises the oxidation of polysilicon gate and the deposit of SiN.
6. the cmos device manufacture method that reduces Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the 6th step, light dope impurity is boron fluoride.
7. the cmos device manufacture method that reduces Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the 8th step, utilizing the temperature that UV light irradiates silicon chip is 450-480 ℃, and irradiation time is 100-150S.
8. the cmos device manufacture method that reduces Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the 9th step, the formation of side wall two comprises the deposit of oxide, the deposit of SiN and the etching of SiN.
9. the cmos device manufacture method that reduces Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the tenth step, by the doping of P type, injects the source-drain electrode that forms P type, and described P type is doped to boron doping.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972109A (en) * | 2014-05-21 | 2014-08-06 | 上海华力微电子有限公司 | Method for manufacturing MOS device capable of reducing negative bias temperature instability |
| CN105895634A (en) * | 2015-01-26 | 2016-08-24 | 中芯国际集成电路制造(上海)有限公司 | Cmos device and manufacturing method thereof |
| CN107039299A (en) * | 2016-11-10 | 2017-08-11 | 中国电子产品可靠性与环境试验研究所 | Metal-oxide-semiconductor parameter degradation circuit and metal-oxide-semiconductor parameter degradation early warning circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1405866A (en) * | 2001-03-01 | 2003-03-26 | 海力士半导体有限公司 | Transistor with super-short grating characteristic and storage device unit and their producing method |
| JP2008147325A (en) * | 2006-12-08 | 2008-06-26 | Renesas Technology Corp | Manufacturing method of semiconductor device |
| CN102412201A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Method for improving tensile stress of silicon nitride film in semiconductor devices |
| CN102709186A (en) * | 2012-01-12 | 2012-10-03 | 上海华力微电子有限公司 | Method for reducing negative bias temperature instability effect of device and manufacturing method of device |
-
2013
- 2013-10-18 CN CN201310492053.5A patent/CN103531542B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1405866A (en) * | 2001-03-01 | 2003-03-26 | 海力士半导体有限公司 | Transistor with super-short grating characteristic and storage device unit and their producing method |
| JP2008147325A (en) * | 2006-12-08 | 2008-06-26 | Renesas Technology Corp | Manufacturing method of semiconductor device |
| CN102412201A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Method for improving tensile stress of silicon nitride film in semiconductor devices |
| CN102709186A (en) * | 2012-01-12 | 2012-10-03 | 上海华力微电子有限公司 | Method for reducing negative bias temperature instability effect of device and manufacturing method of device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972109A (en) * | 2014-05-21 | 2014-08-06 | 上海华力微电子有限公司 | Method for manufacturing MOS device capable of reducing negative bias temperature instability |
| CN105895634A (en) * | 2015-01-26 | 2016-08-24 | 中芯国际集成电路制造(上海)有限公司 | Cmos device and manufacturing method thereof |
| CN107039299A (en) * | 2016-11-10 | 2017-08-11 | 中国电子产品可靠性与环境试验研究所 | Metal-oxide-semiconductor parameter degradation circuit and metal-oxide-semiconductor parameter degradation early warning circuit |
| CN107039299B (en) * | 2016-11-10 | 2019-10-18 | 中国电子产品可靠性与环境试验研究所 | Metal-oxide-semiconductor parameter degradation circuit and metal-oxide-semiconductor parameter degradation early warning circuit |
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