CN108268717B

CN108268717B - Novel grid-induced drain leakage current model

Info

Publication number: CN108268717B
Application number: CN201810049423.0A
Authority: CN
Inventors: 范象泉
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2018-01-18
Filing date: 2018-01-18
Publication date: 2021-07-23
Anticipated expiration: 2038-01-18
Also published as: CN108268717A

Abstract

The invention discloses a novel grid-induced drain leakageA current model, the expression of the current model being:

by the method and the device, a gate-induced drain leakage current model with higher accuracy can be realized.

Description

Novel grid-induced drain leakage current model

Technical Field

The invention relates to a current model, in particular to a novel grid-induced drain leakage current model.

Background

In the MOSFET device, when the gate-drain voltage Vdg at the gate-drain overlap region is large, band-to-band tunneling of electrons in silicon near the interface of the overlap region occurs between a valence band and a conduction band to form a current, namely GIDL tunneling current. As the gate oxide of MOS devices becomes thinner and thinner, the GIDL tunneling current increases sharply.

Research has shown that the leakage current causing static power dissipation in MOSFETs is mainly: source-to-Drain sub-threshold Leakage current, Gate-Induced-Drain-Leakage (GIDL) current occurring at the Gate-to-Drain overlap region, as shown in the figure below. Of these leakage currents, GIDL current is dominant in the leakage current when the device is in an off state or in a standby state in the circuit, and has a large influence on the reliability of the MOSFET.

In the prior art, the expression of the gate-induced drain leakage current model is as follows:

where f (l) ═ P3O, Vdg is the gate-drain voltage, P1, P2 are model parameters for all device dimensions, where P1 is the saturated GIDL current per unit voltage, in the range [0, infinity ], typically 3e-5A/V, P2 is the threshold voltage of the GIDL current, in the range [ negative infinity, positive infinity ], typically 0.5V, P3O is the activation energy of the GIDL current, in the range [0, infinity ], typically 30V.

However, the simulated value of the gate-induced drain leakage current model in the prior art deviates from the measured value significantly at higher gate-to-drain voltage Vdg, which is not suitable for application.

FIG. 1 shows the structure I of a long and short channel under a certain old process_GIDLCompare the figures. As can be seen from fig. 1, in a certain old process, the gate-induced drain leakage current (small cross-line) of the short channel (L ═ 0.55um) is slightly larger than that of the long channel (L ═ 20um) under the same drain-gate voltage Vdg.

FIG. 2 shows the structure of a long and short channel under a new process_GIDLCompare the figures. As shown in fig. 2, under the same drain-gate voltage Vdg, the gate-induced drain leakage current (small cross-line) of the short channel (L ═ 0.55um) is much larger than that of the long channel (L ═ 20um) (box-line) under the new process.

Disclosure of Invention

In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a novel gate-induced drain leakage current model to realize a gate-induced drain leakage current model with high accuracy.

To achieve the above and other objects, the present invention provides a novel gate-induced drain leakage current model, wherein the current model has an expression as follows:

where f (l) ═ P3O, Vdg is the gate-drain voltage, P1 is the saturated GIDL current per unit voltage, P2 is the threshold voltage of the GIDL current, and P3O is the activation energy of the GIDL current.

Further, f (l) ═ P3O-P3_L/L。

Further, the value range of P3O is [0,100], unit V.

Further, P3_LHas a value range of [0,10 ]^-4]In units of V × m.

Further, the air conditioner is provided with a fan,

wherein P3O is activation energy of GIDL current, P3N₁Short channel modifier for GIDL activation energy, P3N₂Channel length offset factor for GIDL activation energy short channel correction term, P3N₃Channel length coefficient of short channel correction term for GIDL activation energy, P3N₄The channel length index of the energy short channel correction term is activated for GIDL, and L is the channel length of the MOS transistor.

Further, the value range of P3O is [0,100], unit V.

Further, P3N₁Has a value range of [0,100]]The unit V.

Further, P3N₂Has a value range of [ -20,20 [)]Unit of

Further, P3N₃Has a value range of [ -10 ]⁹,0]。

Further, P3N₄Has a value range of [0,4 ]]。

Compared with the prior art, the invention realizes the purpose of obtaining more accurate grid-induced drain leakage current by establishing a novel grid-induced drain leakage current model.

Drawings

FIG. 1 shows the structure I of a long and short channel under a certain old process_GIDLComparing the images;

FIG. 2 shows the structure of a long and short channel under a new process_GIDLComparing the images;

FIG. 3 is a simulation comparison diagram of the present invention and the background art.

Detailed Description

Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.

In the present invention, the expression of the gate-induced drain current model is still:

in a preferred embodiment, f (l) ═ P3O-P3_L/L, wherein, P3_LThe energy short channel correction factor is activated for GIDL, and L is the channel length of the MOS transistor. Wherein, P3The value range of O is [0,100]]In units of V, P3_LHas a value range of [0,10 ]^-4]In units of V × m.

And in yet another preferred embodiment of the present invention,

wherein the value range of P3O is [0,100]]Unit V, P3N₁Short channel modifier for GIDL activation energy, P3N₂Channel length offset factor for GIDL activation energy short channel correction term, P3N₃Channel length coefficient of short channel correction term for GIDL activation energy, P3N₄Channel length index of short channel correction term for GIDL activation energy, L is channel length of MOS transistor, where P3N₁Has a value range of [0,100]]Unit V, P3N₂Has a value range of [ -20,20 [)]Unit of

P3N₃Has a value range of [ -10 ]⁹,0]Unitless, P3N₄Has a value range of [0,4 ]]And no unit.

FIG. 3 is a simulation comparison diagram of the present invention and the background art. As shown in fig. 3, for a long channel device (L ═ 20um), the simulated value of the gate-induced drain leakage current (dotted line, fourth thin line from top to bottom in the figure) of the background model of the related art is equivalent to the simulated value of the gate-induced drain leakage current (solid line, third thin line from top to bottom in the figure) of the model of the invention, and both are equivalent to the approximation of the measured value (block line); for a short channel device (L ═ 0.55um), compared with the actual measurement value (the square connecting line), the simulated value of the gate-induced drain leakage current (solid line, the first thin line from top to bottom in the figure) of the invented model is closer to the actual measurement value at higher gate leakage voltage Vdg than the simulated value of the gate-induced drain leakage current (dotted line, the second thin line from top to bottom in the figure) of the background model in the prior art, and the simulated value of the background model in the prior art deviates from the actual measurement value at higher gate leakage voltage Vdg, which is not favorable for application.

Therefore, the invention realizes the purpose of obtaining more accurate grid-induced drain leakage current by establishing a novel grid-induced drain leakage current model.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims

1. A method for establishing a novel grid-induced drain leakage current model is characterized in that the expression of the current model is as follows:

wherein f (L) ═ P3O-P3_LVdg is gate-drain voltage, P1 is saturated GIDL current per unit voltage, P2 is threshold voltage of GIDL current, P3O is activation energy of GIDL current, and P3_LThe energy short channel correction factor is activated for GIDL, and L is the channel length of the MOS transistor.

2. The method of modeling gate-induced drain leakage current as claimed in claim 1, wherein: the value of P3O is in the range of [0,100] in V.

3. The method of modeling gate-induced drain leakage current as claimed in claim 1, wherein: p3_LHas a value range of [0,10 ]^-4]In units of V × m.

4. The method of modeling gate-induced drain leakage current as claimed in claim 1, wherein:

5. The method for modeling gate-induced drain leakage current according to claim 4, wherein: the value of P3O is in the range of [0,100] in V.

6. The method for modeling gate-induced drain leakage current according to claim 4, wherein: P3N₁Has a value range of [0,100]]The unit V.

7. The method for modeling gate-induced drain leakage current according to claim 4, wherein: P3N₂Has a value range of [ -20,20 [)]Unit of

8. The method for modeling gate-induced drain leakage current according to claim 4, wherein: P3N₃Has a value range of [ -10 ]⁹,0]。

9. The method for modeling gate-induced drain leakage current according to claim 4, wherein: P3N₄Has a value range of [0,4 ]]。